1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/ADT/FoldingSet.h"
16 #include "llvm/ADT/Hashing.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/CodeGen/MachineConstantPool.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/DebugInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/InlineAsm.h"
28 #include "llvm/IR/LLVMContext.h"
29 #include "llvm/IR/Metadata.h"
30 #include "llvm/IR/Module.h"
31 #include "llvm/IR/Type.h"
32 #include "llvm/IR/Value.h"
33 #include "llvm/MC/MCInstrDesc.h"
34 #include "llvm/MC/MCSymbol.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Target/TargetRegisterInfo.h"
42 #include "llvm/Target/TargetSubtargetInfo.h"
45 //===----------------------------------------------------------------------===//
46 // MachineOperand Implementation
47 //===----------------------------------------------------------------------===//
49 void MachineOperand::setReg(unsigned Reg) {
50 if (getReg() == Reg) return; // No change.
52 // Otherwise, we have to change the register. If this operand is embedded
53 // into a machine function, we need to update the old and new register's
55 if (MachineInstr *MI = getParent())
56 if (MachineBasicBlock *MBB = MI->getParent())
57 if (MachineFunction *MF = MBB->getParent()) {
58 MachineRegisterInfo &MRI = MF->getRegInfo();
59 MRI.removeRegOperandFromUseList(this);
60 SmallContents.RegNo = Reg;
61 MRI.addRegOperandToUseList(this);
65 // Otherwise, just change the register, no problem. :)
66 SmallContents.RegNo = Reg;
69 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
70 const TargetRegisterInfo &TRI) {
71 assert(TargetRegisterInfo::isVirtualRegister(Reg));
72 if (SubIdx && getSubReg())
73 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
79 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
80 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
82 Reg = TRI.getSubReg(Reg, getSubReg());
83 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
84 // That won't happen in legal code.
90 /// Change a def to a use, or a use to a def.
91 void MachineOperand::setIsDef(bool Val) {
92 assert(isReg() && "Wrong MachineOperand accessor");
93 assert((!Val || !isDebug()) && "Marking a debug operation as def");
96 // MRI may keep uses and defs in different list positions.
97 if (MachineInstr *MI = getParent())
98 if (MachineBasicBlock *MBB = MI->getParent())
99 if (MachineFunction *MF = MBB->getParent()) {
100 MachineRegisterInfo &MRI = MF->getRegInfo();
101 MRI.removeRegOperandFromUseList(this);
103 MRI.addRegOperandToUseList(this);
109 // If this operand is currently a register operand, and if this is in a
110 // function, deregister the operand from the register's use/def list.
111 void MachineOperand::removeRegFromUses() {
112 if (!isReg() || !isOnRegUseList())
115 if (MachineInstr *MI = getParent()) {
116 if (MachineBasicBlock *MBB = MI->getParent()) {
117 if (MachineFunction *MF = MBB->getParent())
118 MF->getRegInfo().removeRegOperandFromUseList(this);
123 /// ChangeToImmediate - Replace this operand with a new immediate operand of
124 /// the specified value. If an operand is known to be an immediate already,
125 /// the setImm method should be used.
126 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
127 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
131 OpKind = MO_Immediate;
132 Contents.ImmVal = ImmVal;
135 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
136 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
140 OpKind = MO_FPImmediate;
141 Contents.CFP = FPImm;
144 void MachineOperand::ChangeToES(const char *SymName, unsigned char TargetFlags) {
145 assert((!isReg() || !isTied()) &&
146 "Cannot change a tied operand into an external symbol");
150 OpKind = MO_ExternalSymbol;
151 Contents.OffsetedInfo.Val.SymbolName = SymName;
152 setOffset(0); // Offset is always 0.
153 setTargetFlags(TargetFlags);
156 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
157 assert((!isReg() || !isTied()) &&
158 "Cannot change a tied operand into an MCSymbol");
162 OpKind = MO_MCSymbol;
166 /// ChangeToRegister - Replace this operand with a new register operand of
167 /// the specified value. If an operand is known to be an register already,
168 /// the setReg method should be used.
169 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
170 bool isKill, bool isDead, bool isUndef,
172 MachineRegisterInfo *RegInfo = nullptr;
173 if (MachineInstr *MI = getParent())
174 if (MachineBasicBlock *MBB = MI->getParent())
175 if (MachineFunction *MF = MBB->getParent())
176 RegInfo = &MF->getRegInfo();
177 // If this operand is already a register operand, remove it from the
178 // register's use/def lists.
179 bool WasReg = isReg();
180 if (RegInfo && WasReg)
181 RegInfo->removeRegOperandFromUseList(this);
183 // Change this to a register and set the reg#.
184 OpKind = MO_Register;
185 SmallContents.RegNo = Reg;
186 SubReg_TargetFlags = 0;
192 IsInternalRead = false;
193 IsEarlyClobber = false;
195 // Ensure isOnRegUseList() returns false.
196 Contents.Reg.Prev = nullptr;
197 // Preserve the tie when the operand was already a register.
201 // If this operand is embedded in a function, add the operand to the
202 // register's use/def list.
204 RegInfo->addRegOperandToUseList(this);
207 /// isIdenticalTo - Return true if this operand is identical to the specified
208 /// operand. Note that this should stay in sync with the hash_value overload
210 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
211 if (getType() != Other.getType() ||
212 getTargetFlags() != Other.getTargetFlags())
216 case MachineOperand::MO_Register:
217 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
218 getSubReg() == Other.getSubReg();
219 case MachineOperand::MO_Immediate:
220 return getImm() == Other.getImm();
221 case MachineOperand::MO_CImmediate:
222 return getCImm() == Other.getCImm();
223 case MachineOperand::MO_FPImmediate:
224 return getFPImm() == Other.getFPImm();
225 case MachineOperand::MO_MachineBasicBlock:
226 return getMBB() == Other.getMBB();
227 case MachineOperand::MO_FrameIndex:
228 return getIndex() == Other.getIndex();
229 case MachineOperand::MO_ConstantPoolIndex:
230 case MachineOperand::MO_TargetIndex:
231 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
232 case MachineOperand::MO_JumpTableIndex:
233 return getIndex() == Other.getIndex();
234 case MachineOperand::MO_GlobalAddress:
235 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
236 case MachineOperand::MO_ExternalSymbol:
237 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
238 getOffset() == Other.getOffset();
239 case MachineOperand::MO_BlockAddress:
240 return getBlockAddress() == Other.getBlockAddress() &&
241 getOffset() == Other.getOffset();
242 case MachineOperand::MO_RegisterMask:
243 case MachineOperand::MO_RegisterLiveOut:
244 return getRegMask() == Other.getRegMask();
245 case MachineOperand::MO_MCSymbol:
246 return getMCSymbol() == Other.getMCSymbol();
247 case MachineOperand::MO_CFIIndex:
248 return getCFIIndex() == Other.getCFIIndex();
249 case MachineOperand::MO_Metadata:
250 return getMetadata() == Other.getMetadata();
252 llvm_unreachable("Invalid machine operand type");
255 // Note: this must stay exactly in sync with isIdenticalTo above.
256 hash_code llvm::hash_value(const MachineOperand &MO) {
257 switch (MO.getType()) {
258 case MachineOperand::MO_Register:
259 // Register operands don't have target flags.
260 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
261 case MachineOperand::MO_Immediate:
262 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
263 case MachineOperand::MO_CImmediate:
264 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
265 case MachineOperand::MO_FPImmediate:
266 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
267 case MachineOperand::MO_MachineBasicBlock:
268 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
269 case MachineOperand::MO_FrameIndex:
270 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
271 case MachineOperand::MO_ConstantPoolIndex:
272 case MachineOperand::MO_TargetIndex:
273 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
275 case MachineOperand::MO_JumpTableIndex:
276 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
277 case MachineOperand::MO_ExternalSymbol:
278 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
280 case MachineOperand::MO_GlobalAddress:
281 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
283 case MachineOperand::MO_BlockAddress:
284 return hash_combine(MO.getType(), MO.getTargetFlags(),
285 MO.getBlockAddress(), MO.getOffset());
286 case MachineOperand::MO_RegisterMask:
287 case MachineOperand::MO_RegisterLiveOut:
288 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
289 case MachineOperand::MO_Metadata:
290 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
291 case MachineOperand::MO_MCSymbol:
292 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
293 case MachineOperand::MO_CFIIndex:
294 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
296 llvm_unreachable("Invalid machine operand type");
299 /// print - Print the specified machine operand.
301 void MachineOperand::print(raw_ostream &OS,
302 const TargetRegisterInfo *TRI) const {
304 case MachineOperand::MO_Register:
305 OS << PrintReg(getReg(), TRI, getSubReg());
307 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
308 isInternalRead() || isEarlyClobber() || isTied()) {
310 bool NeedComma = false;
312 if (NeedComma) OS << ',';
313 if (isEarlyClobber())
314 OS << "earlyclobber,";
319 // <def,read-undef> only makes sense when getSubReg() is set.
320 // Don't clutter the output otherwise.
321 if (isUndef() && getSubReg())
323 } else if (isImplicit()) {
329 if (NeedComma) OS << ',';
334 if (NeedComma) OS << ',';
338 if (isUndef() && isUse()) {
339 if (NeedComma) OS << ',';
343 if (isInternalRead()) {
344 if (NeedComma) OS << ',';
349 if (NeedComma) OS << ',';
352 OS << unsigned(TiedTo - 1);
357 case MachineOperand::MO_Immediate:
360 case MachineOperand::MO_CImmediate:
361 getCImm()->getValue().print(OS, false);
363 case MachineOperand::MO_FPImmediate:
364 if (getFPImm()->getType()->isFloatTy())
365 OS << getFPImm()->getValueAPF().convertToFloat();
367 OS << getFPImm()->getValueAPF().convertToDouble();
369 case MachineOperand::MO_MachineBasicBlock:
370 OS << "<BB#" << getMBB()->getNumber() << ">";
372 case MachineOperand::MO_FrameIndex:
373 OS << "<fi#" << getIndex() << '>';
375 case MachineOperand::MO_ConstantPoolIndex:
376 OS << "<cp#" << getIndex();
377 if (getOffset()) OS << "+" << getOffset();
380 case MachineOperand::MO_TargetIndex:
381 OS << "<ti#" << getIndex();
382 if (getOffset()) OS << "+" << getOffset();
385 case MachineOperand::MO_JumpTableIndex:
386 OS << "<jt#" << getIndex() << '>';
388 case MachineOperand::MO_GlobalAddress:
390 getGlobal()->printAsOperand(OS, /*PrintType=*/false);
391 if (getOffset()) OS << "+" << getOffset();
394 case MachineOperand::MO_ExternalSymbol:
395 OS << "<es:" << getSymbolName();
396 if (getOffset()) OS << "+" << getOffset();
399 case MachineOperand::MO_BlockAddress:
401 getBlockAddress()->printAsOperand(OS, /*PrintType=*/false);
402 if (getOffset()) OS << "+" << getOffset();
405 case MachineOperand::MO_RegisterMask:
408 case MachineOperand::MO_RegisterLiveOut:
409 OS << "<regliveout>";
411 case MachineOperand::MO_Metadata:
413 getMetadata()->printAsOperand(OS);
416 case MachineOperand::MO_MCSymbol:
417 OS << "<MCSym=" << *getMCSymbol() << '>';
419 case MachineOperand::MO_CFIIndex:
420 OS << "<call frame instruction>";
424 if (unsigned TF = getTargetFlags())
425 OS << "[TF=" << TF << ']';
428 //===----------------------------------------------------------------------===//
429 // MachineMemOperand Implementation
430 //===----------------------------------------------------------------------===//
432 /// getAddrSpace - Return the LLVM IR address space number that this pointer
434 unsigned MachinePointerInfo::getAddrSpace() const {
435 if (V.isNull() || V.is<const PseudoSourceValue*>()) return 0;
436 return cast<PointerType>(V.get<const Value*>()->getType())->getAddressSpace();
439 /// getConstantPool - Return a MachinePointerInfo record that refers to the
441 MachinePointerInfo MachinePointerInfo::getConstantPool() {
442 return MachinePointerInfo(PseudoSourceValue::getConstantPool());
445 /// getFixedStack - Return a MachinePointerInfo record that refers to the
446 /// the specified FrameIndex.
447 MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
448 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
451 MachinePointerInfo MachinePointerInfo::getJumpTable() {
452 return MachinePointerInfo(PseudoSourceValue::getJumpTable());
455 MachinePointerInfo MachinePointerInfo::getGOT() {
456 return MachinePointerInfo(PseudoSourceValue::getGOT());
459 MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
460 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
463 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
464 uint64_t s, unsigned int a,
465 const AAMDNodes &AAInfo,
466 const MDNode *Ranges)
467 : PtrInfo(ptrinfo), Size(s),
468 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
469 AAInfo(AAInfo), Ranges(Ranges) {
470 assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue*>() ||
471 isa<PointerType>(PtrInfo.V.get<const Value*>()->getType())) &&
472 "invalid pointer value");
473 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
474 assert((isLoad() || isStore()) && "Not a load/store!");
477 /// Profile - Gather unique data for the object.
479 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
480 ID.AddInteger(getOffset());
482 ID.AddPointer(getOpaqueValue());
483 ID.AddInteger(Flags);
486 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
487 // The Value and Offset may differ due to CSE. But the flags and size
488 // should be the same.
489 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
490 assert(MMO->getSize() == getSize() && "Size mismatch!");
492 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
493 // Update the alignment value.
494 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
495 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
496 // Also update the base and offset, because the new alignment may
497 // not be applicable with the old ones.
498 PtrInfo = MMO->PtrInfo;
502 /// getAlignment - Return the minimum known alignment in bytes of the
503 /// actual memory reference.
504 uint64_t MachineMemOperand::getAlignment() const {
505 return MinAlign(getBaseAlignment(), getOffset());
508 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
509 assert((MMO.isLoad() || MMO.isStore()) &&
510 "SV has to be a load, store or both.");
512 if (MMO.isVolatile())
521 // Print the address information.
523 if (const Value *V = MMO.getValue())
524 V->printAsOperand(OS, /*PrintType=*/false);
525 else if (const PseudoSourceValue *PSV = MMO.getPseudoValue())
526 PSV->printCustom(OS);
530 unsigned AS = MMO.getAddrSpace();
532 OS << "(addrspace=" << AS << ')';
534 // If the alignment of the memory reference itself differs from the alignment
535 // of the base pointer, print the base alignment explicitly, next to the base
537 if (MMO.getBaseAlignment() != MMO.getAlignment())
538 OS << "(align=" << MMO.getBaseAlignment() << ")";
540 if (MMO.getOffset() != 0)
541 OS << "+" << MMO.getOffset();
544 // Print the alignment of the reference.
545 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
546 MMO.getBaseAlignment() != MMO.getSize())
547 OS << "(align=" << MMO.getAlignment() << ")";
550 if (const MDNode *TBAAInfo = MMO.getAAInfo().TBAA) {
552 if (TBAAInfo->getNumOperands() > 0)
553 TBAAInfo->getOperand(0)->printAsOperand(OS);
559 // Print AA scope info.
560 if (const MDNode *ScopeInfo = MMO.getAAInfo().Scope) {
561 OS << "(alias.scope=";
562 if (ScopeInfo->getNumOperands() > 0)
563 for (unsigned i = 0, ie = ScopeInfo->getNumOperands(); i != ie; ++i) {
564 ScopeInfo->getOperand(i)->printAsOperand(OS);
573 // Print AA noalias scope info.
574 if (const MDNode *NoAliasInfo = MMO.getAAInfo().NoAlias) {
576 if (NoAliasInfo->getNumOperands() > 0)
577 for (unsigned i = 0, ie = NoAliasInfo->getNumOperands(); i != ie; ++i) {
578 NoAliasInfo->getOperand(i)->printAsOperand(OS);
587 // Print nontemporal info.
588 if (MMO.isNonTemporal())
589 OS << "(nontemporal)";
594 //===----------------------------------------------------------------------===//
595 // MachineInstr Implementation
596 //===----------------------------------------------------------------------===//
598 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
599 if (MCID->ImplicitDefs)
600 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
601 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
602 if (MCID->ImplicitUses)
603 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
604 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
607 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
608 /// implicit operands. It reserves space for the number of operands specified by
610 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
611 DebugLoc dl, bool NoImp)
612 : MCID(&tid), Parent(nullptr), Operands(nullptr), NumOperands(0), Flags(0),
613 AsmPrinterFlags(0), NumMemRefs(0), MemRefs(nullptr),
614 debugLoc(std::move(dl)) {
615 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
617 // Reserve space for the expected number of operands.
618 if (unsigned NumOps = MCID->getNumOperands() +
619 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
620 CapOperands = OperandCapacity::get(NumOps);
621 Operands = MF.allocateOperandArray(CapOperands);
625 addImplicitDefUseOperands(MF);
628 /// MachineInstr ctor - Copies MachineInstr arg exactly
630 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
631 : MCID(&MI.getDesc()), Parent(nullptr), Operands(nullptr), NumOperands(0),
632 Flags(0), AsmPrinterFlags(0),
633 NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
634 debugLoc(MI.getDebugLoc()) {
635 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
637 CapOperands = OperandCapacity::get(MI.getNumOperands());
638 Operands = MF.allocateOperandArray(CapOperands);
641 for (const MachineOperand &MO : MI.operands())
644 // Copy all the sensible flags.
648 /// getRegInfo - If this instruction is embedded into a MachineFunction,
649 /// return the MachineRegisterInfo object for the current function, otherwise
651 MachineRegisterInfo *MachineInstr::getRegInfo() {
652 if (MachineBasicBlock *MBB = getParent())
653 return &MBB->getParent()->getRegInfo();
657 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
658 /// this instruction from their respective use lists. This requires that the
659 /// operands already be on their use lists.
660 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
661 for (MachineOperand &MO : operands())
663 MRI.removeRegOperandFromUseList(&MO);
666 /// AddRegOperandsToUseLists - Add all of the register operands in
667 /// this instruction from their respective use lists. This requires that the
668 /// operands not be on their use lists yet.
669 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
670 for (MachineOperand &MO : operands())
672 MRI.addRegOperandToUseList(&MO);
675 void MachineInstr::addOperand(const MachineOperand &Op) {
676 MachineBasicBlock *MBB = getParent();
677 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
678 MachineFunction *MF = MBB->getParent();
679 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
683 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
684 /// ranges. If MRI is non-null also update use-def chains.
685 static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
686 unsigned NumOps, MachineRegisterInfo *MRI) {
688 return MRI->moveOperands(Dst, Src, NumOps);
690 // MachineOperand is a trivially copyable type so we can just use memmove.
691 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
694 /// addOperand - Add the specified operand to the instruction. If it is an
695 /// implicit operand, it is added to the end of the operand list. If it is
696 /// an explicit operand it is added at the end of the explicit operand list
697 /// (before the first implicit operand).
698 void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
699 assert(MCID && "Cannot add operands before providing an instr descriptor");
701 // Check if we're adding one of our existing operands.
702 if (&Op >= Operands && &Op < Operands + NumOperands) {
703 // This is unusual: MI->addOperand(MI->getOperand(i)).
704 // If adding Op requires reallocating or moving existing operands around,
705 // the Op reference could go stale. Support it by copying Op.
706 MachineOperand CopyOp(Op);
707 return addOperand(MF, CopyOp);
710 // Find the insert location for the new operand. Implicit registers go at
711 // the end, everything else goes before the implicit regs.
713 // FIXME: Allow mixed explicit and implicit operands on inline asm.
714 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
715 // implicit-defs, but they must not be moved around. See the FIXME in
717 unsigned OpNo = getNumOperands();
718 bool isImpReg = Op.isReg() && Op.isImplicit();
719 if (!isImpReg && !isInlineAsm()) {
720 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
722 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
727 bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
728 // OpNo now points as the desired insertion point. Unless this is a variadic
729 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
730 // RegMask operands go between the explicit and implicit operands.
731 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
732 OpNo < MCID->getNumOperands() || isMetaDataOp) &&
733 "Trying to add an operand to a machine instr that is already done!");
736 MachineRegisterInfo *MRI = getRegInfo();
738 // Determine if the Operands array needs to be reallocated.
739 // Save the old capacity and operand array.
740 OperandCapacity OldCap = CapOperands;
741 MachineOperand *OldOperands = Operands;
742 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
743 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
744 Operands = MF.allocateOperandArray(CapOperands);
745 // Move the operands before the insertion point.
747 moveOperands(Operands, OldOperands, OpNo, MRI);
750 // Move the operands following the insertion point.
751 if (OpNo != NumOperands)
752 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
756 // Deallocate the old operand array.
757 if (OldOperands != Operands && OldOperands)
758 MF.deallocateOperandArray(OldCap, OldOperands);
760 // Copy Op into place. It still needs to be inserted into the MRI use lists.
761 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
762 NewMO->ParentMI = this;
764 // When adding a register operand, tell MRI about it.
765 if (NewMO->isReg()) {
766 // Ensure isOnRegUseList() returns false, regardless of Op's status.
767 NewMO->Contents.Reg.Prev = nullptr;
768 // Ignore existing ties. This is not a property that can be copied.
770 // Add the new operand to MRI, but only for instructions in an MBB.
772 MRI->addRegOperandToUseList(NewMO);
773 // The MCID operand information isn't accurate until we start adding
774 // explicit operands. The implicit operands are added first, then the
775 // explicits are inserted before them.
777 // Tie uses to defs as indicated in MCInstrDesc.
778 if (NewMO->isUse()) {
779 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
781 tieOperands(DefIdx, OpNo);
783 // If the register operand is flagged as early, mark the operand as such.
784 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
785 NewMO->setIsEarlyClobber(true);
790 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
791 /// fewer operand than it started with.
793 void MachineInstr::RemoveOperand(unsigned OpNo) {
794 assert(OpNo < getNumOperands() && "Invalid operand number");
795 untieRegOperand(OpNo);
798 // Moving tied operands would break the ties.
799 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
800 if (Operands[i].isReg())
801 assert(!Operands[i].isTied() && "Cannot move tied operands");
804 MachineRegisterInfo *MRI = getRegInfo();
805 if (MRI && Operands[OpNo].isReg())
806 MRI->removeRegOperandFromUseList(Operands + OpNo);
808 // Don't call the MachineOperand destructor. A lot of this code depends on
809 // MachineOperand having a trivial destructor anyway, and adding a call here
810 // wouldn't make it 'destructor-correct'.
812 if (unsigned N = NumOperands - 1 - OpNo)
813 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
817 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
818 /// This function should be used only occasionally. The setMemRefs function
819 /// is the primary method for setting up a MachineInstr's MemRefs list.
820 void MachineInstr::addMemOperand(MachineFunction &MF,
821 MachineMemOperand *MO) {
822 mmo_iterator OldMemRefs = MemRefs;
823 unsigned OldNumMemRefs = NumMemRefs;
825 unsigned NewNum = NumMemRefs + 1;
826 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
828 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
829 NewMemRefs[NewNum - 1] = MO;
830 setMemRefs(NewMemRefs, NewMemRefs + NewNum);
833 bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
834 assert(!isBundledWithPred() && "Must be called on bundle header");
835 for (MachineBasicBlock::const_instr_iterator MII = this;; ++MII) {
836 if (MII->getDesc().getFlags() & Mask) {
837 if (Type == AnyInBundle)
840 if (Type == AllInBundle && !MII->isBundle())
843 // This was the last instruction in the bundle.
844 if (!MII->isBundledWithSucc())
845 return Type == AllInBundle;
849 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
850 MICheckType Check) const {
851 // If opcodes or number of operands are not the same then the two
852 // instructions are obviously not identical.
853 if (Other->getOpcode() != getOpcode() ||
854 Other->getNumOperands() != getNumOperands())
858 // Both instructions are bundles, compare MIs inside the bundle.
859 MachineBasicBlock::const_instr_iterator I1 = *this;
860 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
861 MachineBasicBlock::const_instr_iterator I2 = *Other;
862 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
863 while (++I1 != E1 && I1->isInsideBundle()) {
865 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
870 // Check operands to make sure they match.
871 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
872 const MachineOperand &MO = getOperand(i);
873 const MachineOperand &OMO = Other->getOperand(i);
875 if (!MO.isIdenticalTo(OMO))
880 // Clients may or may not want to ignore defs when testing for equality.
881 // For example, machine CSE pass only cares about finding common
882 // subexpressions, so it's safe to ignore virtual register defs.
884 if (Check == IgnoreDefs)
886 else if (Check == IgnoreVRegDefs) {
887 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
888 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
889 if (MO.getReg() != OMO.getReg())
892 if (!MO.isIdenticalTo(OMO))
894 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
898 if (!MO.isIdenticalTo(OMO))
900 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
904 // If DebugLoc does not match then two dbg.values are not identical.
906 if (getDebugLoc() && Other->getDebugLoc() &&
907 getDebugLoc() != Other->getDebugLoc())
912 MachineInstr *MachineInstr::removeFromParent() {
913 assert(getParent() && "Not embedded in a basic block!");
914 return getParent()->remove(this);
917 MachineInstr *MachineInstr::removeFromBundle() {
918 assert(getParent() && "Not embedded in a basic block!");
919 return getParent()->remove_instr(this);
922 void MachineInstr::eraseFromParent() {
923 assert(getParent() && "Not embedded in a basic block!");
924 getParent()->erase(this);
927 void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
928 assert(getParent() && "Not embedded in a basic block!");
929 MachineBasicBlock *MBB = getParent();
930 MachineFunction *MF = MBB->getParent();
931 assert(MF && "Not embedded in a function!");
933 MachineInstr *MI = (MachineInstr *)this;
934 MachineRegisterInfo &MRI = MF->getRegInfo();
936 for (const MachineOperand &MO : MI->operands()) {
937 if (!MO.isReg() || !MO.isDef())
939 unsigned Reg = MO.getReg();
940 if (!TargetRegisterInfo::isVirtualRegister(Reg))
942 MRI.markUsesInDebugValueAsUndef(Reg);
944 MI->eraseFromParent();
947 void MachineInstr::eraseFromBundle() {
948 assert(getParent() && "Not embedded in a basic block!");
949 getParent()->erase_instr(this);
952 /// getNumExplicitOperands - Returns the number of non-implicit operands.
954 unsigned MachineInstr::getNumExplicitOperands() const {
955 unsigned NumOperands = MCID->getNumOperands();
956 if (!MCID->isVariadic())
959 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
960 const MachineOperand &MO = getOperand(i);
961 if (!MO.isReg() || !MO.isImplicit())
967 void MachineInstr::bundleWithPred() {
968 assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
969 setFlag(BundledPred);
970 MachineBasicBlock::instr_iterator Pred = this;
972 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
973 Pred->setFlag(BundledSucc);
976 void MachineInstr::bundleWithSucc() {
977 assert(!isBundledWithSucc() && "MI is already bundled with its successor");
978 setFlag(BundledSucc);
979 MachineBasicBlock::instr_iterator Succ = this;
981 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
982 Succ->setFlag(BundledPred);
985 void MachineInstr::unbundleFromPred() {
986 assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
987 clearFlag(BundledPred);
988 MachineBasicBlock::instr_iterator Pred = this;
990 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
991 Pred->clearFlag(BundledSucc);
994 void MachineInstr::unbundleFromSucc() {
995 assert(isBundledWithSucc() && "MI isn't bundled with its successor");
996 clearFlag(BundledSucc);
997 MachineBasicBlock::instr_iterator Succ = this;
999 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
1000 Succ->clearFlag(BundledPred);
1003 bool MachineInstr::isStackAligningInlineAsm() const {
1004 if (isInlineAsm()) {
1005 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1006 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1012 InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
1013 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
1014 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1015 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
1018 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
1019 unsigned *GroupNo) const {
1020 assert(isInlineAsm() && "Expected an inline asm instruction");
1021 assert(OpIdx < getNumOperands() && "OpIdx out of range");
1023 // Ignore queries about the initial operands.
1024 if (OpIdx < InlineAsm::MIOp_FirstOperand)
1029 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1031 const MachineOperand &FlagMO = getOperand(i);
1032 // If we reach the implicit register operands, stop looking.
1033 if (!FlagMO.isImm())
1035 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1036 if (i + NumOps > OpIdx) {
1046 const TargetRegisterClass*
1047 MachineInstr::getRegClassConstraint(unsigned OpIdx,
1048 const TargetInstrInfo *TII,
1049 const TargetRegisterInfo *TRI) const {
1050 assert(getParent() && "Can't have an MBB reference here!");
1051 assert(getParent()->getParent() && "Can't have an MF reference here!");
1052 const MachineFunction &MF = *getParent()->getParent();
1054 // Most opcodes have fixed constraints in their MCInstrDesc.
1056 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
1058 if (!getOperand(OpIdx).isReg())
1061 // For tied uses on inline asm, get the constraint from the def.
1063 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
1066 // Inline asm stores register class constraints in the flag word.
1067 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
1071 unsigned Flag = getOperand(FlagIdx).getImm();
1073 if (InlineAsm::hasRegClassConstraint(Flag, RCID))
1074 return TRI->getRegClass(RCID);
1076 // Assume that all registers in a memory operand are pointers.
1077 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
1078 return TRI->getPointerRegClass(MF);
1083 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
1084 unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
1085 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
1086 // Check every operands inside the bundle if we have
1089 for (ConstMIBundleOperands OpndIt(this); OpndIt.isValid() && CurRC;
1091 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
1092 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
1094 // Otherwise, just check the current operands.
1095 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
1096 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
1100 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
1101 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1102 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
1103 assert(CurRC && "Invalid initial register class");
1104 // Check if Reg is constrained by some of its use/def from MI.
1105 const MachineOperand &MO = getOperand(OpIdx);
1106 if (!MO.isReg() || MO.getReg() != Reg)
1108 // If yes, accumulate the constraints through the operand.
1109 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
1112 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
1113 unsigned OpIdx, const TargetRegisterClass *CurRC,
1114 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
1115 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
1116 const MachineOperand &MO = getOperand(OpIdx);
1117 assert(MO.isReg() &&
1118 "Cannot get register constraints for non-register operand");
1119 assert(CurRC && "Invalid initial register class");
1120 if (unsigned SubIdx = MO.getSubReg()) {
1122 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
1124 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
1126 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
1130 /// Return the number of instructions inside the MI bundle, not counting the
1131 /// header instruction.
1132 unsigned MachineInstr::getBundleSize() const {
1133 MachineBasicBlock::const_instr_iterator I = this;
1135 while (I->isBundledWithSucc())
1140 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1141 /// the specific register or -1 if it is not found. It further tightens
1142 /// the search criteria to a use that kills the register if isKill is true.
1143 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
1144 const TargetRegisterInfo *TRI) const {
1145 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1146 const MachineOperand &MO = getOperand(i);
1147 if (!MO.isReg() || !MO.isUse())
1149 unsigned MOReg = MO.getReg();
1154 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1155 TargetRegisterInfo::isPhysicalRegister(Reg) &&
1156 TRI->isSubRegister(MOReg, Reg)))
1157 if (!isKill || MO.isKill())
1163 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1164 /// indicating if this instruction reads or writes Reg. This also considers
1165 /// partial defines.
1166 std::pair<bool,bool>
1167 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1168 SmallVectorImpl<unsigned> *Ops) const {
1169 bool PartDef = false; // Partial redefine.
1170 bool FullDef = false; // Full define.
1173 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1174 const MachineOperand &MO = getOperand(i);
1175 if (!MO.isReg() || MO.getReg() != Reg)
1180 Use |= !MO.isUndef();
1181 else if (MO.getSubReg() && !MO.isUndef())
1182 // A partial <def,undef> doesn't count as reading the register.
1187 // A partial redefine uses Reg unless there is also a full define.
1188 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1191 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1192 /// the specified register or -1 if it is not found. If isDead is true, defs
1193 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1194 /// also checks if there is a def of a super-register.
1196 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1197 const TargetRegisterInfo *TRI) const {
1198 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1199 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1200 const MachineOperand &MO = getOperand(i);
1201 // Accept regmask operands when Overlap is set.
1202 // Ignore them when looking for a specific def operand (Overlap == false).
1203 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1205 if (!MO.isReg() || !MO.isDef())
1207 unsigned MOReg = MO.getReg();
1208 bool Found = (MOReg == Reg);
1209 if (!Found && TRI && isPhys &&
1210 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1212 Found = TRI->regsOverlap(MOReg, Reg);
1214 Found = TRI->isSubRegister(MOReg, Reg);
1216 if (Found && (!isDead || MO.isDead()))
1222 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1223 /// operand list that is used to represent the predicate. It returns -1 if
1225 int MachineInstr::findFirstPredOperandIdx() const {
1226 // Don't call MCID.findFirstPredOperandIdx() because this variant
1227 // is sometimes called on an instruction that's not yet complete, and
1228 // so the number of operands is less than the MCID indicates. In
1229 // particular, the PTX target does this.
1230 const MCInstrDesc &MCID = getDesc();
1231 if (MCID.isPredicable()) {
1232 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1233 if (MCID.OpInfo[i].isPredicate())
1240 // MachineOperand::TiedTo is 4 bits wide.
1241 const unsigned TiedMax = 15;
1243 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1245 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1246 /// field. TiedTo can have these values:
1248 /// 0: Operand is not tied to anything.
1249 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1250 /// TiedMax: Tied to an operand >= TiedMax-1.
1252 /// The tied def must be one of the first TiedMax operands on a normal
1253 /// instruction. INLINEASM instructions allow more tied defs.
1255 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1256 MachineOperand &DefMO = getOperand(DefIdx);
1257 MachineOperand &UseMO = getOperand(UseIdx);
1258 assert(DefMO.isDef() && "DefIdx must be a def operand");
1259 assert(UseMO.isUse() && "UseIdx must be a use operand");
1260 assert(!DefMO.isTied() && "Def is already tied to another use");
1261 assert(!UseMO.isTied() && "Use is already tied to another def");
1263 if (DefIdx < TiedMax)
1264 UseMO.TiedTo = DefIdx + 1;
1266 // Inline asm can use the group descriptors to find tied operands, but on
1267 // normal instruction, the tied def must be within the first TiedMax
1269 assert(isInlineAsm() && "DefIdx out of range");
1270 UseMO.TiedTo = TiedMax;
1273 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1274 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1277 /// Given the index of a tied register operand, find the operand it is tied to.
1278 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1279 /// which must exist.
1280 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1281 const MachineOperand &MO = getOperand(OpIdx);
1282 assert(MO.isTied() && "Operand isn't tied");
1284 // Normally TiedTo is in range.
1285 if (MO.TiedTo < TiedMax)
1286 return MO.TiedTo - 1;
1288 // Uses on normal instructions can be out of range.
1289 if (!isInlineAsm()) {
1290 // Normal tied defs must be in the 0..TiedMax-1 range.
1293 // MO is a def. Search for the tied use.
1294 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1295 const MachineOperand &UseMO = getOperand(i);
1296 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1299 llvm_unreachable("Can't find tied use");
1302 // Now deal with inline asm by parsing the operand group descriptor flags.
1303 // Find the beginning of each operand group.
1304 SmallVector<unsigned, 8> GroupIdx;
1305 unsigned OpIdxGroup = ~0u;
1307 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1309 const MachineOperand &FlagMO = getOperand(i);
1310 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1311 unsigned CurGroup = GroupIdx.size();
1312 GroupIdx.push_back(i);
1313 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1314 // OpIdx belongs to this operand group.
1315 if (OpIdx > i && OpIdx < i + NumOps)
1316 OpIdxGroup = CurGroup;
1318 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1320 // Operands in this group are tied to operands in TiedGroup which must be
1321 // earlier. Find the number of operands between the two groups.
1322 unsigned Delta = i - GroupIdx[TiedGroup];
1324 // OpIdx is a use tied to TiedGroup.
1325 if (OpIdxGroup == CurGroup)
1326 return OpIdx - Delta;
1328 // OpIdx is a def tied to this use group.
1329 if (OpIdxGroup == TiedGroup)
1330 return OpIdx + Delta;
1332 llvm_unreachable("Invalid tied operand on inline asm");
1335 /// clearKillInfo - Clears kill flags on all operands.
1337 void MachineInstr::clearKillInfo() {
1338 for (MachineOperand &MO : operands()) {
1339 if (MO.isReg() && MO.isUse())
1340 MO.setIsKill(false);
1344 void MachineInstr::substituteRegister(unsigned FromReg,
1347 const TargetRegisterInfo &RegInfo) {
1348 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1350 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1351 for (MachineOperand &MO : operands()) {
1352 if (!MO.isReg() || MO.getReg() != FromReg)
1354 MO.substPhysReg(ToReg, RegInfo);
1357 for (MachineOperand &MO : operands()) {
1358 if (!MO.isReg() || MO.getReg() != FromReg)
1360 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1365 /// isSafeToMove - Return true if it is safe to move this instruction. If
1366 /// SawStore is set to true, it means that there is a store (or call) between
1367 /// the instruction's location and its intended destination.
1368 bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
1369 // Ignore stuff that we obviously can't move.
1371 // Treat volatile loads as stores. This is not strictly necessary for
1372 // volatiles, but it is required for atomic loads. It is not allowed to move
1373 // a load across an atomic load with Ordering > Monotonic.
1374 if (mayStore() || isCall() ||
1375 (mayLoad() && hasOrderedMemoryRef())) {
1380 if (isPosition() || isDebugValue() || isTerminator() ||
1381 hasUnmodeledSideEffects())
1384 // See if this instruction does a load. If so, we have to guarantee that the
1385 // loaded value doesn't change between the load and the its intended
1386 // destination. The check for isInvariantLoad gives the targe the chance to
1387 // classify the load as always returning a constant, e.g. a constant pool
1389 if (mayLoad() && !isInvariantLoad(AA))
1390 // Otherwise, this is a real load. If there is a store between the load and
1391 // end of block, we can't move it.
1397 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1398 /// or volatile memory reference, or if the information describing the memory
1399 /// reference is not available. Return false if it is known to have no ordered
1400 /// memory references.
1401 bool MachineInstr::hasOrderedMemoryRef() const {
1402 // An instruction known never to access memory won't have a volatile access.
1406 !hasUnmodeledSideEffects())
1409 // Otherwise, if the instruction has no memory reference information,
1410 // conservatively assume it wasn't preserved.
1411 if (memoperands_empty())
1414 // Check the memory reference information for ordered references.
1415 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1416 if (!(*I)->isUnordered())
1422 /// isInvariantLoad - Return true if this instruction is loading from a
1423 /// location whose value is invariant across the function. For example,
1424 /// loading a value from the constant pool or from the argument area
1425 /// of a function if it does not change. This should only return true of
1426 /// *all* loads the instruction does are invariant (if it does multiple loads).
1427 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1428 // If the instruction doesn't load at all, it isn't an invariant load.
1432 // If the instruction has lost its memoperands, conservatively assume that
1433 // it may not be an invariant load.
1434 if (memoperands_empty())
1437 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1439 for (mmo_iterator I = memoperands_begin(),
1440 E = memoperands_end(); I != E; ++I) {
1441 if ((*I)->isVolatile()) return false;
1442 if ((*I)->isStore()) return false;
1443 if ((*I)->isInvariant()) return true;
1446 // A load from a constant PseudoSourceValue is invariant.
1447 if (const PseudoSourceValue *PSV = (*I)->getPseudoValue())
1448 if (PSV->isConstant(MFI))
1451 if (const Value *V = (*I)->getValue()) {
1452 // If we have an AliasAnalysis, ask it whether the memory is constant.
1453 if (AA && AA->pointsToConstantMemory(
1454 AliasAnalysis::Location(V, (*I)->getSize(),
1455 (*I)->getAAInfo())))
1459 // Otherwise assume conservatively.
1463 // Everything checks out.
1467 /// isConstantValuePHI - If the specified instruction is a PHI that always
1468 /// merges together the same virtual register, return the register, otherwise
1470 unsigned MachineInstr::isConstantValuePHI() const {
1473 assert(getNumOperands() >= 3 &&
1474 "It's illegal to have a PHI without source operands");
1476 unsigned Reg = getOperand(1).getReg();
1477 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1478 if (getOperand(i).getReg() != Reg)
1483 bool MachineInstr::hasUnmodeledSideEffects() const {
1484 if (hasProperty(MCID::UnmodeledSideEffects))
1486 if (isInlineAsm()) {
1487 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1488 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1495 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1497 bool MachineInstr::allDefsAreDead() const {
1498 for (const MachineOperand &MO : operands()) {
1499 if (!MO.isReg() || MO.isUse())
1507 /// copyImplicitOps - Copy implicit register operands from specified
1508 /// instruction to this instruction.
1509 void MachineInstr::copyImplicitOps(MachineFunction &MF,
1510 const MachineInstr *MI) {
1511 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1513 const MachineOperand &MO = MI->getOperand(i);
1514 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1519 void MachineInstr::dump() const {
1520 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1521 dbgs() << " " << *this;
1525 void MachineInstr::print(raw_ostream &OS, bool SkipOpers) const {
1526 // We can be a bit tidier if we know the MachineFunction.
1527 const MachineFunction *MF = nullptr;
1528 const TargetRegisterInfo *TRI = nullptr;
1529 const MachineRegisterInfo *MRI = nullptr;
1530 const TargetInstrInfo *TII = nullptr;
1531 if (const MachineBasicBlock *MBB = getParent()) {
1532 MF = MBB->getParent();
1534 MRI = &MF->getRegInfo();
1535 TRI = MF->getSubtarget().getRegisterInfo();
1536 TII = MF->getSubtarget().getInstrInfo();
1540 // Save a list of virtual registers.
1541 SmallVector<unsigned, 8> VirtRegs;
1543 // Print explicitly defined operands on the left of an assignment syntax.
1544 unsigned StartOp = 0, e = getNumOperands();
1545 for (; StartOp < e && getOperand(StartOp).isReg() &&
1546 getOperand(StartOp).isDef() &&
1547 !getOperand(StartOp).isImplicit();
1549 if (StartOp != 0) OS << ", ";
1550 getOperand(StartOp).print(OS, TRI);
1551 unsigned Reg = getOperand(StartOp).getReg();
1552 if (TargetRegisterInfo::isVirtualRegister(Reg))
1553 VirtRegs.push_back(Reg);
1559 // Print the opcode name.
1561 OS << TII->getName(getOpcode());
1568 // Print the rest of the operands.
1569 bool OmittedAnyCallClobbers = false;
1570 bool FirstOp = true;
1571 unsigned AsmDescOp = ~0u;
1572 unsigned AsmOpCount = 0;
1574 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1575 // Print asm string.
1577 getOperand(InlineAsm::MIOp_AsmString).print(OS, TRI);
1579 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1580 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1581 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1582 OS << " [sideeffect]";
1583 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1585 if (ExtraInfo & InlineAsm::Extra_MayStore)
1586 OS << " [maystore]";
1587 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1588 OS << " [alignstack]";
1589 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1590 OS << " [attdialect]";
1591 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1592 OS << " [inteldialect]";
1594 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1599 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1600 const MachineOperand &MO = getOperand(i);
1602 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1603 VirtRegs.push_back(MO.getReg());
1605 // Omit call-clobbered registers which aren't used anywhere. This makes
1606 // call instructions much less noisy on targets where calls clobber lots
1607 // of registers. Don't rely on MO.isDead() because we may be called before
1608 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1609 if (MRI && isCall() &&
1610 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1611 unsigned Reg = MO.getReg();
1612 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1613 if (MRI->use_empty(Reg)) {
1614 bool HasAliasLive = false;
1615 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
1616 unsigned AliasReg = *AI;
1617 if (!MRI->use_empty(AliasReg)) {
1618 HasAliasLive = true;
1622 if (!HasAliasLive) {
1623 OmittedAnyCallClobbers = true;
1630 if (FirstOp) FirstOp = false; else OS << ",";
1632 if (i < getDesc().NumOperands) {
1633 const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1634 if (MCOI.isPredicate())
1636 if (MCOI.isOptionalDef())
1639 if (isDebugValue() && MO.isMetadata()) {
1640 // Pretty print DBG_VALUE instructions.
1641 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1642 if (DIV && !DIV->getName().empty())
1643 OS << "!\"" << DIV->getName() << '\"';
1646 } else if (TRI && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1647 OS << TRI->getSubRegIndexName(MO.getImm());
1648 } else if (i == AsmDescOp && MO.isImm()) {
1649 // Pretty print the inline asm operand descriptor.
1650 OS << '$' << AsmOpCount++;
1651 unsigned Flag = MO.getImm();
1652 switch (InlineAsm::getKind(Flag)) {
1653 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1654 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1655 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1656 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1657 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1658 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1659 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1663 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1665 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1667 OS << ":RC" << RCID;
1670 unsigned TiedTo = 0;
1671 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1672 OS << " tiedto:$" << TiedTo;
1676 // Compute the index of the next operand descriptor.
1677 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1682 // Briefly indicate whether any call clobbers were omitted.
1683 if (OmittedAnyCallClobbers) {
1684 if (!FirstOp) OS << ",";
1688 bool HaveSemi = false;
1689 const unsigned PrintableFlags = FrameSetup;
1690 if (Flags & PrintableFlags) {
1691 if (!HaveSemi) OS << ";"; HaveSemi = true;
1694 if (Flags & FrameSetup)
1698 if (!memoperands_empty()) {
1699 if (!HaveSemi) OS << ";"; HaveSemi = true;
1702 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1705 if (std::next(i) != e)
1710 // Print the regclass of any virtual registers encountered.
1711 if (MRI && !VirtRegs.empty()) {
1712 if (!HaveSemi) OS << ";"; HaveSemi = true;
1713 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1714 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1715 OS << " " << TRI->getRegClassName(RC)
1716 << ':' << PrintReg(VirtRegs[i]);
1717 for (unsigned j = i+1; j != VirtRegs.size();) {
1718 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1722 if (VirtRegs[i] != VirtRegs[j])
1723 OS << "," << PrintReg(VirtRegs[j]);
1724 VirtRegs.erase(VirtRegs.begin()+j);
1729 // Print debug location information.
1730 if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1731 if (!HaveSemi) OS << ";";
1732 auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1733 OS << " line no:" << DV->getLine();
1734 if (auto *InlinedAt = debugLoc->getInlinedAt()) {
1735 DebugLoc InlinedAtDL(InlinedAt);
1736 if (InlinedAtDL && MF) {
1737 OS << " inlined @[ ";
1738 InlinedAtDL.print(OS);
1742 if (isIndirectDebugValue())
1744 } else if (debugLoc && MF) {
1745 if (!HaveSemi) OS << ";";
1753 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1754 const TargetRegisterInfo *RegInfo,
1755 bool AddIfNotFound) {
1756 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1757 bool hasAliases = isPhysReg &&
1758 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1760 SmallVector<unsigned,4> DeadOps;
1761 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1762 MachineOperand &MO = getOperand(i);
1763 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1765 unsigned Reg = MO.getReg();
1769 if (Reg == IncomingReg) {
1772 // The register is already marked kill.
1774 if (isPhysReg && isRegTiedToDefOperand(i))
1775 // Two-address uses of physregs must not be marked kill.
1780 } else if (hasAliases && MO.isKill() &&
1781 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1782 // A super-register kill already exists.
1783 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1785 if (RegInfo->isSubRegister(IncomingReg, Reg))
1786 DeadOps.push_back(i);
1790 // Trim unneeded kill operands.
1791 while (!DeadOps.empty()) {
1792 unsigned OpIdx = DeadOps.back();
1793 if (getOperand(OpIdx).isImplicit())
1794 RemoveOperand(OpIdx);
1796 getOperand(OpIdx).setIsKill(false);
1800 // If not found, this means an alias of one of the operands is killed. Add a
1801 // new implicit operand if required.
1802 if (!Found && AddIfNotFound) {
1803 addOperand(MachineOperand::CreateReg(IncomingReg,
1812 void MachineInstr::clearRegisterKills(unsigned Reg,
1813 const TargetRegisterInfo *RegInfo) {
1814 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1816 for (MachineOperand &MO : operands()) {
1817 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1819 unsigned OpReg = MO.getReg();
1820 if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1821 MO.setIsKill(false);
1825 bool MachineInstr::addRegisterDead(unsigned Reg,
1826 const TargetRegisterInfo *RegInfo,
1827 bool AddIfNotFound) {
1828 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
1829 bool hasAliases = isPhysReg &&
1830 MCRegAliasIterator(Reg, RegInfo, false).isValid();
1832 SmallVector<unsigned,4> DeadOps;
1833 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1834 MachineOperand &MO = getOperand(i);
1835 if (!MO.isReg() || !MO.isDef())
1837 unsigned MOReg = MO.getReg();
1844 } else if (hasAliases && MO.isDead() &&
1845 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1846 // There exists a super-register that's marked dead.
1847 if (RegInfo->isSuperRegister(Reg, MOReg))
1849 if (RegInfo->isSubRegister(Reg, MOReg))
1850 DeadOps.push_back(i);
1854 // Trim unneeded dead operands.
1855 while (!DeadOps.empty()) {
1856 unsigned OpIdx = DeadOps.back();
1857 if (getOperand(OpIdx).isImplicit())
1858 RemoveOperand(OpIdx);
1860 getOperand(OpIdx).setIsDead(false);
1864 // If not found, this means an alias of one of the operands is dead. Add a
1865 // new implicit operand if required.
1866 if (Found || !AddIfNotFound)
1869 addOperand(MachineOperand::CreateReg(Reg,
1877 void MachineInstr::clearRegisterDeads(unsigned Reg) {
1878 for (MachineOperand &MO : operands()) {
1879 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1881 MO.setIsDead(false);
1885 void MachineInstr::addRegisterDefReadUndef(unsigned Reg) {
1886 for (MachineOperand &MO : operands()) {
1887 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1893 void MachineInstr::addRegisterDefined(unsigned Reg,
1894 const TargetRegisterInfo *RegInfo) {
1895 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1896 MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
1900 for (const MachineOperand &MO : operands()) {
1901 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1902 MO.getSubReg() == 0)
1906 addOperand(MachineOperand::CreateReg(Reg,
1911 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1912 const TargetRegisterInfo &TRI) {
1913 bool HasRegMask = false;
1914 for (MachineOperand &MO : operands()) {
1915 if (MO.isRegMask()) {
1919 if (!MO.isReg() || !MO.isDef()) continue;
1920 unsigned Reg = MO.getReg();
1921 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1922 // If there are no uses, including partial uses, the def is dead.
1923 if (std::none_of(UsedRegs.begin(), UsedRegs.end(),
1924 [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
1928 // This is a call with a register mask operand.
1929 // Mask clobbers are always dead, so add defs for the non-dead defines.
1931 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1933 addRegisterDefined(*I, &TRI);
1937 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1938 // Build up a buffer of hash code components.
1939 SmallVector<size_t, 8> HashComponents;
1940 HashComponents.reserve(MI->getNumOperands() + 1);
1941 HashComponents.push_back(MI->getOpcode());
1942 for (const MachineOperand &MO : MI->operands()) {
1943 if (MO.isReg() && MO.isDef() &&
1944 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1945 continue; // Skip virtual register defs.
1947 HashComponents.push_back(hash_value(MO));
1949 return hash_combine_range(HashComponents.begin(), HashComponents.end());
1952 void MachineInstr::emitError(StringRef Msg) const {
1953 // Find the source location cookie.
1954 unsigned LocCookie = 0;
1955 const MDNode *LocMD = nullptr;
1956 for (unsigned i = getNumOperands(); i != 0; --i) {
1957 if (getOperand(i-1).isMetadata() &&
1958 (LocMD = getOperand(i-1).getMetadata()) &&
1959 LocMD->getNumOperands() != 0) {
1960 if (const ConstantInt *CI =
1961 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
1962 LocCookie = CI->getZExtValue();
1968 if (const MachineBasicBlock *MBB = getParent())
1969 if (const MachineFunction *MF = MBB->getParent())
1970 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1971 report_fatal_error(Msg);