1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/Function.h"
17 #include "llvm/InlineAsm.h"
18 #include "llvm/LLVMContext.h"
19 #include "llvm/Metadata.h"
20 #include "llvm/Module.h"
21 #include "llvm/Type.h"
22 #include "llvm/Value.h"
23 #include "llvm/Assembly/Writer.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineMemOperand.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCSymbol.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Analysis/AliasAnalysis.h"
36 #include "llvm/Analysis/DebugInfo.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/LeakDetector.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/ADT/FoldingSet.h"
45 //===----------------------------------------------------------------------===//
46 // MachineOperand Implementation
47 //===----------------------------------------------------------------------===//
49 /// AddRegOperandToRegInfo - Add this register operand to the specified
50 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
51 /// explicitly nulled out.
52 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
53 assert(isReg() && "Can only add reg operand to use lists");
55 // If the reginfo pointer is null, just explicitly null out or next/prev
56 // pointers, to ensure they are not garbage.
58 Contents.Reg.Prev = 0;
59 Contents.Reg.Next = 0;
63 // Otherwise, add this operand to the head of the registers use/def list.
64 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
66 // For SSA values, we prefer to keep the definition at the start of the list.
67 // we do this by skipping over the definition if it is at the head of the
69 if (*Head && (*Head)->isDef())
70 Head = &(*Head)->Contents.Reg.Next;
72 Contents.Reg.Next = *Head;
73 if (Contents.Reg.Next) {
74 assert(getReg() == Contents.Reg.Next->getReg() &&
75 "Different regs on the same list!");
76 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
79 Contents.Reg.Prev = Head;
83 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
84 /// MachineRegisterInfo it is linked with.
85 void MachineOperand::RemoveRegOperandFromRegInfo() {
86 assert(isOnRegUseList() && "Reg operand is not on a use list");
87 // Unlink this from the doubly linked list of operands.
88 MachineOperand *NextOp = Contents.Reg.Next;
89 *Contents.Reg.Prev = NextOp;
91 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
92 NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
94 Contents.Reg.Prev = 0;
95 Contents.Reg.Next = 0;
98 void MachineOperand::setReg(unsigned Reg) {
99 if (getReg() == Reg) return; // No change.
101 // Otherwise, we have to change the register. If this operand is embedded
102 // into a machine function, we need to update the old and new register's
104 if (MachineInstr *MI = getParent())
105 if (MachineBasicBlock *MBB = MI->getParent())
106 if (MachineFunction *MF = MBB->getParent()) {
107 RemoveRegOperandFromRegInfo();
108 SmallContents.RegNo = Reg;
109 AddRegOperandToRegInfo(&MF->getRegInfo());
113 // Otherwise, just change the register, no problem. :)
114 SmallContents.RegNo = Reg;
117 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
118 const TargetRegisterInfo &TRI) {
119 assert(TargetRegisterInfo::isVirtualRegister(Reg));
120 if (SubIdx && getSubReg())
121 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
127 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
128 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
130 Reg = TRI.getSubReg(Reg, getSubReg());
131 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
132 // That won't happen in legal code.
138 /// ChangeToImmediate - Replace this operand with a new immediate operand of
139 /// the specified value. If an operand is known to be an immediate already,
140 /// the setImm method should be used.
141 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
142 // If this operand is currently a register operand, and if this is in a
143 // function, deregister the operand from the register's use/def list.
144 if (isReg() && getParent() && getParent()->getParent() &&
145 getParent()->getParent()->getParent())
146 RemoveRegOperandFromRegInfo();
148 OpKind = MO_Immediate;
149 Contents.ImmVal = ImmVal;
152 /// ChangeToRegister - Replace this operand with a new register operand of
153 /// the specified value. If an operand is known to be an register already,
154 /// the setReg method should be used.
155 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
156 bool isKill, bool isDead, bool isUndef,
158 // If this operand is already a register operand, use setReg to update the
159 // register's use/def lists.
161 assert(!isEarlyClobber());
164 // Otherwise, change this to a register and set the reg#.
165 OpKind = MO_Register;
166 SmallContents.RegNo = Reg;
168 // If this operand is embedded in a function, add the operand to the
169 // register's use/def list.
170 if (MachineInstr *MI = getParent())
171 if (MachineBasicBlock *MBB = MI->getParent())
172 if (MachineFunction *MF = MBB->getParent())
173 AddRegOperandToRegInfo(&MF->getRegInfo());
181 IsInternalRead = false;
182 IsEarlyClobber = false;
187 /// isIdenticalTo - Return true if this operand is identical to the specified
189 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
190 if (getType() != Other.getType() ||
191 getTargetFlags() != Other.getTargetFlags())
195 default: llvm_unreachable("Unrecognized operand type");
196 case MachineOperand::MO_Register:
197 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
198 getSubReg() == Other.getSubReg();
199 case MachineOperand::MO_Immediate:
200 return getImm() == Other.getImm();
201 case MachineOperand::MO_CImmediate:
202 return getCImm() == Other.getCImm();
203 case MachineOperand::MO_FPImmediate:
204 return getFPImm() == Other.getFPImm();
205 case MachineOperand::MO_MachineBasicBlock:
206 return getMBB() == Other.getMBB();
207 case MachineOperand::MO_FrameIndex:
208 return getIndex() == Other.getIndex();
209 case MachineOperand::MO_ConstantPoolIndex:
210 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
211 case MachineOperand::MO_JumpTableIndex:
212 return getIndex() == Other.getIndex();
213 case MachineOperand::MO_GlobalAddress:
214 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
215 case MachineOperand::MO_ExternalSymbol:
216 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
217 getOffset() == Other.getOffset();
218 case MachineOperand::MO_BlockAddress:
219 return getBlockAddress() == Other.getBlockAddress();
220 case MachineOperand::MO_MCSymbol:
221 return getMCSymbol() == Other.getMCSymbol();
222 case MachineOperand::MO_Metadata:
223 return getMetadata() == Other.getMetadata();
227 /// print - Print the specified machine operand.
229 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
230 // If the instruction is embedded into a basic block, we can find the
231 // target info for the instruction.
233 if (const MachineInstr *MI = getParent())
234 if (const MachineBasicBlock *MBB = MI->getParent())
235 if (const MachineFunction *MF = MBB->getParent())
236 TM = &MF->getTarget();
237 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
240 case MachineOperand::MO_Register:
241 OS << PrintReg(getReg(), TRI, getSubReg());
243 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
244 isInternalRead() || isEarlyClobber()) {
246 bool NeedComma = false;
248 if (NeedComma) OS << ',';
249 if (isEarlyClobber())
250 OS << "earlyclobber,";
255 } else if (isImplicit()) {
260 if (isKill() || isDead() || isUndef() || isInternalRead()) {
261 if (NeedComma) OS << ',';
272 if (NeedComma) OS << ',';
276 if (isInternalRead()) {
277 if (NeedComma) OS << ',';
285 case MachineOperand::MO_Immediate:
288 case MachineOperand::MO_CImmediate:
289 getCImm()->getValue().print(OS, false);
291 case MachineOperand::MO_FPImmediate:
292 if (getFPImm()->getType()->isFloatTy())
293 OS << getFPImm()->getValueAPF().convertToFloat();
295 OS << getFPImm()->getValueAPF().convertToDouble();
297 case MachineOperand::MO_MachineBasicBlock:
298 OS << "<BB#" << getMBB()->getNumber() << ">";
300 case MachineOperand::MO_FrameIndex:
301 OS << "<fi#" << getIndex() << '>';
303 case MachineOperand::MO_ConstantPoolIndex:
304 OS << "<cp#" << getIndex();
305 if (getOffset()) OS << "+" << getOffset();
308 case MachineOperand::MO_JumpTableIndex:
309 OS << "<jt#" << getIndex() << '>';
311 case MachineOperand::MO_GlobalAddress:
313 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
314 if (getOffset()) OS << "+" << getOffset();
317 case MachineOperand::MO_ExternalSymbol:
318 OS << "<es:" << getSymbolName();
319 if (getOffset()) OS << "+" << getOffset();
322 case MachineOperand::MO_BlockAddress:
324 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
327 case MachineOperand::MO_Metadata:
329 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
332 case MachineOperand::MO_MCSymbol:
333 OS << "<MCSym=" << *getMCSymbol() << '>';
336 llvm_unreachable("Unrecognized operand type");
339 if (unsigned TF = getTargetFlags())
340 OS << "[TF=" << TF << ']';
343 //===----------------------------------------------------------------------===//
344 // MachineMemOperand Implementation
345 //===----------------------------------------------------------------------===//
347 /// getAddrSpace - Return the LLVM IR address space number that this pointer
349 unsigned MachinePointerInfo::getAddrSpace() const {
350 if (V == 0) return 0;
351 return cast<PointerType>(V->getType())->getAddressSpace();
354 /// getConstantPool - Return a MachinePointerInfo record that refers to the
356 MachinePointerInfo MachinePointerInfo::getConstantPool() {
357 return MachinePointerInfo(PseudoSourceValue::getConstantPool());
360 /// getFixedStack - Return a MachinePointerInfo record that refers to the
361 /// the specified FrameIndex.
362 MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
363 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
366 MachinePointerInfo MachinePointerInfo::getJumpTable() {
367 return MachinePointerInfo(PseudoSourceValue::getJumpTable());
370 MachinePointerInfo MachinePointerInfo::getGOT() {
371 return MachinePointerInfo(PseudoSourceValue::getGOT());
374 MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
375 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
378 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
379 uint64_t s, unsigned int a,
380 const MDNode *TBAAInfo)
381 : PtrInfo(ptrinfo), Size(s),
382 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
384 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
385 "invalid pointer value");
386 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
387 assert((isLoad() || isStore()) && "Not a load/store!");
390 /// Profile - Gather unique data for the object.
392 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
393 ID.AddInteger(getOffset());
395 ID.AddPointer(getValue());
396 ID.AddInteger(Flags);
399 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
400 // The Value and Offset may differ due to CSE. But the flags and size
401 // should be the same.
402 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
403 assert(MMO->getSize() == getSize() && "Size mismatch!");
405 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
406 // Update the alignment value.
407 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
408 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
409 // Also update the base and offset, because the new alignment may
410 // not be applicable with the old ones.
411 PtrInfo = MMO->PtrInfo;
415 /// getAlignment - Return the minimum known alignment in bytes of the
416 /// actual memory reference.
417 uint64_t MachineMemOperand::getAlignment() const {
418 return MinAlign(getBaseAlignment(), getOffset());
421 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
422 assert((MMO.isLoad() || MMO.isStore()) &&
423 "SV has to be a load, store or both.");
425 if (MMO.isVolatile())
434 // Print the address information.
439 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
441 // If the alignment of the memory reference itself differs from the alignment
442 // of the base pointer, print the base alignment explicitly, next to the base
444 if (MMO.getBaseAlignment() != MMO.getAlignment())
445 OS << "(align=" << MMO.getBaseAlignment() << ")";
447 if (MMO.getOffset() != 0)
448 OS << "+" << MMO.getOffset();
451 // Print the alignment of the reference.
452 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
453 MMO.getBaseAlignment() != MMO.getSize())
454 OS << "(align=" << MMO.getAlignment() << ")";
457 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
459 if (TBAAInfo->getNumOperands() > 0)
460 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
466 // Print nontemporal info.
467 if (MMO.isNonTemporal())
468 OS << "(nontemporal)";
473 //===----------------------------------------------------------------------===//
474 // MachineInstr Implementation
475 //===----------------------------------------------------------------------===//
477 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
478 /// MCID NULL and no operands.
479 MachineInstr::MachineInstr()
480 : MCID(0), Flags(0), AsmPrinterFlags(0),
481 MemRefs(0), MemRefsEnd(0),
483 // Make sure that we get added to a machine basicblock
484 LeakDetector::addGarbageObject(this);
487 void MachineInstr::addImplicitDefUseOperands() {
488 if (MCID->ImplicitDefs)
489 for (const unsigned *ImpDefs = MCID->ImplicitDefs; *ImpDefs; ++ImpDefs)
490 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
491 if (MCID->ImplicitUses)
492 for (const unsigned *ImpUses = MCID->ImplicitUses; *ImpUses; ++ImpUses)
493 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
496 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
497 /// implicit operands. It reserves space for the number of operands specified by
499 MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp)
500 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
501 MemRefs(0), MemRefsEnd(0), Parent(0) {
502 unsigned NumImplicitOps = 0;
504 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
505 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
507 addImplicitDefUseOperands();
508 // Make sure that we get added to a machine basicblock
509 LeakDetector::addGarbageObject(this);
512 /// MachineInstr ctor - As above, but with a DebugLoc.
513 MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
515 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
516 MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
517 unsigned NumImplicitOps = 0;
519 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
520 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
522 addImplicitDefUseOperands();
523 // Make sure that we get added to a machine basicblock
524 LeakDetector::addGarbageObject(this);
527 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
528 /// that the MachineInstr is created and added to the end of the specified
530 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid)
531 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
532 MemRefs(0), MemRefsEnd(0), Parent(0) {
533 assert(MBB && "Cannot use inserting ctor with null basic block!");
534 unsigned NumImplicitOps =
535 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
536 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
537 addImplicitDefUseOperands();
538 // Make sure that we get added to a machine basicblock
539 LeakDetector::addGarbageObject(this);
540 MBB->push_back(this); // Add instruction to end of basic block!
543 /// MachineInstr ctor - As above, but with a DebugLoc.
545 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
546 const MCInstrDesc &tid)
547 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
548 MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
549 assert(MBB && "Cannot use inserting ctor with null basic block!");
550 unsigned NumImplicitOps =
551 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
552 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
553 addImplicitDefUseOperands();
554 // Make sure that we get added to a machine basicblock
555 LeakDetector::addGarbageObject(this);
556 MBB->push_back(this); // Add instruction to end of basic block!
559 /// MachineInstr ctor - Copies MachineInstr arg exactly
561 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
562 : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0),
563 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
564 Parent(0), debugLoc(MI.getDebugLoc()) {
565 Operands.reserve(MI.getNumOperands());
568 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
569 addOperand(MI.getOperand(i));
571 // Copy all the flags.
574 // Set parent to null.
577 LeakDetector::addGarbageObject(this);
580 MachineInstr::~MachineInstr() {
581 LeakDetector::removeGarbageObject(this);
583 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
584 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
585 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
586 "Reg operand def/use list corrupted");
591 /// getRegInfo - If this instruction is embedded into a MachineFunction,
592 /// return the MachineRegisterInfo object for the current function, otherwise
594 MachineRegisterInfo *MachineInstr::getRegInfo() {
595 if (MachineBasicBlock *MBB = getParent())
596 return &MBB->getParent()->getRegInfo();
600 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
601 /// this instruction from their respective use lists. This requires that the
602 /// operands already be on their use lists.
603 void MachineInstr::RemoveRegOperandsFromUseLists() {
604 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
605 if (Operands[i].isReg())
606 Operands[i].RemoveRegOperandFromRegInfo();
610 /// AddRegOperandsToUseLists - Add all of the register operands in
611 /// this instruction from their respective use lists. This requires that the
612 /// operands not be on their use lists yet.
613 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
614 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
615 if (Operands[i].isReg())
616 Operands[i].AddRegOperandToRegInfo(&RegInfo);
621 /// addOperand - Add the specified operand to the instruction. If it is an
622 /// implicit operand, it is added to the end of the operand list. If it is
623 /// an explicit operand it is added at the end of the explicit operand list
624 /// (before the first implicit operand).
625 void MachineInstr::addOperand(const MachineOperand &Op) {
626 assert(MCID && "Cannot add operands before providing an instr descriptor");
627 bool isImpReg = Op.isReg() && Op.isImplicit();
628 MachineRegisterInfo *RegInfo = getRegInfo();
630 // If the Operands backing store is reallocated, all register operands must
631 // be removed and re-added to RegInfo. It is storing pointers to operands.
632 bool Reallocate = RegInfo &&
633 !Operands.empty() && Operands.size() == Operands.capacity();
635 // Find the insert location for the new operand. Implicit registers go at
636 // the end, everything goes before the implicit regs.
637 unsigned OpNo = Operands.size();
639 // Remove all the implicit operands from RegInfo if they need to be shifted.
640 // FIXME: Allow mixed explicit and implicit operands on inline asm.
641 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
642 // implicit-defs, but they must not be moved around. See the FIXME in
644 if (!isImpReg && !isInlineAsm()) {
645 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
648 Operands[OpNo].RemoveRegOperandFromRegInfo();
652 // OpNo now points as the desired insertion point. Unless this is a variadic
653 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
654 assert((isImpReg || MCID->isVariadic() || OpNo < MCID->getNumOperands()) &&
655 "Trying to add an operand to a machine instr that is already done!");
657 // All operands from OpNo have been removed from RegInfo. If the Operands
658 // backing store needs to be reallocated, we also need to remove any other
659 // register operands.
661 for (unsigned i = 0; i != OpNo; ++i)
662 if (Operands[i].isReg())
663 Operands[i].RemoveRegOperandFromRegInfo();
665 // Insert the new operand at OpNo.
666 Operands.insert(Operands.begin() + OpNo, Op);
667 Operands[OpNo].ParentMI = this;
669 // The Operands backing store has now been reallocated, so we can re-add the
670 // operands before OpNo.
672 for (unsigned i = 0; i != OpNo; ++i)
673 if (Operands[i].isReg())
674 Operands[i].AddRegOperandToRegInfo(RegInfo);
676 // When adding a register operand, tell RegInfo about it.
677 if (Operands[OpNo].isReg()) {
678 // Add the new operand to RegInfo, even when RegInfo is NULL.
679 // This will initialize the linked list pointers.
680 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
681 // If the register operand is flagged as early, mark the operand as such.
682 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
683 Operands[OpNo].setIsEarlyClobber(true);
686 // Re-add all the implicit ops.
688 for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) {
689 assert(Operands[i].isReg() && "Should only be an implicit reg!");
690 Operands[i].AddRegOperandToRegInfo(RegInfo);
695 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
696 /// fewer operand than it started with.
698 void MachineInstr::RemoveOperand(unsigned OpNo) {
699 assert(OpNo < Operands.size() && "Invalid operand number");
701 // Special case removing the last one.
702 if (OpNo == Operands.size()-1) {
703 // If needed, remove from the reg def/use list.
704 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
705 Operands.back().RemoveRegOperandFromRegInfo();
711 // Otherwise, we are removing an interior operand. If we have reginfo to
712 // update, remove all operands that will be shifted down from their reg lists,
713 // move everything down, then re-add them.
714 MachineRegisterInfo *RegInfo = getRegInfo();
716 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
717 if (Operands[i].isReg())
718 Operands[i].RemoveRegOperandFromRegInfo();
722 Operands.erase(Operands.begin()+OpNo);
725 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
726 if (Operands[i].isReg())
727 Operands[i].AddRegOperandToRegInfo(RegInfo);
732 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
733 /// This function should be used only occasionally. The setMemRefs function
734 /// is the primary method for setting up a MachineInstr's MemRefs list.
735 void MachineInstr::addMemOperand(MachineFunction &MF,
736 MachineMemOperand *MO) {
737 mmo_iterator OldMemRefs = MemRefs;
738 mmo_iterator OldMemRefsEnd = MemRefsEnd;
740 size_t NewNum = (MemRefsEnd - MemRefs) + 1;
741 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
742 mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
744 std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
745 NewMemRefs[NewNum - 1] = MO;
747 MemRefs = NewMemRefs;
748 MemRefsEnd = NewMemRefsEnd;
752 MachineInstr::hasProperty(unsigned MCFlag, QueryType Type) const {
753 if (Type == IgnoreBundle || !isBundle())
754 return getDesc().getFlags() & (1 << MCFlag);
756 const MachineBasicBlock *MBB = getParent();
757 MachineBasicBlock::const_instr_iterator MII = *this; ++MII;
758 while (MII != MBB->end() && MII->isInsideBundle()) {
759 if (MII->getDesc().getFlags() & (1 << MCFlag)) {
760 if (Type == AnyInBundle)
763 if (Type == AllInBundle)
769 return Type == AllInBundle;
772 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
773 MICheckType Check) const {
774 // If opcodes or number of operands are not the same then the two
775 // instructions are obviously not identical.
776 if (Other->getOpcode() != getOpcode() ||
777 Other->getNumOperands() != getNumOperands())
781 // Both instructions are bundles, compare MIs inside the bundle.
782 MachineBasicBlock::const_instr_iterator I1 = *this;
783 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
784 MachineBasicBlock::const_instr_iterator I2 = *Other;
785 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
786 while (++I1 != E1 && I1->isInsideBundle()) {
788 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
793 // Check operands to make sure they match.
794 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
795 const MachineOperand &MO = getOperand(i);
796 const MachineOperand &OMO = Other->getOperand(i);
798 if (!MO.isIdenticalTo(OMO))
803 // Clients may or may not want to ignore defs when testing for equality.
804 // For example, machine CSE pass only cares about finding common
805 // subexpressions, so it's safe to ignore virtual register defs.
807 if (Check == IgnoreDefs)
809 else if (Check == IgnoreVRegDefs) {
810 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
811 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
812 if (MO.getReg() != OMO.getReg())
815 if (!MO.isIdenticalTo(OMO))
817 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
821 if (!MO.isIdenticalTo(OMO))
823 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
827 // If DebugLoc does not match then two dbg.values are not identical.
829 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
830 && getDebugLoc() != Other->getDebugLoc())
835 /// removeFromParent - This method unlinks 'this' from the containing basic
836 /// block, and returns it, but does not delete it.
837 MachineInstr *MachineInstr::removeFromParent() {
838 assert(getParent() && "Not embedded in a basic block!");
840 // If it's a bundle then remove the MIs inside the bundle as well.
842 MachineBasicBlock *MBB = getParent();
843 MachineBasicBlock::instr_iterator MII = *this; ++MII;
844 MachineBasicBlock::instr_iterator E = MBB->instr_end();
845 while (MII != E && MII->isInsideBundle()) {
846 MachineInstr *MI = &*MII;
851 getParent()->remove(this);
856 /// eraseFromParent - This method unlinks 'this' from the containing basic
857 /// block, and deletes it.
858 void MachineInstr::eraseFromParent() {
859 assert(getParent() && "Not embedded in a basic block!");
860 // If it's a bundle then remove the MIs inside the bundle as well.
862 MachineBasicBlock *MBB = getParent();
863 MachineBasicBlock::instr_iterator MII = *this; ++MII;
864 MachineBasicBlock::instr_iterator E = MBB->instr_end();
865 while (MII != E && MII->isInsideBundle()) {
866 MachineInstr *MI = &*MII;
871 getParent()->erase(this);
875 /// getNumExplicitOperands - Returns the number of non-implicit operands.
877 unsigned MachineInstr::getNumExplicitOperands() const {
878 unsigned NumOperands = MCID->getNumOperands();
879 if (!MCID->isVariadic())
882 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
883 const MachineOperand &MO = getOperand(i);
884 if (!MO.isReg() || !MO.isImplicit())
890 bool MachineInstr::isStackAligningInlineAsm() const {
892 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
893 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
899 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
900 unsigned *GroupNo) const {
901 assert(isInlineAsm() && "Expected an inline asm instruction");
902 assert(OpIdx < getNumOperands() && "OpIdx out of range");
904 // Ignore queries about the initial operands.
905 if (OpIdx < InlineAsm::MIOp_FirstOperand)
910 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
912 const MachineOperand &FlagMO = getOperand(i);
913 // If we reach the implicit register operands, stop looking.
916 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
917 if (i + NumOps > OpIdx) {
927 const TargetRegisterClass*
928 MachineInstr::getRegClassConstraint(unsigned OpIdx,
929 const TargetInstrInfo *TII,
930 const TargetRegisterInfo *TRI) const {
931 // Most opcodes have fixed constraints in their MCInstrDesc.
933 return TII->getRegClass(getDesc(), OpIdx, TRI);
935 if (!getOperand(OpIdx).isReg())
938 // For tied uses on inline asm, get the constraint from the def.
940 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
943 // Inline asm stores register class constraints in the flag word.
944 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
948 unsigned Flag = getOperand(FlagIdx).getImm();
950 if (InlineAsm::hasRegClassConstraint(Flag, RCID))
951 return TRI->getRegClass(RCID);
953 // Assume that all registers in a memory operand are pointers.
954 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
955 return TRI->getPointerRegClass();
960 /// getBundleSize - Return the number of instructions inside the MI bundle.
961 unsigned MachineInstr::getBundleSize() const {
962 assert(isBundle() && "Expecting a bundle");
964 MachineBasicBlock::const_instr_iterator I = *this;
966 while ((++I)->isInsideBundle()) {
969 assert(Size > 1 && "Malformed bundle");
974 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
975 /// the specific register or -1 if it is not found. It further tightens
976 /// the search criteria to a use that kills the register if isKill is true.
977 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
978 const TargetRegisterInfo *TRI) const {
979 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
980 const MachineOperand &MO = getOperand(i);
981 if (!MO.isReg() || !MO.isUse())
983 unsigned MOReg = MO.getReg();
988 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
989 TargetRegisterInfo::isPhysicalRegister(Reg) &&
990 TRI->isSubRegister(MOReg, Reg)))
991 if (!isKill || MO.isKill())
997 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
998 /// indicating if this instruction reads or writes Reg. This also considers
1000 std::pair<bool,bool>
1001 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1002 SmallVectorImpl<unsigned> *Ops) const {
1003 bool PartDef = false; // Partial redefine.
1004 bool FullDef = false; // Full define.
1007 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1008 const MachineOperand &MO = getOperand(i);
1009 if (!MO.isReg() || MO.getReg() != Reg)
1014 Use |= !MO.isUndef();
1015 else if (MO.getSubReg() && !MO.isUndef())
1016 // A partial <def,undef> doesn't count as reading the register.
1021 // A partial redefine uses Reg unless there is also a full define.
1022 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1025 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1026 /// the specified register or -1 if it is not found. If isDead is true, defs
1027 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1028 /// also checks if there is a def of a super-register.
1030 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1031 const TargetRegisterInfo *TRI) const {
1032 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1033 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1034 const MachineOperand &MO = getOperand(i);
1035 if (!MO.isReg() || !MO.isDef())
1037 unsigned MOReg = MO.getReg();
1038 bool Found = (MOReg == Reg);
1039 if (!Found && TRI && isPhys &&
1040 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1042 Found = TRI->regsOverlap(MOReg, Reg);
1044 Found = TRI->isSubRegister(MOReg, Reg);
1046 if (Found && (!isDead || MO.isDead()))
1052 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1053 /// operand list that is used to represent the predicate. It returns -1 if
1055 int MachineInstr::findFirstPredOperandIdx() const {
1056 // Don't call MCID.findFirstPredOperandIdx() because this variant
1057 // is sometimes called on an instruction that's not yet complete, and
1058 // so the number of operands is less than the MCID indicates. In
1059 // particular, the PTX target does this.
1060 const MCInstrDesc &MCID = getDesc();
1061 if (MCID.isPredicable()) {
1062 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1063 if (MCID.OpInfo[i].isPredicate())
1070 /// isRegTiedToUseOperand - Given the index of a register def operand,
1071 /// check if the register def is tied to a source operand, due to either
1072 /// two-address elimination or inline assembly constraints. Returns the
1073 /// first tied use operand index by reference is UseOpIdx is not null.
1075 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
1076 if (isInlineAsm()) {
1077 assert(DefOpIdx > InlineAsm::MIOp_FirstOperand);
1078 const MachineOperand &MO = getOperand(DefOpIdx);
1079 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
1081 // Determine the actual operand index that corresponds to this index.
1083 int FlagIdx = findInlineAsmFlagIdx(DefOpIdx, &DefNo);
1087 // Which part of the group is DefOpIdx?
1088 unsigned DefPart = DefOpIdx - (FlagIdx + 1);
1090 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
1092 const MachineOperand &FMO = getOperand(i);
1095 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
1098 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
1101 *UseOpIdx = (unsigned)i + 1 + DefPart;
1108 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
1109 const MCInstrDesc &MCID = getDesc();
1110 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
1111 const MachineOperand &MO = getOperand(i);
1112 if (MO.isReg() && MO.isUse() &&
1113 MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) {
1115 *UseOpIdx = (unsigned)i;
1122 /// isRegTiedToDefOperand - Return true if the operand of the specified index
1123 /// is a register use and it is tied to an def operand. It also returns the def
1124 /// operand index by reference.
1126 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
1127 if (isInlineAsm()) {
1128 const MachineOperand &MO = getOperand(UseOpIdx);
1129 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
1132 // Find the flag operand corresponding to UseOpIdx
1133 int FlagIdx = findInlineAsmFlagIdx(UseOpIdx);
1137 const MachineOperand &UFMO = getOperand(FlagIdx);
1139 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
1143 unsigned DefIdx = InlineAsm::MIOp_FirstOperand;
1144 // Remember to adjust the index. First operand is asm string, second is
1145 // the HasSideEffects and AlignStack bits, then there is a flag for each.
1147 const MachineOperand &FMO = getOperand(DefIdx);
1148 assert(FMO.isImm());
1149 // Skip over this def.
1150 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
1153 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
1159 const MCInstrDesc &MCID = getDesc();
1160 if (UseOpIdx >= MCID.getNumOperands())
1162 const MachineOperand &MO = getOperand(UseOpIdx);
1163 if (!MO.isReg() || !MO.isUse())
1165 int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO);
1169 *DefOpIdx = (unsigned)DefIdx;
1173 /// clearKillInfo - Clears kill flags on all operands.
1175 void MachineInstr::clearKillInfo() {
1176 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1177 MachineOperand &MO = getOperand(i);
1178 if (MO.isReg() && MO.isUse())
1179 MO.setIsKill(false);
1183 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1185 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1186 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1187 const MachineOperand &MO = MI->getOperand(i);
1188 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1190 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1191 MachineOperand &MOp = getOperand(j);
1192 if (!MOp.isIdenticalTo(MO))
1203 /// copyPredicates - Copies predicate operand(s) from MI.
1204 void MachineInstr::copyPredicates(const MachineInstr *MI) {
1205 assert(!isBundle() && "MachineInstr::copyPredicates() can't handle bundles");
1207 const MCInstrDesc &MCID = MI->getDesc();
1208 if (!MCID.isPredicable())
1210 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1211 if (MCID.OpInfo[i].isPredicate()) {
1212 // Predicated operands must be last operands.
1213 addOperand(MI->getOperand(i));
1218 void MachineInstr::substituteRegister(unsigned FromReg,
1221 const TargetRegisterInfo &RegInfo) {
1222 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1224 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1225 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1226 MachineOperand &MO = getOperand(i);
1227 if (!MO.isReg() || MO.getReg() != FromReg)
1229 MO.substPhysReg(ToReg, RegInfo);
1232 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1233 MachineOperand &MO = getOperand(i);
1234 if (!MO.isReg() || MO.getReg() != FromReg)
1236 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1241 /// isSafeToMove - Return true if it is safe to move this instruction. If
1242 /// SawStore is set to true, it means that there is a store (or call) between
1243 /// the instruction's location and its intended destination.
1244 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1246 bool &SawStore) const {
1247 // Ignore stuff that we obviously can't move.
1248 if (mayStore() || isCall()) {
1253 if (isLabel() || isDebugValue() ||
1254 isTerminator() || hasUnmodeledSideEffects())
1257 // See if this instruction does a load. If so, we have to guarantee that the
1258 // loaded value doesn't change between the load and the its intended
1259 // destination. The check for isInvariantLoad gives the targe the chance to
1260 // classify the load as always returning a constant, e.g. a constant pool
1262 if (mayLoad() && !isInvariantLoad(AA))
1263 // Otherwise, this is a real load. If there is a store between the load and
1264 // end of block, or if the load is volatile, we can't move it.
1265 return !SawStore && !hasVolatileMemoryRef();
1270 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
1271 /// instruction which defined the specified register instead of copying it.
1272 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1274 unsigned DstReg) const {
1275 bool SawStore = false;
1276 if (!TII->isTriviallyReMaterializable(this, AA) ||
1277 !isSafeToMove(TII, AA, SawStore))
1279 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1280 const MachineOperand &MO = getOperand(i);
1283 // FIXME: For now, do not remat any instruction with register operands.
1284 // Later on, we can loosen the restriction is the register operands have
1285 // not been modified between the def and use. Note, this is different from
1286 // MachineSink because the code is no longer in two-address form (at least
1290 else if (!MO.isDead() && MO.getReg() != DstReg)
1296 /// hasVolatileMemoryRef - Return true if this instruction may have a
1297 /// volatile memory reference, or if the information describing the
1298 /// memory reference is not available. Return false if it is known to
1299 /// have no volatile memory references.
1300 bool MachineInstr::hasVolatileMemoryRef() const {
1301 // An instruction known never to access memory won't have a volatile access.
1305 !hasUnmodeledSideEffects())
1308 // Otherwise, if the instruction has no memory reference information,
1309 // conservatively assume it wasn't preserved.
1310 if (memoperands_empty())
1313 // Check the memory reference information for volatile references.
1314 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1315 if ((*I)->isVolatile())
1321 /// isInvariantLoad - Return true if this instruction is loading from a
1322 /// location whose value is invariant across the function. For example,
1323 /// loading a value from the constant pool or from the argument area
1324 /// of a function if it does not change. This should only return true of
1325 /// *all* loads the instruction does are invariant (if it does multiple loads).
1326 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1327 // If the instruction doesn't load at all, it isn't an invariant load.
1331 // If the instruction has lost its memoperands, conservatively assume that
1332 // it may not be an invariant load.
1333 if (memoperands_empty())
1336 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1338 for (mmo_iterator I = memoperands_begin(),
1339 E = memoperands_end(); I != E; ++I) {
1340 if ((*I)->isVolatile()) return false;
1341 if ((*I)->isStore()) return false;
1342 if ((*I)->isInvariant()) return true;
1344 if (const Value *V = (*I)->getValue()) {
1345 // A load from a constant PseudoSourceValue is invariant.
1346 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1347 if (PSV->isConstant(MFI))
1349 // If we have an AliasAnalysis, ask it whether the memory is constant.
1350 if (AA && AA->pointsToConstantMemory(
1351 AliasAnalysis::Location(V, (*I)->getSize(),
1352 (*I)->getTBAAInfo())))
1356 // Otherwise assume conservatively.
1360 // Everything checks out.
1364 /// isConstantValuePHI - If the specified instruction is a PHI that always
1365 /// merges together the same virtual register, return the register, otherwise
1367 unsigned MachineInstr::isConstantValuePHI() const {
1370 assert(getNumOperands() >= 3 &&
1371 "It's illegal to have a PHI without source operands");
1373 unsigned Reg = getOperand(1).getReg();
1374 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1375 if (getOperand(i).getReg() != Reg)
1380 bool MachineInstr::hasUnmodeledSideEffects() const {
1381 if (hasProperty(MCID::UnmodeledSideEffects))
1383 if (isInlineAsm()) {
1384 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1385 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1392 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1394 bool MachineInstr::allDefsAreDead() const {
1395 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1396 const MachineOperand &MO = getOperand(i);
1397 if (!MO.isReg() || MO.isUse())
1405 /// copyImplicitOps - Copy implicit register operands from specified
1406 /// instruction to this instruction.
1407 void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1408 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1410 const MachineOperand &MO = MI->getOperand(i);
1411 if (MO.isReg() && MO.isImplicit())
1416 void MachineInstr::dump() const {
1417 dbgs() << " " << *this;
1420 static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1421 raw_ostream &CommentOS) {
1422 const LLVMContext &Ctx = MF->getFunction()->getContext();
1423 if (!DL.isUnknown()) { // Print source line info.
1424 DIScope Scope(DL.getScope(Ctx));
1425 // Omit the directory, because it's likely to be long and uninteresting.
1427 CommentOS << Scope.getFilename();
1429 CommentOS << "<unknown>";
1430 CommentOS << ':' << DL.getLine();
1431 if (DL.getCol() != 0)
1432 CommentOS << ':' << DL.getCol();
1433 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1434 if (!InlinedAtDL.isUnknown()) {
1435 CommentOS << " @[ ";
1436 printDebugLoc(InlinedAtDL, MF, CommentOS);
1442 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1443 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1444 const MachineFunction *MF = 0;
1445 const MachineRegisterInfo *MRI = 0;
1446 if (const MachineBasicBlock *MBB = getParent()) {
1447 MF = MBB->getParent();
1449 TM = &MF->getTarget();
1451 MRI = &MF->getRegInfo();
1454 // Save a list of virtual registers.
1455 SmallVector<unsigned, 8> VirtRegs;
1457 // Print explicitly defined operands on the left of an assignment syntax.
1458 unsigned StartOp = 0, e = getNumOperands();
1459 for (; StartOp < e && getOperand(StartOp).isReg() &&
1460 getOperand(StartOp).isDef() &&
1461 !getOperand(StartOp).isImplicit();
1463 if (StartOp != 0) OS << ", ";
1464 getOperand(StartOp).print(OS, TM);
1465 unsigned Reg = getOperand(StartOp).getReg();
1466 if (TargetRegisterInfo::isVirtualRegister(Reg))
1467 VirtRegs.push_back(Reg);
1473 // Print the opcode name.
1474 OS << getDesc().getName();
1476 // Print the rest of the operands.
1477 bool OmittedAnyCallClobbers = false;
1478 bool FirstOp = true;
1479 unsigned AsmDescOp = ~0u;
1480 unsigned AsmOpCount = 0;
1482 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1483 // Print asm string.
1485 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1487 // Print HasSideEffects, IsAlignStack
1488 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1489 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1490 OS << " [sideeffect]";
1491 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1492 OS << " [alignstack]";
1494 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1499 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1500 const MachineOperand &MO = getOperand(i);
1502 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1503 VirtRegs.push_back(MO.getReg());
1505 // Omit call-clobbered registers which aren't used anywhere. This makes
1506 // call instructions much less noisy on targets where calls clobber lots
1507 // of registers. Don't rely on MO.isDead() because we may be called before
1508 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1509 if (MF && isCall() &&
1510 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1511 unsigned Reg = MO.getReg();
1512 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1513 const MachineRegisterInfo &MRI = MF->getRegInfo();
1514 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1515 bool HasAliasLive = false;
1516 for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1517 unsigned AliasReg = *Alias; ++Alias)
1518 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1519 HasAliasLive = true;
1522 if (!HasAliasLive) {
1523 OmittedAnyCallClobbers = true;
1530 if (FirstOp) FirstOp = false; else OS << ",";
1532 if (i < getDesc().NumOperands) {
1533 const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1534 if (MCOI.isPredicate())
1536 if (MCOI.isOptionalDef())
1539 if (isDebugValue() && MO.isMetadata()) {
1540 // Pretty print DBG_VALUE instructions.
1541 const MDNode *MD = MO.getMetadata();
1542 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1543 OS << "!\"" << MDS->getString() << '\"';
1546 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1547 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1548 } else if (i == AsmDescOp && MO.isImm()) {
1549 // Pretty print the inline asm operand descriptor.
1550 OS << '$' << AsmOpCount++;
1551 unsigned Flag = MO.getImm();
1552 switch (InlineAsm::getKind(Flag)) {
1553 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1554 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1555 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1556 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1557 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1558 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1559 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1563 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1565 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1567 OS << ":RC" << RCID;
1570 unsigned TiedTo = 0;
1571 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1572 OS << " tiedto:$" << TiedTo;
1576 // Compute the index of the next operand descriptor.
1577 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1582 // Briefly indicate whether any call clobbers were omitted.
1583 if (OmittedAnyCallClobbers) {
1584 if (!FirstOp) OS << ",";
1588 bool HaveSemi = false;
1590 if (!HaveSemi) OS << ";"; HaveSemi = true;
1593 if (Flags & FrameSetup)
1597 if (!memoperands_empty()) {
1598 if (!HaveSemi) OS << ";"; HaveSemi = true;
1601 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1604 if (llvm::next(i) != e)
1609 // Print the regclass of any virtual registers encountered.
1610 if (MRI && !VirtRegs.empty()) {
1611 if (!HaveSemi) OS << ";"; HaveSemi = true;
1612 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1613 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1614 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1615 for (unsigned j = i+1; j != VirtRegs.size();) {
1616 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1620 if (VirtRegs[i] != VirtRegs[j])
1621 OS << "," << PrintReg(VirtRegs[j]);
1622 VirtRegs.erase(VirtRegs.begin()+j);
1627 // Print debug location information.
1628 if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1629 if (!HaveSemi) OS << ";"; HaveSemi = true;
1630 DIVariable DV(getOperand(e - 1).getMetadata());
1631 OS << " line no:" << DV.getLineNumber();
1632 if (MDNode *InlinedAt = DV.getInlinedAt()) {
1633 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1634 if (!InlinedAtDL.isUnknown()) {
1635 OS << " inlined @[ ";
1636 printDebugLoc(InlinedAtDL, MF, OS);
1640 } else if (!debugLoc.isUnknown() && MF) {
1641 if (!HaveSemi) OS << ";"; HaveSemi = true;
1643 printDebugLoc(debugLoc, MF, OS);
1649 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1650 const TargetRegisterInfo *RegInfo,
1651 bool AddIfNotFound) {
1652 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1653 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1655 SmallVector<unsigned,4> DeadOps;
1656 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1657 MachineOperand &MO = getOperand(i);
1658 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1660 unsigned Reg = MO.getReg();
1664 if (Reg == IncomingReg) {
1667 // The register is already marked kill.
1669 if (isPhysReg && isRegTiedToDefOperand(i))
1670 // Two-address uses of physregs must not be marked kill.
1675 } else if (hasAliases && MO.isKill() &&
1676 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1677 // A super-register kill already exists.
1678 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1680 if (RegInfo->isSubRegister(IncomingReg, Reg))
1681 DeadOps.push_back(i);
1685 // Trim unneeded kill operands.
1686 while (!DeadOps.empty()) {
1687 unsigned OpIdx = DeadOps.back();
1688 if (getOperand(OpIdx).isImplicit())
1689 RemoveOperand(OpIdx);
1691 getOperand(OpIdx).setIsKill(false);
1695 // If not found, this means an alias of one of the operands is killed. Add a
1696 // new implicit operand if required.
1697 if (!Found && AddIfNotFound) {
1698 addOperand(MachineOperand::CreateReg(IncomingReg,
1707 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1708 const TargetRegisterInfo *RegInfo,
1709 bool AddIfNotFound) {
1710 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1711 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1713 SmallVector<unsigned,4> DeadOps;
1714 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1715 MachineOperand &MO = getOperand(i);
1716 if (!MO.isReg() || !MO.isDef())
1718 unsigned Reg = MO.getReg();
1722 if (Reg == IncomingReg) {
1725 } else if (hasAliases && MO.isDead() &&
1726 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1727 // There exists a super-register that's marked dead.
1728 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1730 if (RegInfo->getSubRegisters(IncomingReg) &&
1731 RegInfo->getSuperRegisters(Reg) &&
1732 RegInfo->isSubRegister(IncomingReg, Reg))
1733 DeadOps.push_back(i);
1737 // Trim unneeded dead operands.
1738 while (!DeadOps.empty()) {
1739 unsigned OpIdx = DeadOps.back();
1740 if (getOperand(OpIdx).isImplicit())
1741 RemoveOperand(OpIdx);
1743 getOperand(OpIdx).setIsDead(false);
1747 // If not found, this means an alias of one of the operands is dead. Add a
1748 // new implicit operand if required.
1749 if (Found || !AddIfNotFound)
1752 addOperand(MachineOperand::CreateReg(IncomingReg,
1760 void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1761 const TargetRegisterInfo *RegInfo) {
1762 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1763 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1767 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1768 const MachineOperand &MO = getOperand(i);
1769 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1770 MO.getSubReg() == 0)
1774 addOperand(MachineOperand::CreateReg(IncomingReg,
1779 void MachineInstr::setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
1780 const TargetRegisterInfo &TRI) {
1781 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1782 MachineOperand &MO = getOperand(i);
1783 if (!MO.isReg() || !MO.isDef()) continue;
1784 unsigned Reg = MO.getReg();
1785 if (Reg == 0) continue;
1787 for (SmallVectorImpl<unsigned>::const_iterator I = UsedRegs.begin(),
1788 E = UsedRegs.end(); I != E; ++I)
1789 if (TRI.regsOverlap(*I, Reg)) {
1793 // If there are no uses, including partial uses, the def is dead.
1794 if (Dead) MO.setIsDead();
1799 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1800 unsigned Hash = MI->getOpcode() * 37;
1801 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1802 const MachineOperand &MO = MI->getOperand(i);
1803 uint64_t Key = (uint64_t)MO.getType() << 32;
1804 switch (MO.getType()) {
1806 case MachineOperand::MO_Register:
1807 if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1808 continue; // Skip virtual register defs.
1811 case MachineOperand::MO_Immediate:
1814 case MachineOperand::MO_FrameIndex:
1815 case MachineOperand::MO_ConstantPoolIndex:
1816 case MachineOperand::MO_JumpTableIndex:
1817 Key |= MO.getIndex();
1819 case MachineOperand::MO_MachineBasicBlock:
1820 Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1822 case MachineOperand::MO_GlobalAddress:
1823 Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1825 case MachineOperand::MO_BlockAddress:
1826 Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1828 case MachineOperand::MO_MCSymbol:
1829 Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol());
1832 Key += ~(Key << 32);
1834 Key += ~(Key << 13);
1838 Key += ~(Key << 27);
1840 Hash = (unsigned)Key + Hash * 37;
1845 void MachineInstr::emitError(StringRef Msg) const {
1846 // Find the source location cookie.
1847 unsigned LocCookie = 0;
1848 const MDNode *LocMD = 0;
1849 for (unsigned i = getNumOperands(); i != 0; --i) {
1850 if (getOperand(i-1).isMetadata() &&
1851 (LocMD = getOperand(i-1).getMetadata()) &&
1852 LocMD->getNumOperands() != 0) {
1853 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1854 LocCookie = CI->getZExtValue();
1860 if (const MachineBasicBlock *MBB = getParent())
1861 if (const MachineFunction *MF = MBB->getParent())
1862 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1863 report_fatal_error(Msg);