1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 //===----------------------------------------------------------------------===//
5 #include "llvm/CodeGen/MachineInstr.h"
6 #include "llvm/CodeGen/MachineBasicBlock.h"
7 #include "llvm/Value.h"
8 #include "llvm/Target/TargetMachine.h"
9 #include "llvm/Target/MachineInstrInfo.h"
10 #include "llvm/Target/MRegisterInfo.h"
13 // Global variable holding an array of descriptors for machine instructions.
14 // The actual object needs to be created separately for each target machine.
15 // This variable is initialized and reset by class MachineInstrInfo.
17 // FIXME: This should be a property of the target so that more than one target
18 // at a time can be active...
20 extern const MachineInstrDescriptor *TargetInstrDescriptors;
22 // Constructor for instructions with fixed #operands (nearly all)
23 MachineInstr::MachineInstr(MachineOpCode _opCode)
25 operands(TargetInstrDescriptors[_opCode].numOperands, MachineOperand()),
28 assert(TargetInstrDescriptors[_opCode].numOperands >= 0);
31 // Constructor for instructions with variable #operands
32 MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
34 operands(numOperands, MachineOperand()),
39 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
40 /// not a resize for them. It is expected that if you use this that you call
41 /// add* methods below to fill up the operands, instead of the Set methods.
42 /// Eventually, the "resizing" ctors will be phased out.
44 MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
49 operands.reserve(numOperands);
52 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
53 /// MachineInstr is created and added to the end of the specified basic block.
55 MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
60 assert(MBB && "Cannot use inserting ctor with null basic block!");
61 operands.reserve(numOperands);
62 MBB->push_back(this); // Add instruction to end of basic block!
66 // OperandComplete - Return true if it's illegal to add a new operand
67 bool MachineInstr::OperandsComplete() const
69 int NumOperands = TargetInstrDescriptors[opCode].numOperands;
70 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
71 return true; // Broken!
77 // Support for replacing opcode and operands of a MachineInstr in place.
78 // This only resets the size of the operand vector and initializes it.
79 // The new operands must be set explicitly later.
81 void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands)
83 assert(getNumImplicitRefs() == 0 &&
84 "This is probably broken because implicit refs are going to be lost.");
87 operands.resize(numOperands, MachineOperand());
91 MachineInstr::SetMachineOperandVal(unsigned i,
92 MachineOperand::MachineOperandType opType,
97 assert(i < operands.size()); // may be explicit or implicit op
98 operands[i].opType = opType;
99 operands[i].value = V;
100 operands[i].regNum = -1;
103 operands[i].flags = MachineOperand::DEFUSEFLAG;
104 else if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
105 operands[i].flags = MachineOperand::DEFFLAG;
107 operands[i].flags = 0;
111 MachineInstr::SetMachineOperandConst(unsigned i,
112 MachineOperand::MachineOperandType operandType,
115 assert(i < getNumOperands()); // must be explicit op
116 assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
117 "immed. constant cannot be defined");
119 operands[i].opType = operandType;
120 operands[i].value = NULL;
121 operands[i].immedVal = intValue;
122 operands[i].regNum = -1;
123 operands[i].flags = 0;
127 MachineInstr::SetMachineOperandReg(unsigned i,
130 assert(i < getNumOperands()); // must be explicit op
132 operands[i].opType = MachineOperand::MO_MachineRegister;
133 operands[i].value = NULL;
134 operands[i].regNum = regNum;
136 if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
137 operands[i].flags = MachineOperand::DEFFLAG;
139 operands[i].flags = 0;
141 insertUsedReg(regNum);
145 MachineInstr::SetRegForOperand(unsigned i, int regNum)
147 assert(i < getNumOperands()); // must be explicit op
148 operands[i].setRegForValue(regNum);
149 insertUsedReg(regNum);
153 // Subsitute all occurrences of Value* oldVal with newVal in all operands
154 // and all implicit refs. If defsOnly == true, substitute defs only.
156 MachineInstr::substituteValue(const Value* oldVal, Value* newVal, bool defsOnly)
158 unsigned numSubst = 0;
160 // Subsitute operands
161 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
163 if (!defsOnly || O.isDef())
165 O.getMachineOperand().value = newVal;
169 // Subsitute implicit refs
170 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
171 if (getImplicitRef(i) == oldVal)
172 if (!defsOnly || implicitRefIsDefined(i))
174 getImplicitOp(i).value = newVal;
183 MachineInstr::dump() const
185 cerr << " " << *this;
188 static inline std::ostream&
189 OutputValue(std::ostream &os, const Value* val)
192 if (val && val->hasName())
193 return os << val->getName() << ")";
195 return os << (void*) val << ")"; // print address only
198 static inline void OutputReg(std::ostream &os, unsigned RegNo,
199 const MRegisterInfo *MRI = 0) {
201 if (RegNo < MRegisterInfo::FirstVirtualRegister)
202 os << "%" << MRI->get(RegNo).Name;
204 os << "%reg" << RegNo;
206 os << "%mreg(" << RegNo << ")";
209 static void print(const MachineOperand &MO, std::ostream &OS,
210 const TargetMachine &TM) {
211 const MRegisterInfo *MRI = TM.getRegisterInfo();
212 bool CloseParen = true;
215 else if (MO.opLoBits32())
217 else if (MO.opHiBits64())
219 else if (MO.opLoBits64())
224 switch (MO.getType()) {
225 case MachineOperand::MO_VirtualRegister:
226 if (MO.getVRegValue()) {
228 OutputValue(OS, MO.getVRegValue());
229 if (MO.hasAllocatedReg())
232 if (MO.hasAllocatedReg())
233 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
235 case MachineOperand::MO_CCRegister:
237 OutputValue(OS, MO.getVRegValue());
238 if (MO.hasAllocatedReg()) {
240 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
243 case MachineOperand::MO_MachineRegister:
244 OutputReg(OS, MO.getMachineRegNum(), MRI);
246 case MachineOperand::MO_SignExtendedImmed:
247 OS << (long)MO.getImmedValue();
249 case MachineOperand::MO_UnextendedImmed:
250 OS << (long)MO.getImmedValue();
252 case MachineOperand::MO_PCRelativeDisp: {
253 const Value* opVal = MO.getVRegValue();
254 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
255 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
256 if (opVal->hasName())
257 OS << opVal->getName();
259 OS << (const void*) opVal;
264 assert(0 && "Unrecognized operand type");
271 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
272 unsigned StartOp = 0;
274 // Specialize printing if op#0 is definition
275 if (getNumOperands() && operandIsDefined(0)) {
276 ::print(getOperand(0), OS, TM);
278 ++StartOp; // Don't print this operand again!
280 OS << TM.getInstrInfo().getName(getOpcode());
282 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
286 ::print(getOperand(i), OS, TM);
288 if (operandIsDefinedAndUsed(i))
290 else if (operandIsDefined(i))
294 // code for printing implict references
295 if (getNumImplicitRefs()) {
296 OS << "\tImplicitRefs: ";
297 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
299 OutputValue(OS, getImplicitRef(i));
300 if (implicitRefIsDefinedAndUsed(i))
302 else if (implicitRefIsDefined(i))
311 std::ostream &operator<<(std::ostream& os, const MachineInstr& minstr)
313 os << TargetInstrDescriptors[minstr.opCode].Name;
315 for (unsigned i=0, N=minstr.getNumOperands(); i < N; i++) {
316 os << "\t" << minstr.getOperand(i);
317 if( minstr.operandIsDefined(i) )
319 if( minstr.operandIsDefinedAndUsed(i) )
323 // code for printing implict references
324 unsigned NumOfImpRefs = minstr.getNumImplicitRefs();
325 if( NumOfImpRefs > 0 ) {
326 os << "\tImplicit: ";
327 for(unsigned z=0; z < NumOfImpRefs; z++) {
328 OutputValue(os, minstr.getImplicitRef(z));
329 if( minstr.implicitRefIsDefined(z)) os << "*";
330 if( minstr.implicitRefIsDefinedAndUsed(z)) os << "*";
338 std::ostream &operator<<(std::ostream &os, const MachineOperand &mop)
340 if (mop.opHiBits32())
342 else if (mop.opLoBits32())
344 else if (mop.opHiBits64())
346 else if (mop.opLoBits64())
349 switch (mop.getType())
351 case MachineOperand::MO_VirtualRegister:
353 OutputValue(os, mop.getVRegValue());
354 if (mop.hasAllocatedReg()) {
356 OutputReg(os, mop.getAllocatedRegNum());
359 case MachineOperand::MO_CCRegister:
361 OutputValue(os, mop.getVRegValue());
362 if (mop.hasAllocatedReg()) {
364 OutputReg(os, mop.getAllocatedRegNum());
367 case MachineOperand::MO_MachineRegister:
368 OutputReg(os, mop.getMachineRegNum());
370 case MachineOperand::MO_SignExtendedImmed:
371 os << (long)mop.getImmedValue();
373 case MachineOperand::MO_UnextendedImmed:
374 os << (long)mop.getImmedValue();
376 case MachineOperand::MO_PCRelativeDisp:
378 const Value* opVal = mop.getVRegValue();
379 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
380 os << "%disp(" << (isLabel? "label " : "addr-of-val ");
381 if (opVal->hasName())
382 os << opVal->getName();
384 os << (const void*) opVal;
389 assert(0 && "Unrecognized operand type");
394 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
395 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))