1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/ADT/FoldingSet.h"
16 #include "llvm/ADT/Hashing.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/CodeGen/MachineConstantPool.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/DebugInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/InlineAsm.h"
28 #include "llvm/IR/LLVMContext.h"
29 #include "llvm/IR/Metadata.h"
30 #include "llvm/IR/Module.h"
31 #include "llvm/IR/ModuleSlotTracker.h"
32 #include "llvm/IR/Type.h"
33 #include "llvm/IR/Value.h"
34 #include "llvm/MC/MCInstrDesc.h"
35 #include "llvm/MC/MCSymbol.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
43 #include "llvm/Target/TargetSubtargetInfo.h"
46 //===----------------------------------------------------------------------===//
47 // MachineOperand Implementation
48 //===----------------------------------------------------------------------===//
50 void MachineOperand::setReg(unsigned Reg) {
51 if (getReg() == Reg) return; // No change.
53 // Otherwise, we have to change the register. If this operand is embedded
54 // into a machine function, we need to update the old and new register's
56 if (MachineInstr *MI = getParent())
57 if (MachineBasicBlock *MBB = MI->getParent())
58 if (MachineFunction *MF = MBB->getParent()) {
59 MachineRegisterInfo &MRI = MF->getRegInfo();
60 MRI.removeRegOperandFromUseList(this);
61 SmallContents.RegNo = Reg;
62 MRI.addRegOperandToUseList(this);
66 // Otherwise, just change the register, no problem. :)
67 SmallContents.RegNo = Reg;
70 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
71 const TargetRegisterInfo &TRI) {
72 assert(TargetRegisterInfo::isVirtualRegister(Reg));
73 if (SubIdx && getSubReg())
74 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
80 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
81 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
83 Reg = TRI.getSubReg(Reg, getSubReg());
84 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
85 // That won't happen in legal code.
91 /// Change a def to a use, or a use to a def.
92 void MachineOperand::setIsDef(bool Val) {
93 assert(isReg() && "Wrong MachineOperand accessor");
94 assert((!Val || !isDebug()) && "Marking a debug operation as def");
97 // MRI may keep uses and defs in different list positions.
98 if (MachineInstr *MI = getParent())
99 if (MachineBasicBlock *MBB = MI->getParent())
100 if (MachineFunction *MF = MBB->getParent()) {
101 MachineRegisterInfo &MRI = MF->getRegInfo();
102 MRI.removeRegOperandFromUseList(this);
104 MRI.addRegOperandToUseList(this);
110 // If this operand is currently a register operand, and if this is in a
111 // function, deregister the operand from the register's use/def list.
112 void MachineOperand::removeRegFromUses() {
113 if (!isReg() || !isOnRegUseList())
116 if (MachineInstr *MI = getParent()) {
117 if (MachineBasicBlock *MBB = MI->getParent()) {
118 if (MachineFunction *MF = MBB->getParent())
119 MF->getRegInfo().removeRegOperandFromUseList(this);
124 /// ChangeToImmediate - Replace this operand with a new immediate operand of
125 /// the specified value. If an operand is known to be an immediate already,
126 /// the setImm method should be used.
127 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
128 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
132 OpKind = MO_Immediate;
133 Contents.ImmVal = ImmVal;
136 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
137 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
141 OpKind = MO_FPImmediate;
142 Contents.CFP = FPImm;
145 void MachineOperand::ChangeToES(const char *SymName, unsigned char TargetFlags) {
146 assert((!isReg() || !isTied()) &&
147 "Cannot change a tied operand into an external symbol");
151 OpKind = MO_ExternalSymbol;
152 Contents.OffsetedInfo.Val.SymbolName = SymName;
153 setOffset(0); // Offset is always 0.
154 setTargetFlags(TargetFlags);
157 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
158 assert((!isReg() || !isTied()) &&
159 "Cannot change a tied operand into an MCSymbol");
163 OpKind = MO_MCSymbol;
167 /// ChangeToRegister - Replace this operand with a new register operand of
168 /// the specified value. If an operand is known to be an register already,
169 /// the setReg method should be used.
170 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
171 bool isKill, bool isDead, bool isUndef,
173 MachineRegisterInfo *RegInfo = nullptr;
174 if (MachineInstr *MI = getParent())
175 if (MachineBasicBlock *MBB = MI->getParent())
176 if (MachineFunction *MF = MBB->getParent())
177 RegInfo = &MF->getRegInfo();
178 // If this operand is already a register operand, remove it from the
179 // register's use/def lists.
180 bool WasReg = isReg();
181 if (RegInfo && WasReg)
182 RegInfo->removeRegOperandFromUseList(this);
184 // Change this to a register and set the reg#.
185 OpKind = MO_Register;
186 SmallContents.RegNo = Reg;
187 SubReg_TargetFlags = 0;
193 IsInternalRead = false;
194 IsEarlyClobber = false;
196 // Ensure isOnRegUseList() returns false.
197 Contents.Reg.Prev = nullptr;
198 // Preserve the tie when the operand was already a register.
202 // If this operand is embedded in a function, add the operand to the
203 // register's use/def list.
205 RegInfo->addRegOperandToUseList(this);
208 /// isIdenticalTo - Return true if this operand is identical to the specified
209 /// operand. Note that this should stay in sync with the hash_value overload
211 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
212 if (getType() != Other.getType() ||
213 getTargetFlags() != Other.getTargetFlags())
217 case MachineOperand::MO_Register:
218 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
219 getSubReg() == Other.getSubReg();
220 case MachineOperand::MO_Immediate:
221 return getImm() == Other.getImm();
222 case MachineOperand::MO_CImmediate:
223 return getCImm() == Other.getCImm();
224 case MachineOperand::MO_FPImmediate:
225 return getFPImm() == Other.getFPImm();
226 case MachineOperand::MO_MachineBasicBlock:
227 return getMBB() == Other.getMBB();
228 case MachineOperand::MO_FrameIndex:
229 return getIndex() == Other.getIndex();
230 case MachineOperand::MO_ConstantPoolIndex:
231 case MachineOperand::MO_TargetIndex:
232 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
233 case MachineOperand::MO_JumpTableIndex:
234 return getIndex() == Other.getIndex();
235 case MachineOperand::MO_GlobalAddress:
236 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
237 case MachineOperand::MO_ExternalSymbol:
238 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
239 getOffset() == Other.getOffset();
240 case MachineOperand::MO_BlockAddress:
241 return getBlockAddress() == Other.getBlockAddress() &&
242 getOffset() == Other.getOffset();
243 case MachineOperand::MO_RegisterMask:
244 case MachineOperand::MO_RegisterLiveOut:
245 return getRegMask() == Other.getRegMask();
246 case MachineOperand::MO_MCSymbol:
247 return getMCSymbol() == Other.getMCSymbol();
248 case MachineOperand::MO_CFIIndex:
249 return getCFIIndex() == Other.getCFIIndex();
250 case MachineOperand::MO_Metadata:
251 return getMetadata() == Other.getMetadata();
253 llvm_unreachable("Invalid machine operand type");
256 // Note: this must stay exactly in sync with isIdenticalTo above.
257 hash_code llvm::hash_value(const MachineOperand &MO) {
258 switch (MO.getType()) {
259 case MachineOperand::MO_Register:
260 // Register operands don't have target flags.
261 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
262 case MachineOperand::MO_Immediate:
263 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
264 case MachineOperand::MO_CImmediate:
265 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
266 case MachineOperand::MO_FPImmediate:
267 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
268 case MachineOperand::MO_MachineBasicBlock:
269 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
270 case MachineOperand::MO_FrameIndex:
271 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
272 case MachineOperand::MO_ConstantPoolIndex:
273 case MachineOperand::MO_TargetIndex:
274 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
276 case MachineOperand::MO_JumpTableIndex:
277 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
278 case MachineOperand::MO_ExternalSymbol:
279 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
281 case MachineOperand::MO_GlobalAddress:
282 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
284 case MachineOperand::MO_BlockAddress:
285 return hash_combine(MO.getType(), MO.getTargetFlags(),
286 MO.getBlockAddress(), MO.getOffset());
287 case MachineOperand::MO_RegisterMask:
288 case MachineOperand::MO_RegisterLiveOut:
289 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
290 case MachineOperand::MO_Metadata:
291 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
292 case MachineOperand::MO_MCSymbol:
293 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
294 case MachineOperand::MO_CFIIndex:
295 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
297 llvm_unreachable("Invalid machine operand type");
300 void MachineOperand::print(raw_ostream &OS,
301 const TargetRegisterInfo *TRI) const {
302 ModuleSlotTracker DummyMST(nullptr);
303 print(OS, DummyMST, TRI);
306 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
307 const TargetRegisterInfo *TRI) const {
309 case MachineOperand::MO_Register:
310 OS << PrintReg(getReg(), TRI, getSubReg());
312 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
313 isInternalRead() || isEarlyClobber() || isTied()) {
315 bool NeedComma = false;
317 if (NeedComma) OS << ',';
318 if (isEarlyClobber())
319 OS << "earlyclobber,";
324 // <def,read-undef> only makes sense when getSubReg() is set.
325 // Don't clutter the output otherwise.
326 if (isUndef() && getSubReg())
328 } else if (isImplicit()) {
334 if (NeedComma) OS << ',';
339 if (NeedComma) OS << ',';
343 if (isUndef() && isUse()) {
344 if (NeedComma) OS << ',';
348 if (isInternalRead()) {
349 if (NeedComma) OS << ',';
354 if (NeedComma) OS << ',';
357 OS << unsigned(TiedTo - 1);
362 case MachineOperand::MO_Immediate:
365 case MachineOperand::MO_CImmediate:
366 getCImm()->getValue().print(OS, false);
368 case MachineOperand::MO_FPImmediate:
369 if (getFPImm()->getType()->isFloatTy())
370 OS << getFPImm()->getValueAPF().convertToFloat();
372 OS << getFPImm()->getValueAPF().convertToDouble();
374 case MachineOperand::MO_MachineBasicBlock:
375 OS << "<BB#" << getMBB()->getNumber() << ">";
377 case MachineOperand::MO_FrameIndex:
378 OS << "<fi#" << getIndex() << '>';
380 case MachineOperand::MO_ConstantPoolIndex:
381 OS << "<cp#" << getIndex();
382 if (getOffset()) OS << "+" << getOffset();
385 case MachineOperand::MO_TargetIndex:
386 OS << "<ti#" << getIndex();
387 if (getOffset()) OS << "+" << getOffset();
390 case MachineOperand::MO_JumpTableIndex:
391 OS << "<jt#" << getIndex() << '>';
393 case MachineOperand::MO_GlobalAddress:
395 getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
396 if (getOffset()) OS << "+" << getOffset();
399 case MachineOperand::MO_ExternalSymbol:
400 OS << "<es:" << getSymbolName();
401 if (getOffset()) OS << "+" << getOffset();
404 case MachineOperand::MO_BlockAddress:
406 getBlockAddress()->printAsOperand(OS, /*PrintType=*/false, MST);
407 if (getOffset()) OS << "+" << getOffset();
410 case MachineOperand::MO_RegisterMask:
413 case MachineOperand::MO_RegisterLiveOut:
414 OS << "<regliveout>";
416 case MachineOperand::MO_Metadata:
418 getMetadata()->printAsOperand(OS, MST);
421 case MachineOperand::MO_MCSymbol:
422 OS << "<MCSym=" << *getMCSymbol() << '>';
424 case MachineOperand::MO_CFIIndex:
425 OS << "<call frame instruction>";
429 if (unsigned TF = getTargetFlags())
430 OS << "[TF=" << TF << ']';
433 //===----------------------------------------------------------------------===//
434 // MachineMemOperand Implementation
435 //===----------------------------------------------------------------------===//
437 /// getAddrSpace - Return the LLVM IR address space number that this pointer
439 unsigned MachinePointerInfo::getAddrSpace() const {
440 if (V.isNull() || V.is<const PseudoSourceValue*>()) return 0;
441 return cast<PointerType>(V.get<const Value*>()->getType())->getAddressSpace();
444 /// getConstantPool - Return a MachinePointerInfo record that refers to the
446 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
447 return MachinePointerInfo(MF.getPSVManager().getConstantPool());
450 /// getFixedStack - Return a MachinePointerInfo record that refers to the
451 /// the specified FrameIndex.
452 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
453 int FI, int64_t Offset) {
454 return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
457 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
458 return MachinePointerInfo(MF.getPSVManager().getJumpTable());
461 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
462 return MachinePointerInfo(MF.getPSVManager().getGOT());
465 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
467 return MachinePointerInfo(MF.getPSVManager().getStack(), Offset);
470 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
471 uint64_t s, unsigned int a,
472 const AAMDNodes &AAInfo,
473 const MDNode *Ranges)
474 : PtrInfo(ptrinfo), Size(s),
475 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
476 AAInfo(AAInfo), Ranges(Ranges) {
477 assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue*>() ||
478 isa<PointerType>(PtrInfo.V.get<const Value*>()->getType())) &&
479 "invalid pointer value");
480 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
481 assert((isLoad() || isStore()) && "Not a load/store!");
484 /// Profile - Gather unique data for the object.
486 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
487 ID.AddInteger(getOffset());
489 ID.AddPointer(getOpaqueValue());
490 ID.AddInteger(Flags);
493 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
494 // The Value and Offset may differ due to CSE. But the flags and size
495 // should be the same.
496 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
497 assert(MMO->getSize() == getSize() && "Size mismatch!");
499 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
500 // Update the alignment value.
501 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
502 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
503 // Also update the base and offset, because the new alignment may
504 // not be applicable with the old ones.
505 PtrInfo = MMO->PtrInfo;
509 /// getAlignment - Return the minimum known alignment in bytes of the
510 /// actual memory reference.
511 uint64_t MachineMemOperand::getAlignment() const {
512 return MinAlign(getBaseAlignment(), getOffset());
515 void MachineMemOperand::print(raw_ostream &OS) const {
516 ModuleSlotTracker DummyMST(nullptr);
519 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
520 assert((isLoad() || isStore()) &&
521 "SV has to be a load, store or both.");
532 // Print the address information.
534 if (const Value *V = getValue())
535 V->printAsOperand(OS, /*PrintType=*/false, MST);
536 else if (const PseudoSourceValue *PSV = getPseudoValue())
537 PSV->printCustom(OS);
541 unsigned AS = getAddrSpace();
543 OS << "(addrspace=" << AS << ')';
545 // If the alignment of the memory reference itself differs from the alignment
546 // of the base pointer, print the base alignment explicitly, next to the base
548 if (getBaseAlignment() != getAlignment())
549 OS << "(align=" << getBaseAlignment() << ")";
551 if (getOffset() != 0)
552 OS << "+" << getOffset();
555 // Print the alignment of the reference.
556 if (getBaseAlignment() != getAlignment() || getBaseAlignment() != getSize())
557 OS << "(align=" << getAlignment() << ")";
560 if (const MDNode *TBAAInfo = getAAInfo().TBAA) {
562 if (TBAAInfo->getNumOperands() > 0)
563 TBAAInfo->getOperand(0)->printAsOperand(OS, MST);
569 // Print AA scope info.
570 if (const MDNode *ScopeInfo = getAAInfo().Scope) {
571 OS << "(alias.scope=";
572 if (ScopeInfo->getNumOperands() > 0)
573 for (unsigned i = 0, ie = ScopeInfo->getNumOperands(); i != ie; ++i) {
574 ScopeInfo->getOperand(i)->printAsOperand(OS, MST);
583 // Print AA noalias scope info.
584 if (const MDNode *NoAliasInfo = getAAInfo().NoAlias) {
586 if (NoAliasInfo->getNumOperands() > 0)
587 for (unsigned i = 0, ie = NoAliasInfo->getNumOperands(); i != ie; ++i) {
588 NoAliasInfo->getOperand(i)->printAsOperand(OS, MST);
597 // Print nontemporal info.
599 OS << "(nontemporal)";
605 //===----------------------------------------------------------------------===//
606 // MachineInstr Implementation
607 //===----------------------------------------------------------------------===//
609 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
610 if (MCID->ImplicitDefs)
611 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
612 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
613 if (MCID->ImplicitUses)
614 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
615 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
618 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
619 /// implicit operands. It reserves space for the number of operands specified by
621 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
622 DebugLoc dl, bool NoImp)
623 : MCID(&tid), Parent(nullptr), Operands(nullptr), NumOperands(0), Flags(0),
624 AsmPrinterFlags(0), NumMemRefs(0), MemRefs(nullptr),
625 debugLoc(std::move(dl)) {
626 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
628 // Reserve space for the expected number of operands.
629 if (unsigned NumOps = MCID->getNumOperands() +
630 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
631 CapOperands = OperandCapacity::get(NumOps);
632 Operands = MF.allocateOperandArray(CapOperands);
636 addImplicitDefUseOperands(MF);
639 /// MachineInstr ctor - Copies MachineInstr arg exactly
641 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
642 : MCID(&MI.getDesc()), Parent(nullptr), Operands(nullptr), NumOperands(0),
643 Flags(0), AsmPrinterFlags(0),
644 NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
645 debugLoc(MI.getDebugLoc()) {
646 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
648 CapOperands = OperandCapacity::get(MI.getNumOperands());
649 Operands = MF.allocateOperandArray(CapOperands);
652 for (const MachineOperand &MO : MI.operands())
655 // Copy all the sensible flags.
659 /// getRegInfo - If this instruction is embedded into a MachineFunction,
660 /// return the MachineRegisterInfo object for the current function, otherwise
662 MachineRegisterInfo *MachineInstr::getRegInfo() {
663 if (MachineBasicBlock *MBB = getParent())
664 return &MBB->getParent()->getRegInfo();
668 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
669 /// this instruction from their respective use lists. This requires that the
670 /// operands already be on their use lists.
671 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
672 for (MachineOperand &MO : operands())
674 MRI.removeRegOperandFromUseList(&MO);
677 /// AddRegOperandsToUseLists - Add all of the register operands in
678 /// this instruction from their respective use lists. This requires that the
679 /// operands not be on their use lists yet.
680 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
681 for (MachineOperand &MO : operands())
683 MRI.addRegOperandToUseList(&MO);
686 void MachineInstr::addOperand(const MachineOperand &Op) {
687 MachineBasicBlock *MBB = getParent();
688 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
689 MachineFunction *MF = MBB->getParent();
690 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
694 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
695 /// ranges. If MRI is non-null also update use-def chains.
696 static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
697 unsigned NumOps, MachineRegisterInfo *MRI) {
699 return MRI->moveOperands(Dst, Src, NumOps);
701 // MachineOperand is a trivially copyable type so we can just use memmove.
702 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
705 /// addOperand - Add the specified operand to the instruction. If it is an
706 /// implicit operand, it is added to the end of the operand list. If it is
707 /// an explicit operand it is added at the end of the explicit operand list
708 /// (before the first implicit operand).
709 void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
710 assert(MCID && "Cannot add operands before providing an instr descriptor");
712 // Check if we're adding one of our existing operands.
713 if (&Op >= Operands && &Op < Operands + NumOperands) {
714 // This is unusual: MI->addOperand(MI->getOperand(i)).
715 // If adding Op requires reallocating or moving existing operands around,
716 // the Op reference could go stale. Support it by copying Op.
717 MachineOperand CopyOp(Op);
718 return addOperand(MF, CopyOp);
721 // Find the insert location for the new operand. Implicit registers go at
722 // the end, everything else goes before the implicit regs.
724 // FIXME: Allow mixed explicit and implicit operands on inline asm.
725 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
726 // implicit-defs, but they must not be moved around. See the FIXME in
728 unsigned OpNo = getNumOperands();
729 bool isImpReg = Op.isReg() && Op.isImplicit();
730 if (!isImpReg && !isInlineAsm()) {
731 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
733 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
738 bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
739 // OpNo now points as the desired insertion point. Unless this is a variadic
740 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
741 // RegMask operands go between the explicit and implicit operands.
742 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
743 OpNo < MCID->getNumOperands() || isMetaDataOp) &&
744 "Trying to add an operand to a machine instr that is already done!");
747 MachineRegisterInfo *MRI = getRegInfo();
749 // Determine if the Operands array needs to be reallocated.
750 // Save the old capacity and operand array.
751 OperandCapacity OldCap = CapOperands;
752 MachineOperand *OldOperands = Operands;
753 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
754 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
755 Operands = MF.allocateOperandArray(CapOperands);
756 // Move the operands before the insertion point.
758 moveOperands(Operands, OldOperands, OpNo, MRI);
761 // Move the operands following the insertion point.
762 if (OpNo != NumOperands)
763 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
767 // Deallocate the old operand array.
768 if (OldOperands != Operands && OldOperands)
769 MF.deallocateOperandArray(OldCap, OldOperands);
771 // Copy Op into place. It still needs to be inserted into the MRI use lists.
772 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
773 NewMO->ParentMI = this;
775 // When adding a register operand, tell MRI about it.
776 if (NewMO->isReg()) {
777 // Ensure isOnRegUseList() returns false, regardless of Op's status.
778 NewMO->Contents.Reg.Prev = nullptr;
779 // Ignore existing ties. This is not a property that can be copied.
781 // Add the new operand to MRI, but only for instructions in an MBB.
783 MRI->addRegOperandToUseList(NewMO);
784 // The MCID operand information isn't accurate until we start adding
785 // explicit operands. The implicit operands are added first, then the
786 // explicits are inserted before them.
788 // Tie uses to defs as indicated in MCInstrDesc.
789 if (NewMO->isUse()) {
790 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
792 tieOperands(DefIdx, OpNo);
794 // If the register operand is flagged as early, mark the operand as such.
795 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
796 NewMO->setIsEarlyClobber(true);
801 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
802 /// fewer operand than it started with.
804 void MachineInstr::RemoveOperand(unsigned OpNo) {
805 assert(OpNo < getNumOperands() && "Invalid operand number");
806 untieRegOperand(OpNo);
809 // Moving tied operands would break the ties.
810 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
811 if (Operands[i].isReg())
812 assert(!Operands[i].isTied() && "Cannot move tied operands");
815 MachineRegisterInfo *MRI = getRegInfo();
816 if (MRI && Operands[OpNo].isReg())
817 MRI->removeRegOperandFromUseList(Operands + OpNo);
819 // Don't call the MachineOperand destructor. A lot of this code depends on
820 // MachineOperand having a trivial destructor anyway, and adding a call here
821 // wouldn't make it 'destructor-correct'.
823 if (unsigned N = NumOperands - 1 - OpNo)
824 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
828 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
829 /// This function should be used only occasionally. The setMemRefs function
830 /// is the primary method for setting up a MachineInstr's MemRefs list.
831 void MachineInstr::addMemOperand(MachineFunction &MF,
832 MachineMemOperand *MO) {
833 mmo_iterator OldMemRefs = MemRefs;
834 unsigned OldNumMemRefs = NumMemRefs;
836 unsigned NewNum = NumMemRefs + 1;
837 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
839 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
840 NewMemRefs[NewNum - 1] = MO;
841 setMemRefs(NewMemRefs, NewMemRefs + NewNum);
844 bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
845 assert(!isBundledWithPred() && "Must be called on bundle header");
846 for (MachineBasicBlock::const_instr_iterator MII = this;; ++MII) {
847 if (MII->getDesc().getFlags() & Mask) {
848 if (Type == AnyInBundle)
851 if (Type == AllInBundle && !MII->isBundle())
854 // This was the last instruction in the bundle.
855 if (!MII->isBundledWithSucc())
856 return Type == AllInBundle;
860 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
861 MICheckType Check) const {
862 // If opcodes or number of operands are not the same then the two
863 // instructions are obviously not identical.
864 if (Other->getOpcode() != getOpcode() ||
865 Other->getNumOperands() != getNumOperands())
869 // Both instructions are bundles, compare MIs inside the bundle.
870 MachineBasicBlock::const_instr_iterator I1 = *this;
871 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
872 MachineBasicBlock::const_instr_iterator I2 = *Other;
873 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
874 while (++I1 != E1 && I1->isInsideBundle()) {
876 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
881 // Check operands to make sure they match.
882 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
883 const MachineOperand &MO = getOperand(i);
884 const MachineOperand &OMO = Other->getOperand(i);
886 if (!MO.isIdenticalTo(OMO))
891 // Clients may or may not want to ignore defs when testing for equality.
892 // For example, machine CSE pass only cares about finding common
893 // subexpressions, so it's safe to ignore virtual register defs.
895 if (Check == IgnoreDefs)
897 else if (Check == IgnoreVRegDefs) {
898 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
899 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
900 if (MO.getReg() != OMO.getReg())
903 if (!MO.isIdenticalTo(OMO))
905 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
909 if (!MO.isIdenticalTo(OMO))
911 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
915 // If DebugLoc does not match then two dbg.values are not identical.
917 if (getDebugLoc() && Other->getDebugLoc() &&
918 getDebugLoc() != Other->getDebugLoc())
923 MachineInstr *MachineInstr::removeFromParent() {
924 assert(getParent() && "Not embedded in a basic block!");
925 return getParent()->remove(this);
928 MachineInstr *MachineInstr::removeFromBundle() {
929 assert(getParent() && "Not embedded in a basic block!");
930 return getParent()->remove_instr(this);
933 void MachineInstr::eraseFromParent() {
934 assert(getParent() && "Not embedded in a basic block!");
935 getParent()->erase(this);
938 void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
939 assert(getParent() && "Not embedded in a basic block!");
940 MachineBasicBlock *MBB = getParent();
941 MachineFunction *MF = MBB->getParent();
942 assert(MF && "Not embedded in a function!");
944 MachineInstr *MI = (MachineInstr *)this;
945 MachineRegisterInfo &MRI = MF->getRegInfo();
947 for (const MachineOperand &MO : MI->operands()) {
948 if (!MO.isReg() || !MO.isDef())
950 unsigned Reg = MO.getReg();
951 if (!TargetRegisterInfo::isVirtualRegister(Reg))
953 MRI.markUsesInDebugValueAsUndef(Reg);
955 MI->eraseFromParent();
958 void MachineInstr::eraseFromBundle() {
959 assert(getParent() && "Not embedded in a basic block!");
960 getParent()->erase_instr(this);
963 /// getNumExplicitOperands - Returns the number of non-implicit operands.
965 unsigned MachineInstr::getNumExplicitOperands() const {
966 unsigned NumOperands = MCID->getNumOperands();
967 if (!MCID->isVariadic())
970 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
971 const MachineOperand &MO = getOperand(i);
972 if (!MO.isReg() || !MO.isImplicit())
978 void MachineInstr::bundleWithPred() {
979 assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
980 setFlag(BundledPred);
981 MachineBasicBlock::instr_iterator Pred = this;
983 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
984 Pred->setFlag(BundledSucc);
987 void MachineInstr::bundleWithSucc() {
988 assert(!isBundledWithSucc() && "MI is already bundled with its successor");
989 setFlag(BundledSucc);
990 MachineBasicBlock::instr_iterator Succ = this;
992 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
993 Succ->setFlag(BundledPred);
996 void MachineInstr::unbundleFromPred() {
997 assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
998 clearFlag(BundledPred);
999 MachineBasicBlock::instr_iterator Pred = this;
1001 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
1002 Pred->clearFlag(BundledSucc);
1005 void MachineInstr::unbundleFromSucc() {
1006 assert(isBundledWithSucc() && "MI isn't bundled with its successor");
1007 clearFlag(BundledSucc);
1008 MachineBasicBlock::instr_iterator Succ = this;
1010 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
1011 Succ->clearFlag(BundledPred);
1014 bool MachineInstr::isStackAligningInlineAsm() const {
1015 if (isInlineAsm()) {
1016 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1017 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1023 InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
1024 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
1025 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1026 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
1029 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
1030 unsigned *GroupNo) const {
1031 assert(isInlineAsm() && "Expected an inline asm instruction");
1032 assert(OpIdx < getNumOperands() && "OpIdx out of range");
1034 // Ignore queries about the initial operands.
1035 if (OpIdx < InlineAsm::MIOp_FirstOperand)
1040 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1042 const MachineOperand &FlagMO = getOperand(i);
1043 // If we reach the implicit register operands, stop looking.
1044 if (!FlagMO.isImm())
1046 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1047 if (i + NumOps > OpIdx) {
1057 const TargetRegisterClass*
1058 MachineInstr::getRegClassConstraint(unsigned OpIdx,
1059 const TargetInstrInfo *TII,
1060 const TargetRegisterInfo *TRI) const {
1061 assert(getParent() && "Can't have an MBB reference here!");
1062 assert(getParent()->getParent() && "Can't have an MF reference here!");
1063 const MachineFunction &MF = *getParent()->getParent();
1065 // Most opcodes have fixed constraints in their MCInstrDesc.
1067 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
1069 if (!getOperand(OpIdx).isReg())
1072 // For tied uses on inline asm, get the constraint from the def.
1074 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
1077 // Inline asm stores register class constraints in the flag word.
1078 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
1082 unsigned Flag = getOperand(FlagIdx).getImm();
1084 if (InlineAsm::hasRegClassConstraint(Flag, RCID))
1085 return TRI->getRegClass(RCID);
1087 // Assume that all registers in a memory operand are pointers.
1088 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
1089 return TRI->getPointerRegClass(MF);
1094 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
1095 unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
1096 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
1097 // Check every operands inside the bundle if we have
1100 for (ConstMIBundleOperands OpndIt(this); OpndIt.isValid() && CurRC;
1102 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
1103 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
1105 // Otherwise, just check the current operands.
1106 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
1107 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
1111 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
1112 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1113 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
1114 assert(CurRC && "Invalid initial register class");
1115 // Check if Reg is constrained by some of its use/def from MI.
1116 const MachineOperand &MO = getOperand(OpIdx);
1117 if (!MO.isReg() || MO.getReg() != Reg)
1119 // If yes, accumulate the constraints through the operand.
1120 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
1123 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
1124 unsigned OpIdx, const TargetRegisterClass *CurRC,
1125 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
1126 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
1127 const MachineOperand &MO = getOperand(OpIdx);
1128 assert(MO.isReg() &&
1129 "Cannot get register constraints for non-register operand");
1130 assert(CurRC && "Invalid initial register class");
1131 if (unsigned SubIdx = MO.getSubReg()) {
1133 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
1135 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
1137 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
1141 /// Return the number of instructions inside the MI bundle, not counting the
1142 /// header instruction.
1143 unsigned MachineInstr::getBundleSize() const {
1144 MachineBasicBlock::const_instr_iterator I = this;
1146 while (I->isBundledWithSucc())
1151 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1152 /// the specific register or -1 if it is not found. It further tightens
1153 /// the search criteria to a use that kills the register if isKill is true.
1154 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
1155 const TargetRegisterInfo *TRI) const {
1156 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1157 const MachineOperand &MO = getOperand(i);
1158 if (!MO.isReg() || !MO.isUse())
1160 unsigned MOReg = MO.getReg();
1165 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1166 TargetRegisterInfo::isPhysicalRegister(Reg) &&
1167 TRI->isSubRegister(MOReg, Reg)))
1168 if (!isKill || MO.isKill())
1174 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1175 /// indicating if this instruction reads or writes Reg. This also considers
1176 /// partial defines.
1177 std::pair<bool,bool>
1178 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1179 SmallVectorImpl<unsigned> *Ops) const {
1180 bool PartDef = false; // Partial redefine.
1181 bool FullDef = false; // Full define.
1184 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1185 const MachineOperand &MO = getOperand(i);
1186 if (!MO.isReg() || MO.getReg() != Reg)
1191 Use |= !MO.isUndef();
1192 else if (MO.getSubReg() && !MO.isUndef())
1193 // A partial <def,undef> doesn't count as reading the register.
1198 // A partial redefine uses Reg unless there is also a full define.
1199 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1202 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1203 /// the specified register or -1 if it is not found. If isDead is true, defs
1204 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1205 /// also checks if there is a def of a super-register.
1207 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1208 const TargetRegisterInfo *TRI) const {
1209 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1210 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1211 const MachineOperand &MO = getOperand(i);
1212 // Accept regmask operands when Overlap is set.
1213 // Ignore them when looking for a specific def operand (Overlap == false).
1214 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1216 if (!MO.isReg() || !MO.isDef())
1218 unsigned MOReg = MO.getReg();
1219 bool Found = (MOReg == Reg);
1220 if (!Found && TRI && isPhys &&
1221 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1223 Found = TRI->regsOverlap(MOReg, Reg);
1225 Found = TRI->isSubRegister(MOReg, Reg);
1227 if (Found && (!isDead || MO.isDead()))
1233 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1234 /// operand list that is used to represent the predicate. It returns -1 if
1236 int MachineInstr::findFirstPredOperandIdx() const {
1237 // Don't call MCID.findFirstPredOperandIdx() because this variant
1238 // is sometimes called on an instruction that's not yet complete, and
1239 // so the number of operands is less than the MCID indicates. In
1240 // particular, the PTX target does this.
1241 const MCInstrDesc &MCID = getDesc();
1242 if (MCID.isPredicable()) {
1243 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1244 if (MCID.OpInfo[i].isPredicate())
1251 // MachineOperand::TiedTo is 4 bits wide.
1252 const unsigned TiedMax = 15;
1254 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1256 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1257 /// field. TiedTo can have these values:
1259 /// 0: Operand is not tied to anything.
1260 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1261 /// TiedMax: Tied to an operand >= TiedMax-1.
1263 /// The tied def must be one of the first TiedMax operands on a normal
1264 /// instruction. INLINEASM instructions allow more tied defs.
1266 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1267 MachineOperand &DefMO = getOperand(DefIdx);
1268 MachineOperand &UseMO = getOperand(UseIdx);
1269 assert(DefMO.isDef() && "DefIdx must be a def operand");
1270 assert(UseMO.isUse() && "UseIdx must be a use operand");
1271 assert(!DefMO.isTied() && "Def is already tied to another use");
1272 assert(!UseMO.isTied() && "Use is already tied to another def");
1274 if (DefIdx < TiedMax)
1275 UseMO.TiedTo = DefIdx + 1;
1277 // Inline asm can use the group descriptors to find tied operands, but on
1278 // normal instruction, the tied def must be within the first TiedMax
1280 assert(isInlineAsm() && "DefIdx out of range");
1281 UseMO.TiedTo = TiedMax;
1284 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1285 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1288 /// Given the index of a tied register operand, find the operand it is tied to.
1289 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1290 /// which must exist.
1291 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1292 const MachineOperand &MO = getOperand(OpIdx);
1293 assert(MO.isTied() && "Operand isn't tied");
1295 // Normally TiedTo is in range.
1296 if (MO.TiedTo < TiedMax)
1297 return MO.TiedTo - 1;
1299 // Uses on normal instructions can be out of range.
1300 if (!isInlineAsm()) {
1301 // Normal tied defs must be in the 0..TiedMax-1 range.
1304 // MO is a def. Search for the tied use.
1305 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1306 const MachineOperand &UseMO = getOperand(i);
1307 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1310 llvm_unreachable("Can't find tied use");
1313 // Now deal with inline asm by parsing the operand group descriptor flags.
1314 // Find the beginning of each operand group.
1315 SmallVector<unsigned, 8> GroupIdx;
1316 unsigned OpIdxGroup = ~0u;
1318 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1320 const MachineOperand &FlagMO = getOperand(i);
1321 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1322 unsigned CurGroup = GroupIdx.size();
1323 GroupIdx.push_back(i);
1324 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1325 // OpIdx belongs to this operand group.
1326 if (OpIdx > i && OpIdx < i + NumOps)
1327 OpIdxGroup = CurGroup;
1329 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1331 // Operands in this group are tied to operands in TiedGroup which must be
1332 // earlier. Find the number of operands between the two groups.
1333 unsigned Delta = i - GroupIdx[TiedGroup];
1335 // OpIdx is a use tied to TiedGroup.
1336 if (OpIdxGroup == CurGroup)
1337 return OpIdx - Delta;
1339 // OpIdx is a def tied to this use group.
1340 if (OpIdxGroup == TiedGroup)
1341 return OpIdx + Delta;
1343 llvm_unreachable("Invalid tied operand on inline asm");
1346 /// clearKillInfo - Clears kill flags on all operands.
1348 void MachineInstr::clearKillInfo() {
1349 for (MachineOperand &MO : operands()) {
1350 if (MO.isReg() && MO.isUse())
1351 MO.setIsKill(false);
1355 void MachineInstr::substituteRegister(unsigned FromReg,
1358 const TargetRegisterInfo &RegInfo) {
1359 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1361 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1362 for (MachineOperand &MO : operands()) {
1363 if (!MO.isReg() || MO.getReg() != FromReg)
1365 MO.substPhysReg(ToReg, RegInfo);
1368 for (MachineOperand &MO : operands()) {
1369 if (!MO.isReg() || MO.getReg() != FromReg)
1371 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1376 /// isSafeToMove - Return true if it is safe to move this instruction. If
1377 /// SawStore is set to true, it means that there is a store (or call) between
1378 /// the instruction's location and its intended destination.
1379 bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
1380 // Ignore stuff that we obviously can't move.
1382 // Treat volatile loads as stores. This is not strictly necessary for
1383 // volatiles, but it is required for atomic loads. It is not allowed to move
1384 // a load across an atomic load with Ordering > Monotonic.
1385 if (mayStore() || isCall() ||
1386 (mayLoad() && hasOrderedMemoryRef())) {
1391 if (isPosition() || isDebugValue() || isTerminator() ||
1392 hasUnmodeledSideEffects())
1395 // See if this instruction does a load. If so, we have to guarantee that the
1396 // loaded value doesn't change between the load and the its intended
1397 // destination. The check for isInvariantLoad gives the targe the chance to
1398 // classify the load as always returning a constant, e.g. a constant pool
1400 if (mayLoad() && !isInvariantLoad(AA))
1401 // Otherwise, this is a real load. If there is a store between the load and
1402 // end of block, we can't move it.
1408 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1409 /// or volatile memory reference, or if the information describing the memory
1410 /// reference is not available. Return false if it is known to have no ordered
1411 /// memory references.
1412 bool MachineInstr::hasOrderedMemoryRef() const {
1413 // An instruction known never to access memory won't have a volatile access.
1417 !hasUnmodeledSideEffects())
1420 // Otherwise, if the instruction has no memory reference information,
1421 // conservatively assume it wasn't preserved.
1422 if (memoperands_empty())
1425 // Check the memory reference information for ordered references.
1426 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1427 if (!(*I)->isUnordered())
1433 /// isInvariantLoad - Return true if this instruction is loading from a
1434 /// location whose value is invariant across the function. For example,
1435 /// loading a value from the constant pool or from the argument area
1436 /// of a function if it does not change. This should only return true of
1437 /// *all* loads the instruction does are invariant (if it does multiple loads).
1438 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1439 // If the instruction doesn't load at all, it isn't an invariant load.
1443 // If the instruction has lost its memoperands, conservatively assume that
1444 // it may not be an invariant load.
1445 if (memoperands_empty())
1448 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1450 for (mmo_iterator I = memoperands_begin(),
1451 E = memoperands_end(); I != E; ++I) {
1452 if ((*I)->isVolatile()) return false;
1453 if ((*I)->isStore()) return false;
1454 if ((*I)->isInvariant()) return true;
1457 // A load from a constant PseudoSourceValue is invariant.
1458 if (const PseudoSourceValue *PSV = (*I)->getPseudoValue())
1459 if (PSV->isConstant(MFI))
1462 if (const Value *V = (*I)->getValue()) {
1463 // If we have an AliasAnalysis, ask it whether the memory is constant.
1465 AA->pointsToConstantMemory(
1466 MemoryLocation(V, (*I)->getSize(), (*I)->getAAInfo())))
1470 // Otherwise assume conservatively.
1474 // Everything checks out.
1478 /// isConstantValuePHI - If the specified instruction is a PHI that always
1479 /// merges together the same virtual register, return the register, otherwise
1481 unsigned MachineInstr::isConstantValuePHI() const {
1484 assert(getNumOperands() >= 3 &&
1485 "It's illegal to have a PHI without source operands");
1487 unsigned Reg = getOperand(1).getReg();
1488 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1489 if (getOperand(i).getReg() != Reg)
1494 bool MachineInstr::hasUnmodeledSideEffects() const {
1495 if (hasProperty(MCID::UnmodeledSideEffects))
1497 if (isInlineAsm()) {
1498 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1499 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1506 bool MachineInstr::isLoadFoldBarrier() const {
1507 return mayStore() || isCall() || hasUnmodeledSideEffects();
1510 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1512 bool MachineInstr::allDefsAreDead() const {
1513 for (const MachineOperand &MO : operands()) {
1514 if (!MO.isReg() || MO.isUse())
1522 /// copyImplicitOps - Copy implicit register operands from specified
1523 /// instruction to this instruction.
1524 void MachineInstr::copyImplicitOps(MachineFunction &MF,
1525 const MachineInstr *MI) {
1526 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1528 const MachineOperand &MO = MI->getOperand(i);
1529 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1534 void MachineInstr::dump() const {
1535 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1536 dbgs() << " " << *this;
1540 void MachineInstr::print(raw_ostream &OS, bool SkipOpers) const {
1541 const Module *M = nullptr;
1542 if (const MachineBasicBlock *MBB = getParent())
1543 if (const MachineFunction *MF = MBB->getParent())
1544 M = MF->getFunction()->getParent();
1546 ModuleSlotTracker MST(M);
1547 print(OS, MST, SkipOpers);
1550 void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1551 bool SkipOpers) const {
1552 // We can be a bit tidier if we know the MachineFunction.
1553 const MachineFunction *MF = nullptr;
1554 const TargetRegisterInfo *TRI = nullptr;
1555 const MachineRegisterInfo *MRI = nullptr;
1556 const TargetInstrInfo *TII = nullptr;
1557 if (const MachineBasicBlock *MBB = getParent()) {
1558 MF = MBB->getParent();
1560 MRI = &MF->getRegInfo();
1561 TRI = MF->getSubtarget().getRegisterInfo();
1562 TII = MF->getSubtarget().getInstrInfo();
1566 // Save a list of virtual registers.
1567 SmallVector<unsigned, 8> VirtRegs;
1569 // Print explicitly defined operands on the left of an assignment syntax.
1570 unsigned StartOp = 0, e = getNumOperands();
1571 for (; StartOp < e && getOperand(StartOp).isReg() &&
1572 getOperand(StartOp).isDef() &&
1573 !getOperand(StartOp).isImplicit();
1575 if (StartOp != 0) OS << ", ";
1576 getOperand(StartOp).print(OS, MST, TRI);
1577 unsigned Reg = getOperand(StartOp).getReg();
1578 if (TargetRegisterInfo::isVirtualRegister(Reg))
1579 VirtRegs.push_back(Reg);
1585 // Print the opcode name.
1587 OS << TII->getName(getOpcode());
1594 // Print the rest of the operands.
1595 bool OmittedAnyCallClobbers = false;
1596 bool FirstOp = true;
1597 unsigned AsmDescOp = ~0u;
1598 unsigned AsmOpCount = 0;
1600 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1601 // Print asm string.
1603 getOperand(InlineAsm::MIOp_AsmString).print(OS, MST, TRI);
1605 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1606 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1607 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1608 OS << " [sideeffect]";
1609 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1611 if (ExtraInfo & InlineAsm::Extra_MayStore)
1612 OS << " [maystore]";
1613 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1614 OS << " [alignstack]";
1615 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1616 OS << " [attdialect]";
1617 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1618 OS << " [inteldialect]";
1620 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1625 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1626 const MachineOperand &MO = getOperand(i);
1628 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1629 VirtRegs.push_back(MO.getReg());
1631 // Omit call-clobbered registers which aren't used anywhere. This makes
1632 // call instructions much less noisy on targets where calls clobber lots
1633 // of registers. Don't rely on MO.isDead() because we may be called before
1634 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1635 if (MRI && isCall() &&
1636 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1637 unsigned Reg = MO.getReg();
1638 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1639 if (MRI->use_empty(Reg)) {
1640 bool HasAliasLive = false;
1641 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
1642 unsigned AliasReg = *AI;
1643 if (!MRI->use_empty(AliasReg)) {
1644 HasAliasLive = true;
1648 if (!HasAliasLive) {
1649 OmittedAnyCallClobbers = true;
1656 if (FirstOp) FirstOp = false; else OS << ",";
1658 if (i < getDesc().NumOperands) {
1659 const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1660 if (MCOI.isPredicate())
1662 if (MCOI.isOptionalDef())
1665 if (isDebugValue() && MO.isMetadata()) {
1666 // Pretty print DBG_VALUE instructions.
1667 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1668 if (DIV && !DIV->getName().empty())
1669 OS << "!\"" << DIV->getName() << '\"';
1671 MO.print(OS, MST, TRI);
1672 } else if (TRI && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1673 OS << TRI->getSubRegIndexName(MO.getImm());
1674 } else if (i == AsmDescOp && MO.isImm()) {
1675 // Pretty print the inline asm operand descriptor.
1676 OS << '$' << AsmOpCount++;
1677 unsigned Flag = MO.getImm();
1678 switch (InlineAsm::getKind(Flag)) {
1679 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1680 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1681 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1682 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1683 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1684 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1685 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1689 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1691 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1693 OS << ":RC" << RCID;
1696 unsigned TiedTo = 0;
1697 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1698 OS << " tiedto:$" << TiedTo;
1702 // Compute the index of the next operand descriptor.
1703 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1705 MO.print(OS, MST, TRI);
1708 // Briefly indicate whether any call clobbers were omitted.
1709 if (OmittedAnyCallClobbers) {
1710 if (!FirstOp) OS << ",";
1714 bool HaveSemi = false;
1715 const unsigned PrintableFlags = FrameSetup;
1716 if (Flags & PrintableFlags) {
1717 if (!HaveSemi) OS << ";"; HaveSemi = true;
1720 if (Flags & FrameSetup)
1724 if (!memoperands_empty()) {
1725 if (!HaveSemi) OS << ";"; HaveSemi = true;
1728 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1730 (*i)->print(OS, MST);
1731 if (std::next(i) != e)
1736 // Print the regclass of any virtual registers encountered.
1737 if (MRI && !VirtRegs.empty()) {
1738 if (!HaveSemi) OS << ";"; HaveSemi = true;
1739 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1740 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1741 OS << " " << TRI->getRegClassName(RC)
1742 << ':' << PrintReg(VirtRegs[i]);
1743 for (unsigned j = i+1; j != VirtRegs.size();) {
1744 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1748 if (VirtRegs[i] != VirtRegs[j])
1749 OS << "," << PrintReg(VirtRegs[j]);
1750 VirtRegs.erase(VirtRegs.begin()+j);
1755 // Print debug location information.
1756 if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1757 if (!HaveSemi) OS << ";";
1758 auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1759 OS << " line no:" << DV->getLine();
1760 if (auto *InlinedAt = debugLoc->getInlinedAt()) {
1761 DebugLoc InlinedAtDL(InlinedAt);
1762 if (InlinedAtDL && MF) {
1763 OS << " inlined @[ ";
1764 InlinedAtDL.print(OS);
1768 if (isIndirectDebugValue())
1770 } else if (debugLoc && MF) {
1771 if (!HaveSemi) OS << ";";
1779 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1780 const TargetRegisterInfo *RegInfo,
1781 bool AddIfNotFound) {
1782 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1783 bool hasAliases = isPhysReg &&
1784 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1786 SmallVector<unsigned,4> DeadOps;
1787 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1788 MachineOperand &MO = getOperand(i);
1789 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1791 unsigned Reg = MO.getReg();
1795 if (Reg == IncomingReg) {
1798 // The register is already marked kill.
1800 if (isPhysReg && isRegTiedToDefOperand(i))
1801 // Two-address uses of physregs must not be marked kill.
1806 } else if (hasAliases && MO.isKill() &&
1807 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1808 // A super-register kill already exists.
1809 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1811 if (RegInfo->isSubRegister(IncomingReg, Reg))
1812 DeadOps.push_back(i);
1816 // Trim unneeded kill operands.
1817 while (!DeadOps.empty()) {
1818 unsigned OpIdx = DeadOps.back();
1819 if (getOperand(OpIdx).isImplicit())
1820 RemoveOperand(OpIdx);
1822 getOperand(OpIdx).setIsKill(false);
1826 // If not found, this means an alias of one of the operands is killed. Add a
1827 // new implicit operand if required.
1828 if (!Found && AddIfNotFound) {
1829 addOperand(MachineOperand::CreateReg(IncomingReg,
1838 void MachineInstr::clearRegisterKills(unsigned Reg,
1839 const TargetRegisterInfo *RegInfo) {
1840 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1842 for (MachineOperand &MO : operands()) {
1843 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1845 unsigned OpReg = MO.getReg();
1846 if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1847 MO.setIsKill(false);
1851 bool MachineInstr::addRegisterDead(unsigned Reg,
1852 const TargetRegisterInfo *RegInfo,
1853 bool AddIfNotFound) {
1854 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
1855 bool hasAliases = isPhysReg &&
1856 MCRegAliasIterator(Reg, RegInfo, false).isValid();
1858 SmallVector<unsigned,4> DeadOps;
1859 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1860 MachineOperand &MO = getOperand(i);
1861 if (!MO.isReg() || !MO.isDef())
1863 unsigned MOReg = MO.getReg();
1870 } else if (hasAliases && MO.isDead() &&
1871 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1872 // There exists a super-register that's marked dead.
1873 if (RegInfo->isSuperRegister(Reg, MOReg))
1875 if (RegInfo->isSubRegister(Reg, MOReg))
1876 DeadOps.push_back(i);
1880 // Trim unneeded dead operands.
1881 while (!DeadOps.empty()) {
1882 unsigned OpIdx = DeadOps.back();
1883 if (getOperand(OpIdx).isImplicit())
1884 RemoveOperand(OpIdx);
1886 getOperand(OpIdx).setIsDead(false);
1890 // If not found, this means an alias of one of the operands is dead. Add a
1891 // new implicit operand if required.
1892 if (Found || !AddIfNotFound)
1895 addOperand(MachineOperand::CreateReg(Reg,
1903 void MachineInstr::clearRegisterDeads(unsigned Reg) {
1904 for (MachineOperand &MO : operands()) {
1905 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1907 MO.setIsDead(false);
1911 void MachineInstr::addRegisterDefReadUndef(unsigned Reg) {
1912 for (MachineOperand &MO : operands()) {
1913 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1919 void MachineInstr::addRegisterDefined(unsigned Reg,
1920 const TargetRegisterInfo *RegInfo) {
1921 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1922 MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
1926 for (const MachineOperand &MO : operands()) {
1927 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1928 MO.getSubReg() == 0)
1932 addOperand(MachineOperand::CreateReg(Reg,
1937 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1938 const TargetRegisterInfo &TRI) {
1939 bool HasRegMask = false;
1940 for (MachineOperand &MO : operands()) {
1941 if (MO.isRegMask()) {
1945 if (!MO.isReg() || !MO.isDef()) continue;
1946 unsigned Reg = MO.getReg();
1947 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1948 // If there are no uses, including partial uses, the def is dead.
1949 if (std::none_of(UsedRegs.begin(), UsedRegs.end(),
1950 [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
1954 // This is a call with a register mask operand.
1955 // Mask clobbers are always dead, so add defs for the non-dead defines.
1957 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1959 addRegisterDefined(*I, &TRI);
1963 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1964 // Build up a buffer of hash code components.
1965 SmallVector<size_t, 8> HashComponents;
1966 HashComponents.reserve(MI->getNumOperands() + 1);
1967 HashComponents.push_back(MI->getOpcode());
1968 for (const MachineOperand &MO : MI->operands()) {
1969 if (MO.isReg() && MO.isDef() &&
1970 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1971 continue; // Skip virtual register defs.
1973 HashComponents.push_back(hash_value(MO));
1975 return hash_combine_range(HashComponents.begin(), HashComponents.end());
1978 void MachineInstr::emitError(StringRef Msg) const {
1979 // Find the source location cookie.
1980 unsigned LocCookie = 0;
1981 const MDNode *LocMD = nullptr;
1982 for (unsigned i = getNumOperands(); i != 0; --i) {
1983 if (getOperand(i-1).isMetadata() &&
1984 (LocMD = getOperand(i-1).getMetadata()) &&
1985 LocMD->getNumOperands() != 0) {
1986 if (const ConstantInt *CI =
1987 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
1988 LocCookie = CI->getZExtValue();
1994 if (const MachineBasicBlock *MBB = getParent())
1995 if (const MachineFunction *MF = MBB->getParent())
1996 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1997 report_fatal_error(Msg);