2 //***************************************************************************
12 // 7/2/01 - Vikram Adve - Created
13 //**************************************************************************/
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/ConstPoolVals.h"
17 #include "llvm/Instruction.h"
20 //************************ Class Implementations **************************/
22 // Constructor for instructions with fixed #operands (nearly all)
23 MachineInstr::MachineInstr(MachineOpCode _opCode,
24 OpCodeMask _opCodeMask)
26 opCodeMask(_opCodeMask),
27 operands(TargetInstrDescriptors[_opCode].numOperands)
29 assert(TargetInstrDescriptors[_opCode].numOperands >= 0);
32 // Constructor for instructions with variable #operands
33 MachineInstr::MachineInstr(MachineOpCode _opCode,
35 OpCodeMask _opCodeMask)
37 opCodeMask(_opCodeMask),
43 MachineInstr::SetMachineOperand(unsigned int i,
44 MachineOperand::MachineOperandType operandType,
45 Value* _val, bool isdef=false)
47 assert(i < operands.size());
48 operands[i].Initialize(operandType, _val);
49 operands[i].isDef = isdef;
53 MachineInstr::SetMachineOperand(unsigned int i,
54 MachineOperand::MachineOperandType operandType,
55 int64_t intValue, bool isdef=false)
57 assert(i < operands.size());
58 operands[i].InitializeConst(operandType, intValue);
59 operands[i].isDef = isdef;
63 MachineInstr::SetMachineOperand(unsigned int i,
64 unsigned int regNum, bool isdef=false)
66 assert(i < operands.size());
67 operands[i].InitializeReg(regNum);
68 operands[i].isDef = isdef;
72 MachineInstr::dump(unsigned int indent)
74 for (unsigned i=0; i < indent; i++)
81 operator<< (ostream& os, const MachineInstr& minstr)
83 os << TargetInstrDescriptors[minstr.opCode].opCodeString;
85 for (unsigned i=0, N=minstr.getNumOperands(); i < N; i++)
86 os << "\t" << minstr.getOperand(i);
88 #undef DEBUG_VAL_OP_ITERATOR
89 #ifdef DEBUG_VAL_OP_ITERATOR
90 os << endl << "\tValue operands are: ";
91 for (MachineInstr::val_op_const_iterator vo(&minstr); ! vo.done(); ++vo)
93 const Value* val = *vo;
94 os << val << (vo.isDef()? "(def), " : ", ");
103 operator<< (ostream& os, const MachineOperand& mop)
106 if (mop.opType == MachineOperand::MO_VirtualRegister)
107 regInfo << "(val " << mop.value << ")" << ends;
108 else if (mop.opType == MachineOperand::MO_MachineRegister)
109 regInfo << "(" << mop.regNum << ")" << ends;
110 else if (mop.opType == MachineOperand::MO_CCRegister)
111 regInfo << "(val " << mop.value << ")" << ends;
115 case MachineOperand::MO_VirtualRegister:
116 case MachineOperand::MO_MachineRegister:
117 os << "%reg" << regInfo.str();
121 case MachineOperand::MO_CCRegister:
122 os << "%ccreg" << regInfo.str();
126 case MachineOperand::MO_SignExtendedImmed:
130 case MachineOperand::MO_UnextendedImmed:
134 case MachineOperand::MO_PCRelativeDisp:
135 os << "%disp(label " << mop.value << ")";
139 assert(0 && "Unrecognized operand type");
147 //---------------------------------------------------------------------------
148 // Target-independent utility routines for creating machine instructions
149 //---------------------------------------------------------------------------
152 //------------------------------------------------------------------------
153 // Function Set2OperandsFromInstr
154 // Function Set3OperandsFromInstr
156 // For the common case of 2- and 3-operand arithmetic/logical instructions,
157 // set the m/c instr. operands directly from the VM instruction's operands.
158 // Check whether the first or second operand is 0 and can use a dedicated "0" register.
159 // Check whether the second operand should use an immediate field or register.
160 // (First and third operands are never immediates for such instructions.)
163 // canDiscardResult: Specifies that the result operand can be discarded
164 // by using the dedicated "0"
166 // op1position, op2position and resultPosition: Specify in which position
167 // in the machine instruction the 3 operands (arg1, arg2
168 // and result) should go.
170 // RETURN VALUE: unsigned int flags, where
171 // flags & 0x01 => operand 1 is constant and needs a register
172 // flags & 0x02 => operand 2 is constant and needs a register
173 //------------------------------------------------------------------------
176 Set2OperandsFromInstr(MachineInstr* minstr,
177 InstructionNode* vmInstrNode,
178 const TargetMachine& target,
179 bool canDiscardResult,
183 Set3OperandsFromInstr(minstr, vmInstrNode, target,
184 canDiscardResult, op1Position,
185 /*op2Position*/ -1, resultPosition);
188 #undef REVERT_TO_EXPLICIT_CONSTANT_CHECKS
189 #ifdef REVERT_TO_EXPLICIT_CONSTANT_CHECKS
191 Set3OperandsFromInstrJUNK(MachineInstr* minstr,
192 InstructionNode* vmInstrNode,
193 const TargetMachine& target,
194 bool canDiscardResult,
199 assert(op1Position >= 0);
200 assert(resultPosition >= 0);
202 unsigned returnFlags = 0x0;
204 // Check if operand 1 is 0 and if so, try to use the register that gives 0, if any.
205 Value* op1Value = vmInstrNode->leftChild()->getValue();
206 bool isValidConstant;
207 int64_t intValue = GetConstantValueAsSignedInt(op1Value, isValidConstant);
208 if (isValidConstant && intValue == 0 && target.zeroRegNum >= 0)
209 minstr->SetMachineOperand(op1Position, /*regNum*/ target.zeroRegNum);
212 if (op1Value->getValueType() == Value::ConstantVal)
213 {// value is constant and must be loaded from constant pool
214 returnFlags = returnFlags | (1 << op1Position);
216 minstr->SetMachineOperand(op1Position,MachineOperand::MO_VirtualRegister,
220 // Check if operand 2 (if any) fits in the immediate field of the instruction,
221 // of if it is 0 and can use a dedicated machine register
222 if (op2Position >= 0)
224 Value* op2Value = vmInstrNode->rightChild()->getValue();
226 unsigned int machineRegNum;
228 MachineOperand::MachineOperandType
229 op2type = ChooseRegOrImmed(op2Value, minstr->getOpCode(), target,
230 /*canUseImmed*/ true,
231 machineRegNum, immedValue);
233 if (op2type == MachineOperand::MO_MachineRegister)
234 minstr->SetMachineOperand(op2Position, machineRegNum);
235 else if (op2type == MachineOperand::MO_VirtualRegister)
237 if (op2Value->getValueType() == Value::ConstantVal)
238 {// value is constant and must be loaded from constant pool
239 returnFlags = returnFlags | (1 << op2Position);
241 minstr->SetMachineOperand(op2Position, op2type, op2Value);
245 assert(op2type != MO_CCRegister);
246 minstr->SetMachineOperand(op2Position, op2type, immedValue);
250 // If operand 3 (result) can be discarded, use a dead register if one exists
251 if (canDiscardResult && target.zeroRegNum >= 0)
252 minstr->SetMachineOperand(resultPosition, target.zeroRegNum);
254 minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
262 Set3OperandsFromInstr(MachineInstr* minstr,
263 InstructionNode* vmInstrNode,
264 const TargetMachine& target,
265 bool canDiscardResult,
270 assert(op1Position >= 0);
271 assert(resultPosition >= 0);
274 minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister,
275 vmInstrNode->leftChild()->getValue());
277 // operand 2 (if any)
278 if (op2Position >= 0)
279 minstr->SetMachineOperand(op2Position, MachineOperand::MO_VirtualRegister,
280 vmInstrNode->rightChild()->getValue());
282 // result operand: if it can be discarded, use a dead register if one exists
283 if (canDiscardResult && target.zeroRegNum >= 0)
284 minstr->SetMachineOperand(resultPosition, target.zeroRegNum);
286 minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
290 MachineOperand::MachineOperandType
291 ChooseRegOrImmed(Value* val,
292 MachineOpCode opCode,
293 const TargetMachine& target,
295 unsigned int& getMachineRegNum,
296 int64_t& getImmedValue)
298 MachineOperand::MachineOperandType opType =
299 MachineOperand::MO_VirtualRegister;
300 getMachineRegNum = 0;
303 // Check for the common case first: argument is not constant
305 if (val->getValueType() != Value::ConstantVal)
308 // Now get the constant value and check if it fits in the IMMED field.
309 // Take advantage of the fact that the max unsigned value will rarely
310 // fit into any IMMED field and ignore that case (i.e., cast smaller
311 // unsigned constants to signed).
313 bool isValidConstant;
314 int64_t intValue = GetConstantValueAsSignedInt(val, isValidConstant);
318 if (intValue == 0 && target.zeroRegNum >= 0)
320 opType = MachineOperand::MO_MachineRegister;
321 getMachineRegNum = target.zeroRegNum;
323 else if (canUseImmed &&
324 target.getInstrInfo().constantFitsInImmedField(opCode,intValue))
326 opType = MachineOperand::MO_SignExtendedImmed;
327 getImmedValue = intValue;