1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/ADT/FoldingSet.h"
16 #include "llvm/ADT/Hashing.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/Assembly/Writer.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/DebugInfo.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/InlineAsm.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/IR/Metadata.h"
31 #include "llvm/IR/Module.h"
32 #include "llvm/IR/Type.h"
33 #include "llvm/IR/Value.h"
34 #include "llvm/MC/MCInstrDesc.h"
35 #include "llvm/MC/MCSymbol.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
45 //===----------------------------------------------------------------------===//
46 // MachineOperand Implementation
47 //===----------------------------------------------------------------------===//
49 void MachineOperand::setReg(unsigned Reg) {
50 if (getReg() == Reg) return; // No change.
52 // Otherwise, we have to change the register. If this operand is embedded
53 // into a machine function, we need to update the old and new register's
55 if (MachineInstr *MI = getParent())
56 if (MachineBasicBlock *MBB = MI->getParent())
57 if (MachineFunction *MF = MBB->getParent()) {
58 MachineRegisterInfo &MRI = MF->getRegInfo();
59 MRI.removeRegOperandFromUseList(this);
60 SmallContents.RegNo = Reg;
61 MRI.addRegOperandToUseList(this);
65 // Otherwise, just change the register, no problem. :)
66 SmallContents.RegNo = Reg;
69 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
70 const TargetRegisterInfo &TRI) {
71 assert(TargetRegisterInfo::isVirtualRegister(Reg));
72 if (SubIdx && getSubReg())
73 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
79 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
80 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
82 Reg = TRI.getSubReg(Reg, getSubReg());
83 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
84 // That won't happen in legal code.
90 /// Change a def to a use, or a use to a def.
91 void MachineOperand::setIsDef(bool Val) {
92 assert(isReg() && "Wrong MachineOperand accessor");
93 assert((!Val || !isDebug()) && "Marking a debug operation as def");
96 // MRI may keep uses and defs in different list positions.
97 if (MachineInstr *MI = getParent())
98 if (MachineBasicBlock *MBB = MI->getParent())
99 if (MachineFunction *MF = MBB->getParent()) {
100 MachineRegisterInfo &MRI = MF->getRegInfo();
101 MRI.removeRegOperandFromUseList(this);
103 MRI.addRegOperandToUseList(this);
109 /// ChangeToImmediate - Replace this operand with a new immediate operand of
110 /// the specified value. If an operand is known to be an immediate already,
111 /// the setImm method should be used.
112 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
113 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
114 // If this operand is currently a register operand, and if this is in a
115 // function, deregister the operand from the register's use/def list.
116 if (isReg() && isOnRegUseList())
117 if (MachineInstr *MI = getParent())
118 if (MachineBasicBlock *MBB = MI->getParent())
119 if (MachineFunction *MF = MBB->getParent())
120 MF->getRegInfo().removeRegOperandFromUseList(this);
122 OpKind = MO_Immediate;
123 Contents.ImmVal = ImmVal;
126 /// ChangeToRegister - Replace this operand with a new register operand of
127 /// the specified value. If an operand is known to be an register already,
128 /// the setReg method should be used.
129 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
130 bool isKill, bool isDead, bool isUndef,
132 MachineRegisterInfo *RegInfo = 0;
133 if (MachineInstr *MI = getParent())
134 if (MachineBasicBlock *MBB = MI->getParent())
135 if (MachineFunction *MF = MBB->getParent())
136 RegInfo = &MF->getRegInfo();
137 // If this operand is already a register operand, remove it from the
138 // register's use/def lists.
139 bool WasReg = isReg();
140 if (RegInfo && WasReg)
141 RegInfo->removeRegOperandFromUseList(this);
143 // Change this to a register and set the reg#.
144 OpKind = MO_Register;
145 SmallContents.RegNo = Reg;
146 SubReg_TargetFlags = 0;
152 IsInternalRead = false;
153 IsEarlyClobber = false;
155 // Ensure isOnRegUseList() returns false.
156 Contents.Reg.Prev = 0;
157 // Preserve the tie when the operand was already a register.
161 // If this operand is embedded in a function, add the operand to the
162 // register's use/def list.
164 RegInfo->addRegOperandToUseList(this);
167 /// isIdenticalTo - Return true if this operand is identical to the specified
168 /// operand. Note that this should stay in sync with the hash_value overload
170 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
171 if (getType() != Other.getType() ||
172 getTargetFlags() != Other.getTargetFlags())
176 case MachineOperand::MO_Register:
177 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
178 getSubReg() == Other.getSubReg();
179 case MachineOperand::MO_Immediate:
180 return getImm() == Other.getImm();
181 case MachineOperand::MO_CImmediate:
182 return getCImm() == Other.getCImm();
183 case MachineOperand::MO_FPImmediate:
184 return getFPImm() == Other.getFPImm();
185 case MachineOperand::MO_MachineBasicBlock:
186 return getMBB() == Other.getMBB();
187 case MachineOperand::MO_FrameIndex:
188 return getIndex() == Other.getIndex();
189 case MachineOperand::MO_ConstantPoolIndex:
190 case MachineOperand::MO_TargetIndex:
191 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
192 case MachineOperand::MO_JumpTableIndex:
193 return getIndex() == Other.getIndex();
194 case MachineOperand::MO_GlobalAddress:
195 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
196 case MachineOperand::MO_ExternalSymbol:
197 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
198 getOffset() == Other.getOffset();
199 case MachineOperand::MO_BlockAddress:
200 return getBlockAddress() == Other.getBlockAddress() &&
201 getOffset() == Other.getOffset();
202 case MO_RegisterMask:
203 return getRegMask() == Other.getRegMask();
204 case MachineOperand::MO_MCSymbol:
205 return getMCSymbol() == Other.getMCSymbol();
206 case MachineOperand::MO_Metadata:
207 return getMetadata() == Other.getMetadata();
209 llvm_unreachable("Invalid machine operand type");
212 // Note: this must stay exactly in sync with isIdenticalTo above.
213 hash_code llvm::hash_value(const MachineOperand &MO) {
214 switch (MO.getType()) {
215 case MachineOperand::MO_Register:
216 // Register operands don't have target flags.
217 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
218 case MachineOperand::MO_Immediate:
219 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
220 case MachineOperand::MO_CImmediate:
221 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
222 case MachineOperand::MO_FPImmediate:
223 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
224 case MachineOperand::MO_MachineBasicBlock:
225 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
226 case MachineOperand::MO_FrameIndex:
227 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
228 case MachineOperand::MO_ConstantPoolIndex:
229 case MachineOperand::MO_TargetIndex:
230 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
232 case MachineOperand::MO_JumpTableIndex:
233 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
234 case MachineOperand::MO_ExternalSymbol:
235 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
237 case MachineOperand::MO_GlobalAddress:
238 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
240 case MachineOperand::MO_BlockAddress:
241 return hash_combine(MO.getType(), MO.getTargetFlags(),
242 MO.getBlockAddress(), MO.getOffset());
243 case MachineOperand::MO_RegisterMask:
244 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
245 case MachineOperand::MO_Metadata:
246 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
247 case MachineOperand::MO_MCSymbol:
248 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
250 llvm_unreachable("Invalid machine operand type");
253 /// print - Print the specified machine operand.
255 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
256 // If the instruction is embedded into a basic block, we can find the
257 // target info for the instruction.
259 if (const MachineInstr *MI = getParent())
260 if (const MachineBasicBlock *MBB = MI->getParent())
261 if (const MachineFunction *MF = MBB->getParent())
262 TM = &MF->getTarget();
263 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
266 case MachineOperand::MO_Register:
267 OS << PrintReg(getReg(), TRI, getSubReg());
269 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
270 isInternalRead() || isEarlyClobber() || isTied()) {
272 bool NeedComma = false;
274 if (NeedComma) OS << ',';
275 if (isEarlyClobber())
276 OS << "earlyclobber,";
281 // <def,read-undef> only makes sense when getSubReg() is set.
282 // Don't clutter the output otherwise.
283 if (isUndef() && getSubReg())
285 } else if (isImplicit()) {
291 if (NeedComma) OS << ',';
296 if (NeedComma) OS << ',';
300 if (isUndef() && isUse()) {
301 if (NeedComma) OS << ',';
305 if (isInternalRead()) {
306 if (NeedComma) OS << ',';
311 if (NeedComma) OS << ',';
314 OS << unsigned(TiedTo - 1);
320 case MachineOperand::MO_Immediate:
323 case MachineOperand::MO_CImmediate:
324 getCImm()->getValue().print(OS, false);
326 case MachineOperand::MO_FPImmediate:
327 if (getFPImm()->getType()->isFloatTy())
328 OS << getFPImm()->getValueAPF().convertToFloat();
330 OS << getFPImm()->getValueAPF().convertToDouble();
332 case MachineOperand::MO_MachineBasicBlock:
333 OS << "<BB#" << getMBB()->getNumber() << ">";
335 case MachineOperand::MO_FrameIndex:
336 OS << "<fi#" << getIndex() << '>';
338 case MachineOperand::MO_ConstantPoolIndex:
339 OS << "<cp#" << getIndex();
340 if (getOffset()) OS << "+" << getOffset();
343 case MachineOperand::MO_TargetIndex:
344 OS << "<ti#" << getIndex();
345 if (getOffset()) OS << "+" << getOffset();
348 case MachineOperand::MO_JumpTableIndex:
349 OS << "<jt#" << getIndex() << '>';
351 case MachineOperand::MO_GlobalAddress:
353 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
354 if (getOffset()) OS << "+" << getOffset();
357 case MachineOperand::MO_ExternalSymbol:
358 OS << "<es:" << getSymbolName();
359 if (getOffset()) OS << "+" << getOffset();
362 case MachineOperand::MO_BlockAddress:
364 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
365 if (getOffset()) OS << "+" << getOffset();
368 case MachineOperand::MO_RegisterMask:
371 case MachineOperand::MO_Metadata:
373 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
376 case MachineOperand::MO_MCSymbol:
377 OS << "<MCSym=" << *getMCSymbol() << '>';
381 if (unsigned TF = getTargetFlags())
382 OS << "[TF=" << TF << ']';
385 //===----------------------------------------------------------------------===//
386 // MachineMemOperand Implementation
387 //===----------------------------------------------------------------------===//
389 /// getAddrSpace - Return the LLVM IR address space number that this pointer
391 unsigned MachinePointerInfo::getAddrSpace() const {
392 if (V == 0) return 0;
393 return cast<PointerType>(V->getType())->getAddressSpace();
396 /// getConstantPool - Return a MachinePointerInfo record that refers to the
398 MachinePointerInfo MachinePointerInfo::getConstantPool() {
399 return MachinePointerInfo(PseudoSourceValue::getConstantPool());
402 /// getFixedStack - Return a MachinePointerInfo record that refers to the
403 /// the specified FrameIndex.
404 MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
405 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
408 MachinePointerInfo MachinePointerInfo::getJumpTable() {
409 return MachinePointerInfo(PseudoSourceValue::getJumpTable());
412 MachinePointerInfo MachinePointerInfo::getGOT() {
413 return MachinePointerInfo(PseudoSourceValue::getGOT());
416 MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
417 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
420 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
421 uint64_t s, unsigned int a,
422 const MDNode *TBAAInfo,
423 const MDNode *Ranges)
424 : PtrInfo(ptrinfo), Size(s),
425 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
426 TBAAInfo(TBAAInfo), Ranges(Ranges) {
427 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
428 "invalid pointer value");
429 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
430 assert((isLoad() || isStore()) && "Not a load/store!");
433 /// Profile - Gather unique data for the object.
435 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
436 ID.AddInteger(getOffset());
438 ID.AddPointer(getValue());
439 ID.AddInteger(Flags);
442 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
443 // The Value and Offset may differ due to CSE. But the flags and size
444 // should be the same.
445 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
446 assert(MMO->getSize() == getSize() && "Size mismatch!");
448 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
449 // Update the alignment value.
450 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
451 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
452 // Also update the base and offset, because the new alignment may
453 // not be applicable with the old ones.
454 PtrInfo = MMO->PtrInfo;
458 /// getAlignment - Return the minimum known alignment in bytes of the
459 /// actual memory reference.
460 uint64_t MachineMemOperand::getAlignment() const {
461 return MinAlign(getBaseAlignment(), getOffset());
464 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
465 assert((MMO.isLoad() || MMO.isStore()) &&
466 "SV has to be a load, store or both.");
468 if (MMO.isVolatile())
477 // Print the address information.
482 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
484 unsigned AS = MMO.getAddrSpace();
486 OS << "(addrspace=" << AS << ')';
488 // If the alignment of the memory reference itself differs from the alignment
489 // of the base pointer, print the base alignment explicitly, next to the base
491 if (MMO.getBaseAlignment() != MMO.getAlignment())
492 OS << "(align=" << MMO.getBaseAlignment() << ")";
494 if (MMO.getOffset() != 0)
495 OS << "+" << MMO.getOffset();
498 // Print the alignment of the reference.
499 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
500 MMO.getBaseAlignment() != MMO.getSize())
501 OS << "(align=" << MMO.getAlignment() << ")";
504 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
506 if (TBAAInfo->getNumOperands() > 0)
507 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
513 // Print nontemporal info.
514 if (MMO.isNonTemporal())
515 OS << "(nontemporal)";
520 //===----------------------------------------------------------------------===//
521 // MachineInstr Implementation
522 //===----------------------------------------------------------------------===//
524 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
525 if (MCID->ImplicitDefs)
526 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
527 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
528 if (MCID->ImplicitUses)
529 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
530 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
533 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
534 /// implicit operands. It reserves space for the number of operands specified by
536 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
537 const DebugLoc dl, bool NoImp)
538 : MCID(&tid), Parent(0), Operands(0), NumOperands(0),
539 Flags(0), AsmPrinterFlags(0),
540 NumMemRefs(0), MemRefs(0), debugLoc(dl) {
541 // Reserve space for the expected number of operands.
542 if (unsigned NumOps = MCID->getNumOperands() +
543 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
544 CapOperands = OperandCapacity::get(NumOps);
545 Operands = MF.allocateOperandArray(CapOperands);
549 addImplicitDefUseOperands(MF);
552 /// MachineInstr ctor - Copies MachineInstr arg exactly
554 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
555 : MCID(&MI.getDesc()), Parent(0), Operands(0), NumOperands(0),
556 Flags(0), AsmPrinterFlags(0),
557 NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
558 debugLoc(MI.getDebugLoc()) {
559 CapOperands = OperandCapacity::get(MI.getNumOperands());
560 Operands = MF.allocateOperandArray(CapOperands);
563 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
564 addOperand(MF, MI.getOperand(i));
566 // Copy all the sensible flags.
570 /// getRegInfo - If this instruction is embedded into a MachineFunction,
571 /// return the MachineRegisterInfo object for the current function, otherwise
573 MachineRegisterInfo *MachineInstr::getRegInfo() {
574 if (MachineBasicBlock *MBB = getParent())
575 return &MBB->getParent()->getRegInfo();
579 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
580 /// this instruction from their respective use lists. This requires that the
581 /// operands already be on their use lists.
582 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
583 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
584 if (Operands[i].isReg())
585 MRI.removeRegOperandFromUseList(&Operands[i]);
588 /// AddRegOperandsToUseLists - Add all of the register operands in
589 /// this instruction from their respective use lists. This requires that the
590 /// operands not be on their use lists yet.
591 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
592 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
593 if (Operands[i].isReg())
594 MRI.addRegOperandToUseList(&Operands[i]);
597 void MachineInstr::addOperand(const MachineOperand &Op) {
598 MachineBasicBlock *MBB = getParent();
599 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
600 MachineFunction *MF = MBB->getParent();
601 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
605 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
606 /// ranges. If MRI is non-null also update use-def chains.
607 static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
608 unsigned NumOps, MachineRegisterInfo *MRI) {
610 return MRI->moveOperands(Dst, Src, NumOps);
612 // Here it would be convenient to call memmove, so that isn't allowed because
613 // MachineOperand has a constructor and so isn't a POD type.
615 for (unsigned i = 0; i != NumOps; ++i)
616 new (Dst + i) MachineOperand(Src[i]);
618 for (unsigned i = NumOps; i ; --i)
619 new (Dst + i - 1) MachineOperand(Src[i - 1]);
622 /// addOperand - Add the specified operand to the instruction. If it is an
623 /// implicit operand, it is added to the end of the operand list. If it is
624 /// an explicit operand it is added at the end of the explicit operand list
625 /// (before the first implicit operand).
626 void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
627 assert(MCID && "Cannot add operands before providing an instr descriptor");
629 // Check if we're adding one of our existing operands.
630 if (&Op >= Operands && &Op < Operands + NumOperands) {
631 // This is unusual: MI->addOperand(MI->getOperand(i)).
632 // If adding Op requires reallocating or moving existing operands around,
633 // the Op reference could go stale. Support it by copying Op.
634 MachineOperand CopyOp(Op);
635 return addOperand(MF, CopyOp);
638 // Find the insert location for the new operand. Implicit registers go at
639 // the end, everything else goes before the implicit regs.
641 // FIXME: Allow mixed explicit and implicit operands on inline asm.
642 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
643 // implicit-defs, but they must not be moved around. See the FIXME in
645 unsigned OpNo = getNumOperands();
646 bool isImpReg = Op.isReg() && Op.isImplicit();
647 if (!isImpReg && !isInlineAsm()) {
648 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
650 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
655 bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
656 // OpNo now points as the desired insertion point. Unless this is a variadic
657 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
658 // RegMask operands go between the explicit and implicit operands.
659 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
660 OpNo < MCID->getNumOperands() || isMetaDataOp) &&
661 "Trying to add an operand to a machine instr that is already done!");
664 MachineRegisterInfo *MRI = getRegInfo();
666 // Determine if the Operands array needs to be reallocated.
667 // Save the old capacity and operand array.
668 OperandCapacity OldCap = CapOperands;
669 MachineOperand *OldOperands = Operands;
670 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
671 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
672 Operands = MF.allocateOperandArray(CapOperands);
673 // Move the operands before the insertion point.
675 moveOperands(Operands, OldOperands, OpNo, MRI);
678 // Move the operands following the insertion point.
679 if (OpNo != NumOperands)
680 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
684 // Deallocate the old operand array.
685 if (OldOperands != Operands && OldOperands)
686 MF.deallocateOperandArray(OldCap, OldOperands);
688 // Copy Op into place. It still needs to be inserted into the MRI use lists.
689 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
690 NewMO->ParentMI = this;
692 // When adding a register operand, tell MRI about it.
693 if (NewMO->isReg()) {
694 // Ensure isOnRegUseList() returns false, regardless of Op's status.
695 NewMO->Contents.Reg.Prev = 0;
696 // Ignore existing ties. This is not a property that can be copied.
698 // Add the new operand to MRI, but only for instructions in an MBB.
700 MRI->addRegOperandToUseList(NewMO);
701 // The MCID operand information isn't accurate until we start adding
702 // explicit operands. The implicit operands are added first, then the
703 // explicits are inserted before them.
705 // Tie uses to defs as indicated in MCInstrDesc.
706 if (NewMO->isUse()) {
707 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
709 tieOperands(DefIdx, OpNo);
711 // If the register operand is flagged as early, mark the operand as such.
712 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
713 NewMO->setIsEarlyClobber(true);
718 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
719 /// fewer operand than it started with.
721 void MachineInstr::RemoveOperand(unsigned OpNo) {
722 assert(OpNo < getNumOperands() && "Invalid operand number");
723 untieRegOperand(OpNo);
726 // Moving tied operands would break the ties.
727 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
728 if (Operands[i].isReg())
729 assert(!Operands[i].isTied() && "Cannot move tied operands");
732 MachineRegisterInfo *MRI = getRegInfo();
733 if (MRI && Operands[OpNo].isReg())
734 MRI->removeRegOperandFromUseList(Operands + OpNo);
736 // Don't call the MachineOperand destructor. A lot of this code depends on
737 // MachineOperand having a trivial destructor anyway, and adding a call here
738 // wouldn't make it 'destructor-correct'.
740 if (unsigned N = NumOperands - 1 - OpNo)
741 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
745 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
746 /// This function should be used only occasionally. The setMemRefs function
747 /// is the primary method for setting up a MachineInstr's MemRefs list.
748 void MachineInstr::addMemOperand(MachineFunction &MF,
749 MachineMemOperand *MO) {
750 mmo_iterator OldMemRefs = MemRefs;
751 unsigned OldNumMemRefs = NumMemRefs;
753 unsigned NewNum = NumMemRefs + 1;
754 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
756 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
757 NewMemRefs[NewNum - 1] = MO;
758 setMemRefs(NewMemRefs, NewMemRefs + NewNum);
761 bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
762 assert(!isBundledWithPred() && "Must be called on bundle header");
763 for (MachineBasicBlock::const_instr_iterator MII = this;; ++MII) {
764 if (MII->getDesc().getFlags() & Mask) {
765 if (Type == AnyInBundle)
768 if (Type == AllInBundle && !MII->isBundle())
771 // This was the last instruction in the bundle.
772 if (!MII->isBundledWithSucc())
773 return Type == AllInBundle;
777 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
778 MICheckType Check) const {
779 // If opcodes or number of operands are not the same then the two
780 // instructions are obviously not identical.
781 if (Other->getOpcode() != getOpcode() ||
782 Other->getNumOperands() != getNumOperands())
786 // Both instructions are bundles, compare MIs inside the bundle.
787 MachineBasicBlock::const_instr_iterator I1 = *this;
788 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
789 MachineBasicBlock::const_instr_iterator I2 = *Other;
790 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
791 while (++I1 != E1 && I1->isInsideBundle()) {
793 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
798 // Check operands to make sure they match.
799 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
800 const MachineOperand &MO = getOperand(i);
801 const MachineOperand &OMO = Other->getOperand(i);
803 if (!MO.isIdenticalTo(OMO))
808 // Clients may or may not want to ignore defs when testing for equality.
809 // For example, machine CSE pass only cares about finding common
810 // subexpressions, so it's safe to ignore virtual register defs.
812 if (Check == IgnoreDefs)
814 else if (Check == IgnoreVRegDefs) {
815 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
816 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
817 if (MO.getReg() != OMO.getReg())
820 if (!MO.isIdenticalTo(OMO))
822 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
826 if (!MO.isIdenticalTo(OMO))
828 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
832 // If DebugLoc does not match then two dbg.values are not identical.
834 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
835 && getDebugLoc() != Other->getDebugLoc())
840 MachineInstr *MachineInstr::removeFromParent() {
841 assert(getParent() && "Not embedded in a basic block!");
842 return getParent()->remove(this);
845 MachineInstr *MachineInstr::removeFromBundle() {
846 assert(getParent() && "Not embedded in a basic block!");
847 return getParent()->remove_instr(this);
850 void MachineInstr::eraseFromParent() {
851 assert(getParent() && "Not embedded in a basic block!");
852 getParent()->erase(this);
855 void MachineInstr::eraseFromBundle() {
856 assert(getParent() && "Not embedded in a basic block!");
857 getParent()->erase_instr(this);
860 /// getNumExplicitOperands - Returns the number of non-implicit operands.
862 unsigned MachineInstr::getNumExplicitOperands() const {
863 unsigned NumOperands = MCID->getNumOperands();
864 if (!MCID->isVariadic())
867 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
868 const MachineOperand &MO = getOperand(i);
869 if (!MO.isReg() || !MO.isImplicit())
875 void MachineInstr::bundleWithPred() {
876 assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
877 setFlag(BundledPred);
878 MachineBasicBlock::instr_iterator Pred = this;
880 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
881 Pred->setFlag(BundledSucc);
884 void MachineInstr::bundleWithSucc() {
885 assert(!isBundledWithSucc() && "MI is already bundled with its successor");
886 setFlag(BundledSucc);
887 MachineBasicBlock::instr_iterator Succ = this;
889 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
890 Succ->setFlag(BundledPred);
893 void MachineInstr::unbundleFromPred() {
894 assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
895 clearFlag(BundledPred);
896 MachineBasicBlock::instr_iterator Pred = this;
898 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
899 Pred->clearFlag(BundledSucc);
902 void MachineInstr::unbundleFromSucc() {
903 assert(isBundledWithSucc() && "MI isn't bundled with its successor");
904 clearFlag(BundledSucc);
905 MachineBasicBlock::instr_iterator Succ = this;
907 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
908 Succ->clearFlag(BundledPred);
911 bool MachineInstr::isStackAligningInlineAsm() const {
913 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
914 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
920 InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
921 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
922 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
923 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
926 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
927 unsigned *GroupNo) const {
928 assert(isInlineAsm() && "Expected an inline asm instruction");
929 assert(OpIdx < getNumOperands() && "OpIdx out of range");
931 // Ignore queries about the initial operands.
932 if (OpIdx < InlineAsm::MIOp_FirstOperand)
937 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
939 const MachineOperand &FlagMO = getOperand(i);
940 // If we reach the implicit register operands, stop looking.
943 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
944 if (i + NumOps > OpIdx) {
954 const TargetRegisterClass*
955 MachineInstr::getRegClassConstraint(unsigned OpIdx,
956 const TargetInstrInfo *TII,
957 const TargetRegisterInfo *TRI) const {
958 assert(getParent() && "Can't have an MBB reference here!");
959 assert(getParent()->getParent() && "Can't have an MF reference here!");
960 const MachineFunction &MF = *getParent()->getParent();
962 // Most opcodes have fixed constraints in their MCInstrDesc.
964 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
966 if (!getOperand(OpIdx).isReg())
969 // For tied uses on inline asm, get the constraint from the def.
971 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
974 // Inline asm stores register class constraints in the flag word.
975 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
979 unsigned Flag = getOperand(FlagIdx).getImm();
981 if (InlineAsm::hasRegClassConstraint(Flag, RCID))
982 return TRI->getRegClass(RCID);
984 // Assume that all registers in a memory operand are pointers.
985 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
986 return TRI->getPointerRegClass(MF);
991 /// Return the number of instructions inside the MI bundle, not counting the
992 /// header instruction.
993 unsigned MachineInstr::getBundleSize() const {
994 MachineBasicBlock::const_instr_iterator I = this;
996 while (I->isBundledWithSucc())
1001 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1002 /// the specific register or -1 if it is not found. It further tightens
1003 /// the search criteria to a use that kills the register if isKill is true.
1004 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
1005 const TargetRegisterInfo *TRI) const {
1006 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1007 const MachineOperand &MO = getOperand(i);
1008 if (!MO.isReg() || !MO.isUse())
1010 unsigned MOReg = MO.getReg();
1015 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1016 TargetRegisterInfo::isPhysicalRegister(Reg) &&
1017 TRI->isSubRegister(MOReg, Reg)))
1018 if (!isKill || MO.isKill())
1024 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1025 /// indicating if this instruction reads or writes Reg. This also considers
1026 /// partial defines.
1027 std::pair<bool,bool>
1028 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1029 SmallVectorImpl<unsigned> *Ops) const {
1030 bool PartDef = false; // Partial redefine.
1031 bool FullDef = false; // Full define.
1034 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1035 const MachineOperand &MO = getOperand(i);
1036 if (!MO.isReg() || MO.getReg() != Reg)
1041 Use |= !MO.isUndef();
1042 else if (MO.getSubReg() && !MO.isUndef())
1043 // A partial <def,undef> doesn't count as reading the register.
1048 // A partial redefine uses Reg unless there is also a full define.
1049 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1052 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1053 /// the specified register or -1 if it is not found. If isDead is true, defs
1054 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1055 /// also checks if there is a def of a super-register.
1057 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1058 const TargetRegisterInfo *TRI) const {
1059 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1060 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1061 const MachineOperand &MO = getOperand(i);
1062 // Accept regmask operands when Overlap is set.
1063 // Ignore them when looking for a specific def operand (Overlap == false).
1064 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1066 if (!MO.isReg() || !MO.isDef())
1068 unsigned MOReg = MO.getReg();
1069 bool Found = (MOReg == Reg);
1070 if (!Found && TRI && isPhys &&
1071 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1073 Found = TRI->regsOverlap(MOReg, Reg);
1075 Found = TRI->isSubRegister(MOReg, Reg);
1077 if (Found && (!isDead || MO.isDead()))
1083 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1084 /// operand list that is used to represent the predicate. It returns -1 if
1086 int MachineInstr::findFirstPredOperandIdx() const {
1087 // Don't call MCID.findFirstPredOperandIdx() because this variant
1088 // is sometimes called on an instruction that's not yet complete, and
1089 // so the number of operands is less than the MCID indicates. In
1090 // particular, the PTX target does this.
1091 const MCInstrDesc &MCID = getDesc();
1092 if (MCID.isPredicable()) {
1093 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1094 if (MCID.OpInfo[i].isPredicate())
1101 // MachineOperand::TiedTo is 4 bits wide.
1102 const unsigned TiedMax = 15;
1104 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1106 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1107 /// field. TiedTo can have these values:
1109 /// 0: Operand is not tied to anything.
1110 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1111 /// TiedMax: Tied to an operand >= TiedMax-1.
1113 /// The tied def must be one of the first TiedMax operands on a normal
1114 /// instruction. INLINEASM instructions allow more tied defs.
1116 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1117 MachineOperand &DefMO = getOperand(DefIdx);
1118 MachineOperand &UseMO = getOperand(UseIdx);
1119 assert(DefMO.isDef() && "DefIdx must be a def operand");
1120 assert(UseMO.isUse() && "UseIdx must be a use operand");
1121 assert(!DefMO.isTied() && "Def is already tied to another use");
1122 assert(!UseMO.isTied() && "Use is already tied to another def");
1124 if (DefIdx < TiedMax)
1125 UseMO.TiedTo = DefIdx + 1;
1127 // Inline asm can use the group descriptors to find tied operands, but on
1128 // normal instruction, the tied def must be within the first TiedMax
1130 assert(isInlineAsm() && "DefIdx out of range");
1131 UseMO.TiedTo = TiedMax;
1134 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1135 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1138 /// Given the index of a tied register operand, find the operand it is tied to.
1139 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1140 /// which must exist.
1141 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1142 const MachineOperand &MO = getOperand(OpIdx);
1143 assert(MO.isTied() && "Operand isn't tied");
1145 // Normally TiedTo is in range.
1146 if (MO.TiedTo < TiedMax)
1147 return MO.TiedTo - 1;
1149 // Uses on normal instructions can be out of range.
1150 if (!isInlineAsm()) {
1151 // Normal tied defs must be in the 0..TiedMax-1 range.
1154 // MO is a def. Search for the tied use.
1155 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1156 const MachineOperand &UseMO = getOperand(i);
1157 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1160 llvm_unreachable("Can't find tied use");
1163 // Now deal with inline asm by parsing the operand group descriptor flags.
1164 // Find the beginning of each operand group.
1165 SmallVector<unsigned, 8> GroupIdx;
1166 unsigned OpIdxGroup = ~0u;
1168 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1170 const MachineOperand &FlagMO = getOperand(i);
1171 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1172 unsigned CurGroup = GroupIdx.size();
1173 GroupIdx.push_back(i);
1174 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1175 // OpIdx belongs to this operand group.
1176 if (OpIdx > i && OpIdx < i + NumOps)
1177 OpIdxGroup = CurGroup;
1179 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1181 // Operands in this group are tied to operands in TiedGroup which must be
1182 // earlier. Find the number of operands between the two groups.
1183 unsigned Delta = i - GroupIdx[TiedGroup];
1185 // OpIdx is a use tied to TiedGroup.
1186 if (OpIdxGroup == CurGroup)
1187 return OpIdx - Delta;
1189 // OpIdx is a def tied to this use group.
1190 if (OpIdxGroup == TiedGroup)
1191 return OpIdx + Delta;
1193 llvm_unreachable("Invalid tied operand on inline asm");
1196 /// clearKillInfo - Clears kill flags on all operands.
1198 void MachineInstr::clearKillInfo() {
1199 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1200 MachineOperand &MO = getOperand(i);
1201 if (MO.isReg() && MO.isUse())
1202 MO.setIsKill(false);
1206 void MachineInstr::substituteRegister(unsigned FromReg,
1209 const TargetRegisterInfo &RegInfo) {
1210 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1212 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1213 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1214 MachineOperand &MO = getOperand(i);
1215 if (!MO.isReg() || MO.getReg() != FromReg)
1217 MO.substPhysReg(ToReg, RegInfo);
1220 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1221 MachineOperand &MO = getOperand(i);
1222 if (!MO.isReg() || MO.getReg() != FromReg)
1224 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1229 /// isSafeToMove - Return true if it is safe to move this instruction. If
1230 /// SawStore is set to true, it means that there is a store (or call) between
1231 /// the instruction's location and its intended destination.
1232 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1234 bool &SawStore) const {
1235 // Ignore stuff that we obviously can't move.
1237 // Treat volatile loads as stores. This is not strictly necessary for
1238 // volatiles, but it is required for atomic loads. It is not allowed to move
1239 // a load across an atomic load with Ordering > Monotonic.
1240 if (mayStore() || isCall() ||
1241 (mayLoad() && hasOrderedMemoryRef())) {
1246 if (isLabel() || isDebugValue() ||
1247 isTerminator() || hasUnmodeledSideEffects())
1250 // See if this instruction does a load. If so, we have to guarantee that the
1251 // loaded value doesn't change between the load and the its intended
1252 // destination. The check for isInvariantLoad gives the targe the chance to
1253 // classify the load as always returning a constant, e.g. a constant pool
1255 if (mayLoad() && !isInvariantLoad(AA))
1256 // Otherwise, this is a real load. If there is a store between the load and
1257 // end of block, we can't move it.
1263 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1264 /// or volatile memory reference, or if the information describing the memory
1265 /// reference is not available. Return false if it is known to have no ordered
1266 /// memory references.
1267 bool MachineInstr::hasOrderedMemoryRef() const {
1268 // An instruction known never to access memory won't have a volatile access.
1272 !hasUnmodeledSideEffects())
1275 // Otherwise, if the instruction has no memory reference information,
1276 // conservatively assume it wasn't preserved.
1277 if (memoperands_empty())
1280 // Check the memory reference information for ordered references.
1281 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1282 if (!(*I)->isUnordered())
1288 /// isInvariantLoad - Return true if this instruction is loading from a
1289 /// location whose value is invariant across the function. For example,
1290 /// loading a value from the constant pool or from the argument area
1291 /// of a function if it does not change. This should only return true of
1292 /// *all* loads the instruction does are invariant (if it does multiple loads).
1293 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1294 // If the instruction doesn't load at all, it isn't an invariant load.
1298 // If the instruction has lost its memoperands, conservatively assume that
1299 // it may not be an invariant load.
1300 if (memoperands_empty())
1303 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1305 for (mmo_iterator I = memoperands_begin(),
1306 E = memoperands_end(); I != E; ++I) {
1307 if ((*I)->isVolatile()) return false;
1308 if ((*I)->isStore()) return false;
1309 if ((*I)->isInvariant()) return true;
1311 if (const Value *V = (*I)->getValue()) {
1312 // A load from a constant PseudoSourceValue is invariant.
1313 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1314 if (PSV->isConstant(MFI))
1316 // If we have an AliasAnalysis, ask it whether the memory is constant.
1317 if (AA && AA->pointsToConstantMemory(
1318 AliasAnalysis::Location(V, (*I)->getSize(),
1319 (*I)->getTBAAInfo())))
1323 // Otherwise assume conservatively.
1327 // Everything checks out.
1331 /// isConstantValuePHI - If the specified instruction is a PHI that always
1332 /// merges together the same virtual register, return the register, otherwise
1334 unsigned MachineInstr::isConstantValuePHI() const {
1337 assert(getNumOperands() >= 3 &&
1338 "It's illegal to have a PHI without source operands");
1340 unsigned Reg = getOperand(1).getReg();
1341 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1342 if (getOperand(i).getReg() != Reg)
1347 bool MachineInstr::hasUnmodeledSideEffects() const {
1348 if (hasProperty(MCID::UnmodeledSideEffects))
1350 if (isInlineAsm()) {
1351 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1352 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1359 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1361 bool MachineInstr::allDefsAreDead() const {
1362 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1363 const MachineOperand &MO = getOperand(i);
1364 if (!MO.isReg() || MO.isUse())
1372 /// copyImplicitOps - Copy implicit register operands from specified
1373 /// instruction to this instruction.
1374 void MachineInstr::copyImplicitOps(MachineFunction &MF,
1375 const MachineInstr *MI) {
1376 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1378 const MachineOperand &MO = MI->getOperand(i);
1379 if (MO.isReg() && MO.isImplicit())
1384 void MachineInstr::dump() const {
1385 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1386 dbgs() << " " << *this;
1390 static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1391 raw_ostream &CommentOS) {
1392 const LLVMContext &Ctx = MF->getFunction()->getContext();
1393 if (!DL.isUnknown()) { // Print source line info.
1394 DIScope Scope(DL.getScope(Ctx));
1395 assert((!Scope || Scope.isScope()) &&
1396 "Scope of a DebugLoc should be null or a DIScope.");
1397 // Omit the directory, because it's likely to be long and uninteresting.
1399 CommentOS << Scope.getFilename();
1401 CommentOS << "<unknown>";
1402 CommentOS << ':' << DL.getLine();
1403 if (DL.getCol() != 0)
1404 CommentOS << ':' << DL.getCol();
1405 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1406 if (!InlinedAtDL.isUnknown()) {
1407 CommentOS << " @[ ";
1408 printDebugLoc(InlinedAtDL, MF, CommentOS);
1414 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
1415 bool SkipOpers) const {
1416 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1417 const MachineFunction *MF = 0;
1418 const MachineRegisterInfo *MRI = 0;
1419 if (const MachineBasicBlock *MBB = getParent()) {
1420 MF = MBB->getParent();
1422 TM = &MF->getTarget();
1424 MRI = &MF->getRegInfo();
1427 // Save a list of virtual registers.
1428 SmallVector<unsigned, 8> VirtRegs;
1430 // Print explicitly defined operands on the left of an assignment syntax.
1431 unsigned StartOp = 0, e = getNumOperands();
1432 for (; StartOp < e && getOperand(StartOp).isReg() &&
1433 getOperand(StartOp).isDef() &&
1434 !getOperand(StartOp).isImplicit();
1436 if (StartOp != 0) OS << ", ";
1437 getOperand(StartOp).print(OS, TM);
1438 unsigned Reg = getOperand(StartOp).getReg();
1439 if (TargetRegisterInfo::isVirtualRegister(Reg))
1440 VirtRegs.push_back(Reg);
1446 // Print the opcode name.
1447 if (TM && TM->getInstrInfo())
1448 OS << TM->getInstrInfo()->getName(getOpcode());
1455 // Print the rest of the operands.
1456 bool OmittedAnyCallClobbers = false;
1457 bool FirstOp = true;
1458 unsigned AsmDescOp = ~0u;
1459 unsigned AsmOpCount = 0;
1461 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1462 // Print asm string.
1464 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1466 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1467 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1468 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1469 OS << " [sideeffect]";
1470 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1472 if (ExtraInfo & InlineAsm::Extra_MayStore)
1473 OS << " [maystore]";
1474 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1475 OS << " [alignstack]";
1476 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1477 OS << " [attdialect]";
1478 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1479 OS << " [inteldialect]";
1481 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1486 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1487 const MachineOperand &MO = getOperand(i);
1489 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1490 VirtRegs.push_back(MO.getReg());
1492 // Omit call-clobbered registers which aren't used anywhere. This makes
1493 // call instructions much less noisy on targets where calls clobber lots
1494 // of registers. Don't rely on MO.isDead() because we may be called before
1495 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1496 if (MF && isCall() &&
1497 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1498 unsigned Reg = MO.getReg();
1499 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1500 const MachineRegisterInfo &MRI = MF->getRegInfo();
1501 if (MRI.use_empty(Reg)) {
1502 bool HasAliasLive = false;
1503 for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true);
1504 AI.isValid(); ++AI) {
1505 unsigned AliasReg = *AI;
1506 if (!MRI.use_empty(AliasReg)) {
1507 HasAliasLive = true;
1511 if (!HasAliasLive) {
1512 OmittedAnyCallClobbers = true;
1519 if (FirstOp) FirstOp = false; else OS << ",";
1521 if (i < getDesc().NumOperands) {
1522 const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1523 if (MCOI.isPredicate())
1525 if (MCOI.isOptionalDef())
1528 if (isDebugValue() && MO.isMetadata()) {
1529 // Pretty print DBG_VALUE instructions.
1530 const MDNode *MD = MO.getMetadata();
1531 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1532 OS << "!\"" << MDS->getString() << '\"';
1535 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1536 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1537 } else if (i == AsmDescOp && MO.isImm()) {
1538 // Pretty print the inline asm operand descriptor.
1539 OS << '$' << AsmOpCount++;
1540 unsigned Flag = MO.getImm();
1541 switch (InlineAsm::getKind(Flag)) {
1542 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1543 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1544 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1545 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1546 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1547 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1548 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1552 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1554 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1556 OS << ":RC" << RCID;
1559 unsigned TiedTo = 0;
1560 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1561 OS << " tiedto:$" << TiedTo;
1565 // Compute the index of the next operand descriptor.
1566 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1571 // Briefly indicate whether any call clobbers were omitted.
1572 if (OmittedAnyCallClobbers) {
1573 if (!FirstOp) OS << ",";
1577 bool HaveSemi = false;
1578 const unsigned PrintableFlags = FrameSetup;
1579 if (Flags & PrintableFlags) {
1580 if (!HaveSemi) OS << ";"; HaveSemi = true;
1583 if (Flags & FrameSetup)
1587 if (!memoperands_empty()) {
1588 if (!HaveSemi) OS << ";"; HaveSemi = true;
1591 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1594 if (llvm::next(i) != e)
1599 // Print the regclass of any virtual registers encountered.
1600 if (MRI && !VirtRegs.empty()) {
1601 if (!HaveSemi) OS << ";"; HaveSemi = true;
1602 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1603 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1604 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1605 for (unsigned j = i+1; j != VirtRegs.size();) {
1606 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1610 if (VirtRegs[i] != VirtRegs[j])
1611 OS << "," << PrintReg(VirtRegs[j]);
1612 VirtRegs.erase(VirtRegs.begin()+j);
1617 // Print debug location information.
1618 if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1619 if (!HaveSemi) OS << ";"; HaveSemi = true;
1620 DIVariable DV(getOperand(e - 1).getMetadata());
1621 OS << " line no:" << DV.getLineNumber();
1622 if (MDNode *InlinedAt = DV.getInlinedAt()) {
1623 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1624 if (!InlinedAtDL.isUnknown()) {
1625 OS << " inlined @[ ";
1626 printDebugLoc(InlinedAtDL, MF, OS);
1630 } else if (!debugLoc.isUnknown() && MF) {
1631 if (!HaveSemi) OS << ";"; HaveSemi = true;
1633 printDebugLoc(debugLoc, MF, OS);
1639 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1640 const TargetRegisterInfo *RegInfo,
1641 bool AddIfNotFound) {
1642 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1643 bool hasAliases = isPhysReg &&
1644 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1646 SmallVector<unsigned,4> DeadOps;
1647 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1648 MachineOperand &MO = getOperand(i);
1649 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1651 unsigned Reg = MO.getReg();
1655 if (Reg == IncomingReg) {
1658 // The register is already marked kill.
1660 if (isPhysReg && isRegTiedToDefOperand(i))
1661 // Two-address uses of physregs must not be marked kill.
1666 } else if (hasAliases && MO.isKill() &&
1667 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1668 // A super-register kill already exists.
1669 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1671 if (RegInfo->isSubRegister(IncomingReg, Reg))
1672 DeadOps.push_back(i);
1676 // Trim unneeded kill operands.
1677 while (!DeadOps.empty()) {
1678 unsigned OpIdx = DeadOps.back();
1679 if (getOperand(OpIdx).isImplicit())
1680 RemoveOperand(OpIdx);
1682 getOperand(OpIdx).setIsKill(false);
1686 // If not found, this means an alias of one of the operands is killed. Add a
1687 // new implicit operand if required.
1688 if (!Found && AddIfNotFound) {
1689 addOperand(MachineOperand::CreateReg(IncomingReg,
1698 void MachineInstr::clearRegisterKills(unsigned Reg,
1699 const TargetRegisterInfo *RegInfo) {
1700 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1702 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1703 MachineOperand &MO = getOperand(i);
1704 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1706 unsigned OpReg = MO.getReg();
1707 if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1708 MO.setIsKill(false);
1712 bool MachineInstr::addRegisterDead(unsigned Reg,
1713 const TargetRegisterInfo *RegInfo,
1714 bool AddIfNotFound) {
1715 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
1716 bool hasAliases = isPhysReg &&
1717 MCRegAliasIterator(Reg, RegInfo, false).isValid();
1719 SmallVector<unsigned,4> DeadOps;
1720 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1721 MachineOperand &MO = getOperand(i);
1722 if (!MO.isReg() || !MO.isDef())
1724 unsigned MOReg = MO.getReg();
1731 } else if (hasAliases && MO.isDead() &&
1732 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1733 // There exists a super-register that's marked dead.
1734 if (RegInfo->isSuperRegister(Reg, MOReg))
1736 if (RegInfo->isSubRegister(Reg, MOReg))
1737 DeadOps.push_back(i);
1741 // Trim unneeded dead operands.
1742 while (!DeadOps.empty()) {
1743 unsigned OpIdx = DeadOps.back();
1744 if (getOperand(OpIdx).isImplicit())
1745 RemoveOperand(OpIdx);
1747 getOperand(OpIdx).setIsDead(false);
1751 // If not found, this means an alias of one of the operands is dead. Add a
1752 // new implicit operand if required.
1753 if (Found || !AddIfNotFound)
1756 addOperand(MachineOperand::CreateReg(Reg,
1764 void MachineInstr::addRegisterDefined(unsigned Reg,
1765 const TargetRegisterInfo *RegInfo) {
1766 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1767 MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
1771 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1772 const MachineOperand &MO = getOperand(i);
1773 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1774 MO.getSubReg() == 0)
1778 addOperand(MachineOperand::CreateReg(Reg,
1783 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1784 const TargetRegisterInfo &TRI) {
1785 bool HasRegMask = false;
1786 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1787 MachineOperand &MO = getOperand(i);
1788 if (MO.isRegMask()) {
1792 if (!MO.isReg() || !MO.isDef()) continue;
1793 unsigned Reg = MO.getReg();
1794 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1796 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1798 if (TRI.regsOverlap(*I, Reg)) {
1802 // If there are no uses, including partial uses, the def is dead.
1803 if (Dead) MO.setIsDead();
1806 // This is a call with a register mask operand.
1807 // Mask clobbers are always dead, so add defs for the non-dead defines.
1809 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1811 addRegisterDefined(*I, &TRI);
1815 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1816 // Build up a buffer of hash code components.
1817 SmallVector<size_t, 8> HashComponents;
1818 HashComponents.reserve(MI->getNumOperands() + 1);
1819 HashComponents.push_back(MI->getOpcode());
1820 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1821 const MachineOperand &MO = MI->getOperand(i);
1822 if (MO.isReg() && MO.isDef() &&
1823 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1824 continue; // Skip virtual register defs.
1826 HashComponents.push_back(hash_value(MO));
1828 return hash_combine_range(HashComponents.begin(), HashComponents.end());
1831 void MachineInstr::emitError(StringRef Msg) const {
1832 // Find the source location cookie.
1833 unsigned LocCookie = 0;
1834 const MDNode *LocMD = 0;
1835 for (unsigned i = getNumOperands(); i != 0; --i) {
1836 if (getOperand(i-1).isMetadata() &&
1837 (LocMD = getOperand(i-1).getMetadata()) &&
1838 LocMD->getNumOperands() != 0) {
1839 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1840 LocCookie = CI->getZExtValue();
1846 if (const MachineBasicBlock *MBB = getParent())
1847 if (const MachineFunction *MF = MBB->getParent())
1848 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1849 report_fatal_error(Msg);