1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 // FIXME: Now that MachineInstrs have parent pointers, they should always
13 // print themselves using their MachineFunction's TargetMachine.
15 //===----------------------------------------------------------------------===//
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Value.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/MRegisterInfo.h"
23 #include "Support/LeakDetector.h"
26 // Global variable holding an array of descriptors for machine instructions.
27 // The actual object needs to be created separately for each target machine.
28 // This variable is initialized and reset by class TargetInstrInfo.
30 // FIXME: This should be a property of the target so that more than one target
31 // at a time can be active...
34 extern const TargetInstrDescriptor *TargetInstrDescriptors;
37 // Constructor for instructions with variable #operands
38 MachineInstr::MachineInstr(short opcode, unsigned numOperands)
41 operands(numOperands, MachineOperand()),
43 // Make sure that we get added to a machine basicblock
44 LeakDetector::addGarbageObject(this);
47 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
48 /// not a resize for them. It is expected that if you use this that you call
49 /// add* methods below to fill up the operands, instead of the Set methods.
50 /// Eventually, the "resizing" ctors will be phased out.
52 MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY)
53 : Opcode(opcode), numImplicitRefs(0), parent(0) {
54 operands.reserve(numOperands);
55 // Make sure that we get added to a machine basicblock
56 LeakDetector::addGarbageObject(this);
59 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
60 /// MachineInstr is created and added to the end of the specified basic block.
62 MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
64 : Opcode(opcode), numImplicitRefs(0), parent(0) {
65 assert(MBB && "Cannot use inserting ctor with null basic block!");
66 operands.reserve(numOperands);
67 // Make sure that we get added to a machine basicblock
68 LeakDetector::addGarbageObject(this);
69 MBB->push_back(this); // Add instruction to end of basic block!
72 ///MachineInstr ctor - Copies MachineInstr arg exactly
73 MachineInstr::MachineInstr(const MachineInstr &MI) {
74 Opcode = MI.getOpcode();
75 numImplicitRefs = MI.getNumImplicitRefs();
76 operands.reserve(MI.getNumOperands());
79 for(unsigned i=0; i < MI.getNumOperands(); ++i)
80 operands.push_back(MachineOperand(MI.getOperand(i)));
82 //Set parent, next, and prev to null
90 MachineInstr::~MachineInstr()
92 LeakDetector::removeGarbageObject(this);
95 ///clone - Create a copy of 'this' instruction that is identical in
96 ///all ways except the following: The instruction has no parent The
97 ///instruction has no name
98 MachineInstr* MachineInstr::clone() const {
99 return new MachineInstr(*this);
102 /// OperandComplete - Return true if it's illegal to add a new operand
104 bool MachineInstr::OperandsComplete() const {
105 int NumOperands = TargetInstrDescriptors[Opcode].numOperands;
106 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
107 return true; // Broken: we have all the operands of this instruction!
111 /// replace - Support for replacing opcode and operands of a MachineInstr in
112 /// place. This only resets the size of the operand vector and initializes it.
113 /// The new operands must be set explicitly later.
115 void MachineInstr::replace(short opcode, unsigned numOperands) {
116 assert(getNumImplicitRefs() == 0 &&
117 "This is probably broken because implicit refs are going to be lost.");
120 operands.resize(numOperands, MachineOperand());
124 void MachineInstr::SetMachineOperandVal(unsigned i,
125 MachineOperand::MachineOperandType opTy,
127 assert(i < operands.size()); // may be explicit or implicit op
128 operands[i].opType = opTy;
129 operands[i].contents.value = V;
130 operands[i].regNum = -1;
134 MachineInstr::SetMachineOperandConst(unsigned i,
135 MachineOperand::MachineOperandType opTy,
137 assert(i < getNumOperands()); // must be explicit op
138 assert(TargetInstrDescriptors[Opcode].resultPos != (int) i &&
139 "immed. constant cannot be defined");
141 operands[i].opType = opTy;
142 operands[i].contents.value = NULL;
143 operands[i].contents.immedVal = intValue;
144 operands[i].regNum = -1;
145 operands[i].flags = 0;
148 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
149 assert(i < getNumOperands()); // must be explicit op
151 operands[i].opType = MachineOperand::MO_MachineRegister;
152 operands[i].contents.value = NULL;
153 operands[i].regNum = regNum;
156 // Used only by the SPARC back-end.
157 void MachineInstr::SetRegForOperand(unsigned i, int regNum) {
158 assert(i < getNumOperands()); // must be explicit op
159 operands[i].setRegForValue(regNum);
162 // Used only by the SPARC back-end.
163 void MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) {
164 getImplicitOp(i).setRegForValue(regNum);
167 /// substituteValue - Substitute all occurrences of Value* oldVal with newVal
168 /// in all operands and all implicit refs. If defsOnly == true, substitute defs
171 /// FIXME: Fold this into its single caller, at SparcInstrSelection.cpp:2865,
172 /// or make it a static function in that file.
175 MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
176 bool defsOnly, bool notDefsAndUses,
177 bool& someArgsWereIgnored)
179 assert((!defsOnly || !notDefsAndUses) &&
180 "notDefsAndUses is irrelevant if defsOnly == true.");
182 unsigned numSubst = 0;
184 // Substitute operands
185 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
188 notDefsAndUses && (O.isDef() && !O.isUse()) ||
189 !notDefsAndUses && O.isDef())
191 O.getMachineOperand().contents.value = newVal;
195 someArgsWereIgnored = true;
197 // Substitute implicit refs
198 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
199 if (getImplicitRef(i) == oldVal)
201 notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) ||
202 !notDefsAndUses && getImplicitOp(i).isDef())
204 getImplicitOp(i).contents.value = newVal;
208 someArgsWereIgnored = true;
213 void MachineInstr::dump() const {
214 std::cerr << " " << *this;
217 static inline std::ostream& OutputValue(std::ostream &os, const Value* val) {
219 os << (void*) val; // print address always
220 if (val && val->hasName())
221 os << " " << val->getName(); // print name also, if available
226 static inline void OutputReg(std::ostream &os, unsigned RegNo,
227 const MRegisterInfo *MRI = 0) {
228 if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) {
230 os << "%" << MRI->get(RegNo).Name;
232 os << "%mreg(" << RegNo << ")";
234 os << "%reg" << RegNo;
237 static void print(const MachineOperand &MO, std::ostream &OS,
238 const TargetMachine *TM) {
240 const MRegisterInfo *MRI = 0;
243 MRI = TM->getRegisterInfo();
246 bool CloseParen = true;
249 else if (MO.isLoBits32())
251 else if (MO.isHiBits64())
253 else if (MO.isLoBits64())
258 switch (MO.getType()) {
259 case MachineOperand::MO_VirtualRegister:
260 if (MO.getVRegValue()) {
262 OutputValue(OS, MO.getVRegValue());
263 if (MO.hasAllocatedReg())
266 if (MO.hasAllocatedReg())
267 OutputReg(OS, MO.getReg(), MRI);
269 case MachineOperand::MO_CCRegister:
271 OutputValue(OS, MO.getVRegValue());
272 if (MO.hasAllocatedReg()) {
274 OutputReg(OS, MO.getReg(), MRI);
277 case MachineOperand::MO_MachineRegister:
278 OutputReg(OS, MO.getMachineRegNum(), MRI);
280 case MachineOperand::MO_SignExtendedImmed:
281 OS << (long)MO.getImmedValue();
283 case MachineOperand::MO_UnextendedImmed:
284 OS << (long)MO.getImmedValue();
286 case MachineOperand::MO_PCRelativeDisp: {
287 const Value* opVal = MO.getVRegValue();
288 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
289 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
290 if (opVal->hasName())
291 OS << opVal->getName();
293 OS << (const void*) opVal;
297 case MachineOperand::MO_MachineBasicBlock:
299 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
300 << "," << (void*)MO.getMachineBasicBlock() << ">";
302 case MachineOperand::MO_FrameIndex:
303 OS << "<fi#" << MO.getFrameIndex() << ">";
305 case MachineOperand::MO_ConstantPoolIndex:
306 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
308 case MachineOperand::MO_GlobalAddress:
309 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
311 case MachineOperand::MO_ExternalSymbol:
312 OS << "<es:" << MO.getSymbolName() << ">";
315 assert(0 && "Unrecognized operand type");
322 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
323 unsigned StartOp = 0;
325 // Specialize printing if op#0 is definition
326 if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
327 ::print(getOperand(0), OS, TM);
329 ++StartOp; // Don't print this operand again!
332 //Must check if Target machine is not null because machine BB could not
333 //be attached to a Machine function yet
335 OS << TM->getInstrInfo()->getName(getOpcode());
337 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
338 const MachineOperand& mop = getOperand(i);
342 ::print(mop, OS, TM);
351 // code for printing implicit references
352 if (getNumImplicitRefs()) {
353 OS << "\tImplicitRefs: ";
354 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
356 OutputValue(OS, getImplicitRef(i));
357 if (getImplicitOp(i).isDef())
358 if (getImplicitOp(i).isUse())
369 std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
370 // If the instruction is embedded into a basic block, we can find the target
371 // info for the instruction.
372 if (const MachineBasicBlock *MBB = MI.getParent()) {
373 const MachineFunction *MF = MBB->getParent();
375 MI.print(os, &MF->getTarget());
381 // Otherwise, print it out in the "raw" format without symbolic register names
383 os << TargetInstrDescriptors[MI.getOpcode()].Name;
385 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
386 os << "\t" << MI.getOperand(i);
387 if (MI.getOperand(i).isDef())
388 if (MI.getOperand(i).isUse())
394 // code for printing implicit references
395 unsigned NumOfImpRefs = MI.getNumImplicitRefs();
396 if (NumOfImpRefs > 0) {
397 os << "\tImplicit: ";
398 for (unsigned z=0; z < NumOfImpRefs; z++) {
399 OutputValue(os, MI.getImplicitRef(z));
400 if (MI.getImplicitOp(z).isDef())
401 if (MI.getImplicitOp(z).isUse())
412 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
415 else if (MO.isLoBits32())
417 else if (MO.isHiBits64())
419 else if (MO.isLoBits64())
422 switch (MO.getType())
424 case MachineOperand::MO_VirtualRegister:
425 if (MO.hasAllocatedReg())
426 OutputReg(OS, MO.getReg());
428 if (MO.getVRegValue()) {
429 if (MO.hasAllocatedReg()) OS << "==";
431 OutputValue(OS, MO.getVRegValue());
434 case MachineOperand::MO_CCRegister:
436 OutputValue(OS, MO.getVRegValue());
437 if (MO.hasAllocatedReg()) {
439 OutputReg(OS, MO.getReg());
442 case MachineOperand::MO_MachineRegister:
443 OutputReg(OS, MO.getMachineRegNum());
445 case MachineOperand::MO_SignExtendedImmed:
446 OS << (long)MO.getImmedValue();
448 case MachineOperand::MO_UnextendedImmed:
449 OS << (long)MO.getImmedValue();
451 case MachineOperand::MO_PCRelativeDisp:
453 const Value* opVal = MO.getVRegValue();
454 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
455 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
456 if (opVal->hasName())
457 OS << opVal->getName();
459 OS << (const void*) opVal;
463 case MachineOperand::MO_MachineBasicBlock:
465 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
466 << "@" << (void*)MO.getMachineBasicBlock() << ">";
468 case MachineOperand::MO_FrameIndex:
469 OS << "<fi#" << MO.getFrameIndex() << ">";
471 case MachineOperand::MO_ConstantPoolIndex:
472 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
474 case MachineOperand::MO_GlobalAddress:
475 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
477 case MachineOperand::MO_ExternalSymbol:
478 OS << "<es:" << MO.getSymbolName() << ">";
481 assert(0 && "Unrecognized operand type");
485 if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64())