1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Value.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/CodeGen/PseudoSourceValue.h"
19 #include "llvm/CodeGen/SelectionDAGNodes.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetInstrDesc.h"
23 #include "llvm/Target/MRegisterInfo.h"
24 #include "llvm/Support/LeakDetector.h"
25 #include "llvm/Support/Streams.h"
29 //===----------------------------------------------------------------------===//
30 // MachineOperand Implementation
31 //===----------------------------------------------------------------------===//
33 /// AddRegOperandToRegInfo - Add this register operand to the specified
34 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
35 /// explicitly nulled out.
36 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
37 assert(isReg() && "Can only add reg operand to use lists");
39 // If the reginfo pointer is null, just explicitly null out or next/prev
40 // pointers, to ensure they are not garbage.
42 Contents.Reg.Prev = 0;
43 Contents.Reg.Next = 0;
47 // Otherwise, add this operand to the head of the registers use/def list.
48 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
50 // For SSA values, we prefer to keep the definition at the start of the list.
51 // we do this by skipping over the definition if it is at the head of the
53 if (*Head && (*Head)->isDef())
54 Head = &(*Head)->Contents.Reg.Next;
56 Contents.Reg.Next = *Head;
57 if (Contents.Reg.Next) {
58 assert(getReg() == Contents.Reg.Next->getReg() &&
59 "Different regs on the same list!");
60 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
63 Contents.Reg.Prev = Head;
67 void MachineOperand::setReg(unsigned Reg) {
68 if (getReg() == Reg) return; // No change.
70 // Otherwise, we have to change the register. If this operand is embedded
71 // into a machine function, we need to update the old and new register's
73 if (MachineInstr *MI = getParent())
74 if (MachineBasicBlock *MBB = MI->getParent())
75 if (MachineFunction *MF = MBB->getParent()) {
76 RemoveRegOperandFromRegInfo();
77 Contents.Reg.RegNo = Reg;
78 AddRegOperandToRegInfo(&MF->getRegInfo());
82 // Otherwise, just change the register, no problem. :)
83 Contents.Reg.RegNo = Reg;
86 /// ChangeToImmediate - Replace this operand with a new immediate operand of
87 /// the specified value. If an operand is known to be an immediate already,
88 /// the setImm method should be used.
89 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
90 // If this operand is currently a register operand, and if this is in a
91 // function, deregister the operand from the register's use/def list.
92 if (isReg() && getParent() && getParent()->getParent() &&
93 getParent()->getParent()->getParent())
94 RemoveRegOperandFromRegInfo();
96 OpKind = MO_Immediate;
97 Contents.ImmVal = ImmVal;
100 /// ChangeToRegister - Replace this operand with a new register operand of
101 /// the specified value. If an operand is known to be an register already,
102 /// the setReg method should be used.
103 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
104 bool isKill, bool isDead) {
105 // If this operand is already a register operand, use setReg to update the
106 // register's use/def lists.
110 // Otherwise, change this to a register and set the reg#.
111 OpKind = MO_Register;
112 Contents.Reg.RegNo = Reg;
114 // If this operand is embedded in a function, add the operand to the
115 // register's use/def list.
116 if (MachineInstr *MI = getParent())
117 if (MachineBasicBlock *MBB = MI->getParent())
118 if (MachineFunction *MF = MBB->getParent())
119 AddRegOperandToRegInfo(&MF->getRegInfo());
129 /// isIdenticalTo - Return true if this operand is identical to the specified
131 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
132 if (getType() != Other.getType()) return false;
135 default: assert(0 && "Unrecognized operand type");
136 case MachineOperand::MO_Register:
137 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
138 getSubReg() == Other.getSubReg();
139 case MachineOperand::MO_Immediate:
140 return getImm() == Other.getImm();
141 case MachineOperand::MO_MachineBasicBlock:
142 return getMBB() == Other.getMBB();
143 case MachineOperand::MO_FrameIndex:
144 return getIndex() == Other.getIndex();
145 case MachineOperand::MO_ConstantPoolIndex:
146 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
147 case MachineOperand::MO_JumpTableIndex:
148 return getIndex() == Other.getIndex();
149 case MachineOperand::MO_GlobalAddress:
150 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
151 case MachineOperand::MO_ExternalSymbol:
152 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
153 getOffset() == Other.getOffset();
157 /// print - Print the specified machine operand.
159 void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
161 case MachineOperand::MO_Register:
162 if (getReg() == 0 || MRegisterInfo::isVirtualRegister(getReg())) {
163 OS << "%reg" << getReg();
165 // If the instruction is embedded into a basic block, we can find the
166 // target info for the instruction.
168 if (const MachineInstr *MI = getParent())
169 if (const MachineBasicBlock *MBB = MI->getParent())
170 if (const MachineFunction *MF = MBB->getParent())
171 TM = &MF->getTarget();
174 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
176 OS << "%mreg" << getReg();
179 if (isDef() || isKill() || isDead() || isImplicit()) {
181 bool NeedComma = false;
183 OS << (isDef() ? "imp-def" : "imp-use");
185 } else if (isDef()) {
189 if (isKill() || isDead()) {
190 if (NeedComma) OS << ",";
191 if (isKill()) OS << "kill";
192 if (isDead()) OS << "dead";
197 case MachineOperand::MO_Immediate:
200 case MachineOperand::MO_MachineBasicBlock:
202 << ((Value*)getMBB()->getBasicBlock())->getName()
203 << "," << (void*)getMBB() << ">";
205 case MachineOperand::MO_FrameIndex:
206 OS << "<fi#" << getIndex() << ">";
208 case MachineOperand::MO_ConstantPoolIndex:
209 OS << "<cp#" << getIndex();
210 if (getOffset()) OS << "+" << getOffset();
213 case MachineOperand::MO_JumpTableIndex:
214 OS << "<jt#" << getIndex() << ">";
216 case MachineOperand::MO_GlobalAddress:
217 OS << "<ga:" << ((Value*)getGlobal())->getName();
218 if (getOffset()) OS << "+" << getOffset();
221 case MachineOperand::MO_ExternalSymbol:
222 OS << "<es:" << getSymbolName();
223 if (getOffset()) OS << "+" << getOffset();
227 assert(0 && "Unrecognized operand type");
231 //===----------------------------------------------------------------------===//
232 // MachineInstr Implementation
233 //===----------------------------------------------------------------------===//
235 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
236 /// TID NULL and no operands.
237 MachineInstr::MachineInstr()
238 : TID(0), NumImplicitOps(0), Parent(0) {
239 // Make sure that we get added to a machine basicblock
240 LeakDetector::addGarbageObject(this);
243 void MachineInstr::addImplicitDefUseOperands() {
244 if (TID->ImplicitDefs)
245 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
246 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
247 if (TID->ImplicitUses)
248 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
249 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
252 /// MachineInstr ctor - This constructor create a MachineInstr and add the
253 /// implicit operands. It reserves space for number of operands specified by
254 /// TargetInstrDesc or the numOperands if it is not zero. (for
255 /// instructions with variable number of operands).
256 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
257 : TID(&tid), NumImplicitOps(0), Parent(0) {
258 if (!NoImp && TID->getImplicitDefs())
259 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
261 if (!NoImp && TID->getImplicitUses())
262 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
264 Operands.reserve(NumImplicitOps + TID->getNumOperands());
266 addImplicitDefUseOperands();
267 // Make sure that we get added to a machine basicblock
268 LeakDetector::addGarbageObject(this);
271 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
272 /// MachineInstr is created and added to the end of the specified basic block.
274 MachineInstr::MachineInstr(MachineBasicBlock *MBB,
275 const TargetInstrDesc &tid)
276 : TID(&tid), NumImplicitOps(0), Parent(0) {
277 assert(MBB && "Cannot use inserting ctor with null basic block!");
278 if (TID->ImplicitDefs)
279 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
281 if (TID->ImplicitUses)
282 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
284 Operands.reserve(NumImplicitOps + TID->getNumOperands());
285 addImplicitDefUseOperands();
286 // Make sure that we get added to a machine basicblock
287 LeakDetector::addGarbageObject(this);
288 MBB->push_back(this); // Add instruction to end of basic block!
291 /// MachineInstr ctor - Copies MachineInstr arg exactly
293 MachineInstr::MachineInstr(const MachineInstr &MI) {
295 NumImplicitOps = MI.NumImplicitOps;
296 Operands.reserve(MI.getNumOperands());
297 MemOperands = MI.MemOperands;
300 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
301 Operands.push_back(MI.getOperand(i));
302 Operands.back().ParentMI = this;
305 // Set parent, next, and prev to null
312 MachineInstr::~MachineInstr() {
313 LeakDetector::removeGarbageObject(this);
315 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
316 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
317 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
318 "Reg operand def/use list corrupted");
323 /// getOpcode - Returns the opcode of this MachineInstr.
325 int MachineInstr::getOpcode() const {
329 /// getRegInfo - If this instruction is embedded into a MachineFunction,
330 /// return the MachineRegisterInfo object for the current function, otherwise
332 MachineRegisterInfo *MachineInstr::getRegInfo() {
333 if (MachineBasicBlock *MBB = getParent())
334 if (MachineFunction *MF = MBB->getParent())
335 return &MF->getRegInfo();
339 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
340 /// this instruction from their respective use lists. This requires that the
341 /// operands already be on their use lists.
342 void MachineInstr::RemoveRegOperandsFromUseLists() {
343 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
344 if (Operands[i].isReg())
345 Operands[i].RemoveRegOperandFromRegInfo();
349 /// AddRegOperandsToUseLists - Add all of the register operands in
350 /// this instruction from their respective use lists. This requires that the
351 /// operands not be on their use lists yet.
352 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
353 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
354 if (Operands[i].isReg())
355 Operands[i].AddRegOperandToRegInfo(&RegInfo);
360 /// addOperand - Add the specified operand to the instruction. If it is an
361 /// implicit operand, it is added to the end of the operand list. If it is
362 /// an explicit operand it is added at the end of the explicit operand list
363 /// (before the first implicit operand).
364 void MachineInstr::addOperand(const MachineOperand &Op) {
365 bool isImpReg = Op.isReg() && Op.isImplicit();
366 assert((isImpReg || !OperandsComplete()) &&
367 "Trying to add an operand to a machine instr that is already done!");
369 // If we are adding the operand to the end of the list, our job is simpler.
370 // This is true most of the time, so this is a reasonable optimization.
371 if (isImpReg || NumImplicitOps == 0) {
372 // We can only do this optimization if we know that the operand list won't
374 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
375 Operands.push_back(Op);
377 // Set the parent of the operand.
378 Operands.back().ParentMI = this;
380 // If the operand is a register, update the operand's use list.
382 Operands.back().AddRegOperandToRegInfo(getRegInfo());
387 // Otherwise, we have to insert a real operand before any implicit ones.
388 unsigned OpNo = Operands.size()-NumImplicitOps;
390 MachineRegisterInfo *RegInfo = getRegInfo();
392 // If this instruction isn't embedded into a function, then we don't need to
393 // update any operand lists.
395 // Simple insertion, no reginfo update needed for other register operands.
396 Operands.insert(Operands.begin()+OpNo, Op);
397 Operands[OpNo].ParentMI = this;
399 // Do explicitly set the reginfo for this operand though, to ensure the
400 // next/prev fields are properly nulled out.
401 if (Operands[OpNo].isReg())
402 Operands[OpNo].AddRegOperandToRegInfo(0);
404 } else if (Operands.size()+1 <= Operands.capacity()) {
405 // Otherwise, we have to remove register operands from their register use
406 // list, add the operand, then add the register operands back to their use
407 // list. This also must handle the case when the operand list reallocates
408 // to somewhere else.
410 // If insertion of this operand won't cause reallocation of the operand
411 // list, just remove the implicit operands, add the operand, then re-add all
412 // the rest of the operands.
413 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
414 assert(Operands[i].isReg() && "Should only be an implicit reg!");
415 Operands[i].RemoveRegOperandFromRegInfo();
418 // Add the operand. If it is a register, add it to the reg list.
419 Operands.insert(Operands.begin()+OpNo, Op);
420 Operands[OpNo].ParentMI = this;
422 if (Operands[OpNo].isReg())
423 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
425 // Re-add all the implicit ops.
426 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
427 assert(Operands[i].isReg() && "Should only be an implicit reg!");
428 Operands[i].AddRegOperandToRegInfo(RegInfo);
431 // Otherwise, we will be reallocating the operand list. Remove all reg
432 // operands from their list, then readd them after the operand list is
434 RemoveRegOperandsFromUseLists();
436 Operands.insert(Operands.begin()+OpNo, Op);
437 Operands[OpNo].ParentMI = this;
439 // Re-add all the operands.
440 AddRegOperandsToUseLists(*RegInfo);
444 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
445 /// fewer operand than it started with.
447 void MachineInstr::RemoveOperand(unsigned OpNo) {
448 assert(OpNo < Operands.size() && "Invalid operand number");
450 // Special case removing the last one.
451 if (OpNo == Operands.size()-1) {
452 // If needed, remove from the reg def/use list.
453 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
454 Operands.back().RemoveRegOperandFromRegInfo();
460 // Otherwise, we are removing an interior operand. If we have reginfo to
461 // update, remove all operands that will be shifted down from their reg lists,
462 // move everything down, then re-add them.
463 MachineRegisterInfo *RegInfo = getRegInfo();
465 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
466 if (Operands[i].isReg())
467 Operands[i].RemoveRegOperandFromRegInfo();
471 Operands.erase(Operands.begin()+OpNo);
474 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
475 if (Operands[i].isReg())
476 Operands[i].AddRegOperandToRegInfo(RegInfo);
482 /// removeFromParent - This method unlinks 'this' from the containing basic
483 /// block, and returns it, but does not delete it.
484 MachineInstr *MachineInstr::removeFromParent() {
485 assert(getParent() && "Not embedded in a basic block!");
486 getParent()->remove(this);
491 /// OperandComplete - Return true if it's illegal to add a new operand
493 bool MachineInstr::OperandsComplete() const {
494 unsigned short NumOperands = TID->getNumOperands();
495 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
496 return true; // Broken: we have all the operands of this instruction!
500 /// getNumExplicitOperands - Returns the number of non-implicit operands.
502 unsigned MachineInstr::getNumExplicitOperands() const {
503 unsigned NumOperands = TID->getNumOperands();
504 if (!TID->isVariadic())
507 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
508 const MachineOperand &MO = getOperand(NumOperands);
509 if (!MO.isRegister() || !MO.isImplicit())
516 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
518 bool MachineInstr::isDebugLabel() const {
519 return getOpcode() == TargetInstrInfo::LABEL && getOperand(1).getImm() == 0;
522 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
523 /// the specific register or -1 if it is not found. It further tightening
524 /// the search criteria to a use that kills the register if isKill is true.
525 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
526 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
527 const MachineOperand &MO = getOperand(i);
528 if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
529 if (!isKill || MO.isKill())
535 /// findRegisterDefOperand() - Returns the MachineOperand that is a def of
536 /// the specific register or NULL if it is not found.
537 MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
538 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
539 MachineOperand &MO = getOperand(i);
540 if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
546 /// findFirstPredOperandIdx() - Find the index of the first operand in the
547 /// operand list that is used to represent the predicate. It returns -1 if
549 int MachineInstr::findFirstPredOperandIdx() const {
550 const TargetInstrDesc &TID = getDesc();
551 if (TID.isPredicable()) {
552 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
553 if (TID.OpInfo[i].isPredicate())
560 /// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
561 /// to two addr elimination.
562 bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
563 const TargetInstrDesc &TID = getDesc();
564 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
565 const MachineOperand &MO1 = getOperand(i);
566 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
567 for (unsigned j = i+1; j < e; ++j) {
568 const MachineOperand &MO2 = getOperand(j);
569 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
570 TID.getOperandConstraint(j, TOI::TIED_TO) == (int)i)
578 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
580 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
581 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
582 const MachineOperand &MO = MI->getOperand(i);
583 if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
585 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
586 MachineOperand &MOp = getOperand(j);
587 if (!MOp.isIdenticalTo(MO))
598 /// copyPredicates - Copies predicate operand(s) from MI.
599 void MachineInstr::copyPredicates(const MachineInstr *MI) {
600 const TargetInstrDesc &TID = MI->getDesc();
601 if (TID.isPredicable()) {
602 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
603 if (TID.OpInfo[i].isPredicate()) {
604 // Predicated operands must be last operands.
605 addOperand(MI->getOperand(i));
611 void MachineInstr::dump() const {
612 cerr << " " << *this;
615 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
616 // Specialize printing if op#0 is definition
617 unsigned StartOp = 0;
618 if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
619 getOperand(0).print(OS, TM);
621 ++StartOp; // Don't print this operand again!
624 OS << getDesc().getName();
626 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
630 getOperand(i).print(OS, TM);
633 if (getNumMemOperands() > 0) {
635 for (unsigned i = 0; i < getNumMemOperands(); i++) {
636 const MemOperand &MRO = getMemOperand(i);
637 const Value *V = MRO.getValue();
639 assert(V && "SV missing.");
640 assert((MRO.isLoad() || MRO.isStore()) &&
641 "SV has to be a load, store or both.");
643 if (MRO.isVolatile())
652 if (!V->getName().empty())
653 OS << "[" << V->getName() << " + " << MRO.getOffset() << "]";
654 else if (isa<PseudoSourceValue>(V))
655 OS << "[" << *V << " + " << MRO.getOffset() << "]";
657 OS << "[" << V << " + " << MRO.getOffset() << "]";
664 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
665 const MRegisterInfo *RegInfo,
666 bool AddIfNotFound) {
668 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
669 MachineOperand &MO = getOperand(i);
670 if (MO.isRegister() && MO.isUse()) {
671 unsigned Reg = MO.getReg();
674 if (Reg == IncomingReg) {
678 } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
679 MRegisterInfo::isPhysicalRegister(IncomingReg) &&
680 RegInfo->isSuperRegister(IncomingReg, Reg) &&
682 // A super-register kill already exists.
687 // If not found, this means an alias of one of the operand is killed. Add a
688 // new implicit operand if required.
689 if (!Found && AddIfNotFound) {
690 addOperand(MachineOperand::CreateReg(IncomingReg, false/*IsDef*/,
691 true/*IsImp*/,true/*IsKill*/));
697 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
698 const MRegisterInfo *RegInfo,
699 bool AddIfNotFound) {
701 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
702 MachineOperand &MO = getOperand(i);
703 if (MO.isRegister() && MO.isDef()) {
704 unsigned Reg = MO.getReg();
707 if (Reg == IncomingReg) {
711 } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
712 MRegisterInfo::isPhysicalRegister(IncomingReg) &&
713 RegInfo->isSuperRegister(IncomingReg, Reg) &&
715 // There exists a super-register that's marked dead.
720 // If not found, this means an alias of one of the operand is dead. Add a
721 // new implicit operand.
722 if (!Found && AddIfNotFound) {
723 addOperand(MachineOperand::CreateReg(IncomingReg, true/*IsDef*/,
724 true/*IsImp*/,false/*IsKill*/,
731 /// copyKillDeadInfo - copies killed/dead information from one instr to another
732 void MachineInstr::copyKillDeadInfo(MachineInstr *OldMI,
733 const MRegisterInfo *RegInfo) {
734 // If the instruction defines any virtual registers, update the VarInfo,
735 // kill and dead information for the instruction.
736 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
737 MachineOperand &MO = OldMI->getOperand(i);
738 if (MO.isRegister() && MO.getReg() &&
739 MRegisterInfo::isVirtualRegister(MO.getReg())) {
740 unsigned Reg = MO.getReg();
744 addRegisterDead(Reg, RegInfo);
749 addRegisterKilled(Reg, RegInfo);