1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/ADT/FoldingSet.h"
16 #include "llvm/ADT/Hashing.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/Assembly/Writer.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/Constants.h"
26 #include "llvm/DebugInfo.h"
27 #include "llvm/Function.h"
28 #include "llvm/InlineAsm.h"
29 #include "llvm/LLVMContext.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCSymbol.h"
32 #include "llvm/Metadata.h"
33 #include "llvm/Module.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/LeakDetector.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Target/TargetRegisterInfo.h"
42 #include "llvm/Type.h"
43 #include "llvm/Value.h"
46 //===----------------------------------------------------------------------===//
47 // MachineOperand Implementation
48 //===----------------------------------------------------------------------===//
50 void MachineOperand::setReg(unsigned Reg) {
51 if (getReg() == Reg) return; // No change.
53 // Otherwise, we have to change the register. If this operand is embedded
54 // into a machine function, we need to update the old and new register's
56 if (MachineInstr *MI = getParent())
57 if (MachineBasicBlock *MBB = MI->getParent())
58 if (MachineFunction *MF = MBB->getParent()) {
59 MachineRegisterInfo &MRI = MF->getRegInfo();
60 MRI.removeRegOperandFromUseList(this);
61 SmallContents.RegNo = Reg;
62 MRI.addRegOperandToUseList(this);
66 // Otherwise, just change the register, no problem. :)
67 SmallContents.RegNo = Reg;
70 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
71 const TargetRegisterInfo &TRI) {
72 assert(TargetRegisterInfo::isVirtualRegister(Reg));
73 if (SubIdx && getSubReg())
74 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
80 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
81 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
83 Reg = TRI.getSubReg(Reg, getSubReg());
84 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
85 // That won't happen in legal code.
91 /// Change a def to a use, or a use to a def.
92 void MachineOperand::setIsDef(bool Val) {
93 assert(isReg() && "Wrong MachineOperand accessor");
94 assert((!Val || !isDebug()) && "Marking a debug operation as def");
97 // MRI may keep uses and defs in different list positions.
98 if (MachineInstr *MI = getParent())
99 if (MachineBasicBlock *MBB = MI->getParent())
100 if (MachineFunction *MF = MBB->getParent()) {
101 MachineRegisterInfo &MRI = MF->getRegInfo();
102 MRI.removeRegOperandFromUseList(this);
104 MRI.addRegOperandToUseList(this);
110 /// ChangeToImmediate - Replace this operand with a new immediate operand of
111 /// the specified value. If an operand is known to be an immediate already,
112 /// the setImm method should be used.
113 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
114 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
115 // If this operand is currently a register operand, and if this is in a
116 // function, deregister the operand from the register's use/def list.
117 if (isReg() && isOnRegUseList())
118 if (MachineInstr *MI = getParent())
119 if (MachineBasicBlock *MBB = MI->getParent())
120 if (MachineFunction *MF = MBB->getParent())
121 MF->getRegInfo().removeRegOperandFromUseList(this);
123 OpKind = MO_Immediate;
124 Contents.ImmVal = ImmVal;
127 /// ChangeToRegister - Replace this operand with a new register operand of
128 /// the specified value. If an operand is known to be an register already,
129 /// the setReg method should be used.
130 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
131 bool isKill, bool isDead, bool isUndef,
133 MachineRegisterInfo *RegInfo = 0;
134 if (MachineInstr *MI = getParent())
135 if (MachineBasicBlock *MBB = MI->getParent())
136 if (MachineFunction *MF = MBB->getParent())
137 RegInfo = &MF->getRegInfo();
138 // If this operand is already a register operand, remove it from the
139 // register's use/def lists.
140 bool WasReg = isReg();
141 if (RegInfo && WasReg)
142 RegInfo->removeRegOperandFromUseList(this);
144 // Change this to a register and set the reg#.
145 OpKind = MO_Register;
146 SmallContents.RegNo = Reg;
153 IsInternalRead = false;
154 IsEarlyClobber = false;
156 // Ensure isOnRegUseList() returns false.
157 Contents.Reg.Prev = 0;
158 // Preserve the tie when the operand was already a register.
162 // If this operand is embedded in a function, add the operand to the
163 // register's use/def list.
165 RegInfo->addRegOperandToUseList(this);
168 /// isIdenticalTo - Return true if this operand is identical to the specified
169 /// operand. Note that this should stay in sync with the hash_value overload
171 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
172 if (getType() != Other.getType() ||
173 getTargetFlags() != Other.getTargetFlags())
177 case MachineOperand::MO_Register:
178 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
179 getSubReg() == Other.getSubReg();
180 case MachineOperand::MO_Immediate:
181 return getImm() == Other.getImm();
182 case MachineOperand::MO_CImmediate:
183 return getCImm() == Other.getCImm();
184 case MachineOperand::MO_FPImmediate:
185 return getFPImm() == Other.getFPImm();
186 case MachineOperand::MO_MachineBasicBlock:
187 return getMBB() == Other.getMBB();
188 case MachineOperand::MO_FrameIndex:
189 return getIndex() == Other.getIndex();
190 case MachineOperand::MO_ConstantPoolIndex:
191 case MachineOperand::MO_TargetIndex:
192 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
193 case MachineOperand::MO_JumpTableIndex:
194 return getIndex() == Other.getIndex();
195 case MachineOperand::MO_GlobalAddress:
196 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
197 case MachineOperand::MO_ExternalSymbol:
198 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
199 getOffset() == Other.getOffset();
200 case MachineOperand::MO_BlockAddress:
201 return getBlockAddress() == Other.getBlockAddress() &&
202 getOffset() == Other.getOffset();
203 case MO_RegisterMask:
204 return getRegMask() == Other.getRegMask();
205 case MachineOperand::MO_MCSymbol:
206 return getMCSymbol() == Other.getMCSymbol();
207 case MachineOperand::MO_Metadata:
208 return getMetadata() == Other.getMetadata();
210 llvm_unreachable("Invalid machine operand type");
213 // Note: this must stay exactly in sync with isIdenticalTo above.
214 hash_code llvm::hash_value(const MachineOperand &MO) {
215 switch (MO.getType()) {
216 case MachineOperand::MO_Register:
217 // Register operands don't have target flags.
218 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
219 case MachineOperand::MO_Immediate:
220 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
221 case MachineOperand::MO_CImmediate:
222 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
223 case MachineOperand::MO_FPImmediate:
224 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
225 case MachineOperand::MO_MachineBasicBlock:
226 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
227 case MachineOperand::MO_FrameIndex:
228 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
229 case MachineOperand::MO_ConstantPoolIndex:
230 case MachineOperand::MO_TargetIndex:
231 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
233 case MachineOperand::MO_JumpTableIndex:
234 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
235 case MachineOperand::MO_ExternalSymbol:
236 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
238 case MachineOperand::MO_GlobalAddress:
239 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
241 case MachineOperand::MO_BlockAddress:
242 return hash_combine(MO.getType(), MO.getTargetFlags(),
243 MO.getBlockAddress(), MO.getOffset());
244 case MachineOperand::MO_RegisterMask:
245 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
246 case MachineOperand::MO_Metadata:
247 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
248 case MachineOperand::MO_MCSymbol:
249 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
251 llvm_unreachable("Invalid machine operand type");
254 /// print - Print the specified machine operand.
256 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
257 // If the instruction is embedded into a basic block, we can find the
258 // target info for the instruction.
260 if (const MachineInstr *MI = getParent())
261 if (const MachineBasicBlock *MBB = MI->getParent())
262 if (const MachineFunction *MF = MBB->getParent())
263 TM = &MF->getTarget();
264 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
267 case MachineOperand::MO_Register:
268 OS << PrintReg(getReg(), TRI, getSubReg());
270 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
271 isInternalRead() || isEarlyClobber() || isTied()) {
273 bool NeedComma = false;
275 if (NeedComma) OS << ',';
276 if (isEarlyClobber())
277 OS << "earlyclobber,";
282 // <def,read-undef> only makes sense when getSubReg() is set.
283 // Don't clutter the output otherwise.
284 if (isUndef() && getSubReg())
286 } else if (isImplicit()) {
292 if (NeedComma) OS << ',';
297 if (NeedComma) OS << ',';
301 if (isUndef() && isUse()) {
302 if (NeedComma) OS << ',';
306 if (isInternalRead()) {
307 if (NeedComma) OS << ',';
312 if (NeedComma) OS << ',';
315 OS << unsigned(TiedTo - 1);
321 case MachineOperand::MO_Immediate:
324 case MachineOperand::MO_CImmediate:
325 getCImm()->getValue().print(OS, false);
327 case MachineOperand::MO_FPImmediate:
328 if (getFPImm()->getType()->isFloatTy())
329 OS << getFPImm()->getValueAPF().convertToFloat();
331 OS << getFPImm()->getValueAPF().convertToDouble();
333 case MachineOperand::MO_MachineBasicBlock:
334 OS << "<BB#" << getMBB()->getNumber() << ">";
336 case MachineOperand::MO_FrameIndex:
337 OS << "<fi#" << getIndex() << '>';
339 case MachineOperand::MO_ConstantPoolIndex:
340 OS << "<cp#" << getIndex();
341 if (getOffset()) OS << "+" << getOffset();
344 case MachineOperand::MO_TargetIndex:
345 OS << "<ti#" << getIndex();
346 if (getOffset()) OS << "+" << getOffset();
349 case MachineOperand::MO_JumpTableIndex:
350 OS << "<jt#" << getIndex() << '>';
352 case MachineOperand::MO_GlobalAddress:
354 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
355 if (getOffset()) OS << "+" << getOffset();
358 case MachineOperand::MO_ExternalSymbol:
359 OS << "<es:" << getSymbolName();
360 if (getOffset()) OS << "+" << getOffset();
363 case MachineOperand::MO_BlockAddress:
365 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
366 if (getOffset()) OS << "+" << getOffset();
369 case MachineOperand::MO_RegisterMask:
372 case MachineOperand::MO_Metadata:
374 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
377 case MachineOperand::MO_MCSymbol:
378 OS << "<MCSym=" << *getMCSymbol() << '>';
382 if (unsigned TF = getTargetFlags())
383 OS << "[TF=" << TF << ']';
386 //===----------------------------------------------------------------------===//
387 // MachineMemOperand Implementation
388 //===----------------------------------------------------------------------===//
390 /// getAddrSpace - Return the LLVM IR address space number that this pointer
392 unsigned MachinePointerInfo::getAddrSpace() const {
393 if (V == 0) return 0;
394 return cast<PointerType>(V->getType())->getAddressSpace();
397 /// getConstantPool - Return a MachinePointerInfo record that refers to the
399 MachinePointerInfo MachinePointerInfo::getConstantPool() {
400 return MachinePointerInfo(PseudoSourceValue::getConstantPool());
403 /// getFixedStack - Return a MachinePointerInfo record that refers to the
404 /// the specified FrameIndex.
405 MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
406 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
409 MachinePointerInfo MachinePointerInfo::getJumpTable() {
410 return MachinePointerInfo(PseudoSourceValue::getJumpTable());
413 MachinePointerInfo MachinePointerInfo::getGOT() {
414 return MachinePointerInfo(PseudoSourceValue::getGOT());
417 MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
418 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
421 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
422 uint64_t s, unsigned int a,
423 const MDNode *TBAAInfo,
424 const MDNode *Ranges)
425 : PtrInfo(ptrinfo), Size(s),
426 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
427 TBAAInfo(TBAAInfo), Ranges(Ranges) {
428 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
429 "invalid pointer value");
430 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
431 assert((isLoad() || isStore()) && "Not a load/store!");
434 /// Profile - Gather unique data for the object.
436 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
437 ID.AddInteger(getOffset());
439 ID.AddPointer(getValue());
440 ID.AddInteger(Flags);
443 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
444 // The Value and Offset may differ due to CSE. But the flags and size
445 // should be the same.
446 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
447 assert(MMO->getSize() == getSize() && "Size mismatch!");
449 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
450 // Update the alignment value.
451 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
452 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
453 // Also update the base and offset, because the new alignment may
454 // not be applicable with the old ones.
455 PtrInfo = MMO->PtrInfo;
459 /// getAlignment - Return the minimum known alignment in bytes of the
460 /// actual memory reference.
461 uint64_t MachineMemOperand::getAlignment() const {
462 return MinAlign(getBaseAlignment(), getOffset());
465 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
466 assert((MMO.isLoad() || MMO.isStore()) &&
467 "SV has to be a load, store or both.");
469 if (MMO.isVolatile())
478 // Print the address information.
483 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
485 // If the alignment of the memory reference itself differs from the alignment
486 // of the base pointer, print the base alignment explicitly, next to the base
488 if (MMO.getBaseAlignment() != MMO.getAlignment())
489 OS << "(align=" << MMO.getBaseAlignment() << ")";
491 if (MMO.getOffset() != 0)
492 OS << "+" << MMO.getOffset();
495 // Print the alignment of the reference.
496 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
497 MMO.getBaseAlignment() != MMO.getSize())
498 OS << "(align=" << MMO.getAlignment() << ")";
501 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
503 if (TBAAInfo->getNumOperands() > 0)
504 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
510 // Print nontemporal info.
511 if (MMO.isNonTemporal())
512 OS << "(nontemporal)";
517 //===----------------------------------------------------------------------===//
518 // MachineInstr Implementation
519 //===----------------------------------------------------------------------===//
521 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
522 if (MCID->ImplicitDefs)
523 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
524 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
525 if (MCID->ImplicitUses)
526 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
527 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
530 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
531 /// implicit operands. It reserves space for the number of operands specified by
533 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
534 const DebugLoc dl, bool NoImp)
535 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
536 NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) {
537 unsigned NumImplicitOps = 0;
539 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
540 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
542 addImplicitDefUseOperands(MF);
543 // Make sure that we get added to a machine basicblock
544 LeakDetector::addGarbageObject(this);
547 /// MachineInstr ctor - Copies MachineInstr arg exactly
549 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
550 : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0),
551 NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
552 Parent(0), debugLoc(MI.getDebugLoc()) {
553 Operands.reserve(MI.getNumOperands());
556 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
557 addOperand(MF, MI.getOperand(i));
559 // Copy all the sensible flags.
562 // Set parent to null.
565 LeakDetector::addGarbageObject(this);
568 MachineInstr::~MachineInstr() {
569 LeakDetector::removeGarbageObject(this);
571 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
572 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
573 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
574 "Reg operand def/use list corrupted");
579 /// getRegInfo - If this instruction is embedded into a MachineFunction,
580 /// return the MachineRegisterInfo object for the current function, otherwise
582 MachineRegisterInfo *MachineInstr::getRegInfo() {
583 if (MachineBasicBlock *MBB = getParent())
584 return &MBB->getParent()->getRegInfo();
588 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
589 /// this instruction from their respective use lists. This requires that the
590 /// operands already be on their use lists.
591 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
592 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
593 if (Operands[i].isReg())
594 MRI.removeRegOperandFromUseList(&Operands[i]);
597 /// AddRegOperandsToUseLists - Add all of the register operands in
598 /// this instruction from their respective use lists. This requires that the
599 /// operands not be on their use lists yet.
600 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
601 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
602 if (Operands[i].isReg())
603 MRI.addRegOperandToUseList(&Operands[i]);
606 /// addOperand - Add the specified operand to the instruction. If it is an
607 /// implicit operand, it is added to the end of the operand list. If it is
608 /// an explicit operand it is added at the end of the explicit operand list
609 /// (before the first implicit operand).
610 void MachineInstr::addOperand(const MachineOperand &Op) {
611 assert(MCID && "Cannot add operands before providing an instr descriptor");
612 bool isImpReg = Op.isReg() && Op.isImplicit();
613 MachineRegisterInfo *RegInfo = getRegInfo();
615 // If the Operands backing store is reallocated, all register operands must
616 // be removed and re-added to RegInfo. It is storing pointers to operands.
617 bool Reallocate = RegInfo &&
618 !Operands.empty() && Operands.size() == Operands.capacity();
620 // Find the insert location for the new operand. Implicit registers go at
621 // the end, everything goes before the implicit regs.
622 unsigned OpNo = Operands.size();
624 // Remove all the implicit operands from RegInfo if they need to be shifted.
625 // FIXME: Allow mixed explicit and implicit operands on inline asm.
626 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
627 // implicit-defs, but they must not be moved around. See the FIXME in
629 if (!isImpReg && !isInlineAsm()) {
630 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
632 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
634 RegInfo->removeRegOperandFromUseList(&Operands[OpNo]);
638 // OpNo now points as the desired insertion point. Unless this is a variadic
639 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
640 // RegMask operands go between the explicit and implicit operands.
641 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
642 OpNo < MCID->getNumOperands()) &&
643 "Trying to add an operand to a machine instr that is already done!");
645 // All operands from OpNo have been removed from RegInfo. If the Operands
646 // backing store needs to be reallocated, we also need to remove any other
647 // register operands.
649 for (unsigned i = 0; i != OpNo; ++i)
650 if (Operands[i].isReg())
651 RegInfo->removeRegOperandFromUseList(&Operands[i]);
653 // Insert the new operand at OpNo.
654 Operands.insert(Operands.begin() + OpNo, Op);
655 Operands[OpNo].ParentMI = this;
657 // The Operands backing store has now been reallocated, so we can re-add the
658 // operands before OpNo.
660 for (unsigned i = 0; i != OpNo; ++i)
661 if (Operands[i].isReg())
662 RegInfo->addRegOperandToUseList(&Operands[i]);
664 // When adding a register operand, tell RegInfo about it.
665 if (Operands[OpNo].isReg()) {
666 // Ensure isOnRegUseList() returns false, regardless of Op's status.
667 Operands[OpNo].Contents.Reg.Prev = 0;
668 // Ignore existing ties. This is not a property that can be copied.
669 Operands[OpNo].TiedTo = 0;
670 // Add the new operand to RegInfo.
672 RegInfo->addRegOperandToUseList(&Operands[OpNo]);
673 // The MCID operand information isn't accurate until we start adding
674 // explicit operands. The implicit operands are added first, then the
675 // explicits are inserted before them.
677 // Tie uses to defs as indicated in MCInstrDesc.
678 if (Operands[OpNo].isUse()) {
679 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
681 tieOperands(DefIdx, OpNo);
683 // If the register operand is flagged as early, mark the operand as such.
684 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
685 Operands[OpNo].setIsEarlyClobber(true);
689 // Re-add all the implicit ops.
691 for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) {
692 assert(Operands[i].isReg() && "Should only be an implicit reg!");
693 RegInfo->addRegOperandToUseList(&Operands[i]);
698 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
699 /// fewer operand than it started with.
701 void MachineInstr::RemoveOperand(unsigned OpNo) {
702 assert(OpNo < Operands.size() && "Invalid operand number");
703 untieRegOperand(OpNo);
704 MachineRegisterInfo *RegInfo = getRegInfo();
706 // Special case removing the last one.
707 if (OpNo == Operands.size()-1) {
708 // If needed, remove from the reg def/use list.
709 if (RegInfo && Operands.back().isReg() && Operands.back().isOnRegUseList())
710 RegInfo->removeRegOperandFromUseList(&Operands.back());
716 // Otherwise, we are removing an interior operand. If we have reginfo to
717 // update, remove all operands that will be shifted down from their reg lists,
718 // move everything down, then re-add them.
720 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
721 if (Operands[i].isReg())
722 RegInfo->removeRegOperandFromUseList(&Operands[i]);
727 // Moving tied operands would break the ties.
728 for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i)
729 if (Operands[i].isReg())
730 assert(!Operands[i].isTied() && "Cannot move tied operands");
733 Operands.erase(Operands.begin()+OpNo);
736 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
737 if (Operands[i].isReg())
738 RegInfo->addRegOperandToUseList(&Operands[i]);
743 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
744 /// This function should be used only occasionally. The setMemRefs function
745 /// is the primary method for setting up a MachineInstr's MemRefs list.
746 void MachineInstr::addMemOperand(MachineFunction &MF,
747 MachineMemOperand *MO) {
748 mmo_iterator OldMemRefs = MemRefs;
749 uint16_t OldNumMemRefs = NumMemRefs;
751 uint16_t NewNum = NumMemRefs + 1;
752 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
754 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
755 NewMemRefs[NewNum - 1] = MO;
757 MemRefs = NewMemRefs;
761 bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
762 const MachineBasicBlock *MBB = getParent();
763 MachineBasicBlock::const_instr_iterator MII = *this; ++MII;
764 while (MII != MBB->end() && MII->isInsideBundle()) {
765 if (MII->getDesc().getFlags() & Mask) {
766 if (Type == AnyInBundle)
769 if (Type == AllInBundle)
775 return Type == AllInBundle;
778 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
779 MICheckType Check) const {
780 // If opcodes or number of operands are not the same then the two
781 // instructions are obviously not identical.
782 if (Other->getOpcode() != getOpcode() ||
783 Other->getNumOperands() != getNumOperands())
787 // Both instructions are bundles, compare MIs inside the bundle.
788 MachineBasicBlock::const_instr_iterator I1 = *this;
789 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
790 MachineBasicBlock::const_instr_iterator I2 = *Other;
791 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
792 while (++I1 != E1 && I1->isInsideBundle()) {
794 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
799 // Check operands to make sure they match.
800 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
801 const MachineOperand &MO = getOperand(i);
802 const MachineOperand &OMO = Other->getOperand(i);
804 if (!MO.isIdenticalTo(OMO))
809 // Clients may or may not want to ignore defs when testing for equality.
810 // For example, machine CSE pass only cares about finding common
811 // subexpressions, so it's safe to ignore virtual register defs.
813 if (Check == IgnoreDefs)
815 else if (Check == IgnoreVRegDefs) {
816 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
817 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
818 if (MO.getReg() != OMO.getReg())
821 if (!MO.isIdenticalTo(OMO))
823 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
827 if (!MO.isIdenticalTo(OMO))
829 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
833 // If DebugLoc does not match then two dbg.values are not identical.
835 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
836 && getDebugLoc() != Other->getDebugLoc())
841 MachineInstr *MachineInstr::removeFromParent() {
842 assert(getParent() && "Not embedded in a basic block!");
843 return getParent()->remove(this);
846 MachineInstr *MachineInstr::removeFromBundle() {
847 assert(getParent() && "Not embedded in a basic block!");
848 return getParent()->remove_instr(this);
851 void MachineInstr::eraseFromParent() {
852 assert(getParent() && "Not embedded in a basic block!");
853 getParent()->erase(this);
856 void MachineInstr::eraseFromBundle() {
857 assert(getParent() && "Not embedded in a basic block!");
858 getParent()->erase_instr(this);
861 /// getNumExplicitOperands - Returns the number of non-implicit operands.
863 unsigned MachineInstr::getNumExplicitOperands() const {
864 unsigned NumOperands = MCID->getNumOperands();
865 if (!MCID->isVariadic())
868 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
869 const MachineOperand &MO = getOperand(i);
870 if (!MO.isReg() || !MO.isImplicit())
876 void MachineInstr::bundleWithPred() {
877 assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
878 setFlag(BundledPred);
879 MachineBasicBlock::instr_iterator Pred = this;
881 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
882 Pred->setFlag(BundledSucc);
885 void MachineInstr::bundleWithSucc() {
886 assert(!isBundledWithSucc() && "MI is already bundled with its successor");
887 setFlag(BundledSucc);
888 MachineBasicBlock::instr_iterator Succ = this;
890 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
891 Succ->setFlag(BundledPred);
894 void MachineInstr::unbundleFromPred() {
895 assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
896 clearFlag(BundledPred);
897 MachineBasicBlock::instr_iterator Pred = this;
899 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
900 Pred->clearFlag(BundledSucc);
903 void MachineInstr::unbundleFromSucc() {
904 assert(isBundledWithSucc() && "MI isn't bundled with its successor");
905 clearFlag(BundledSucc);
906 MachineBasicBlock::instr_iterator Succ = this;
908 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
909 Succ->clearFlag(BundledPred);
912 bool MachineInstr::isStackAligningInlineAsm() const {
914 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
915 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
921 InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
922 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
923 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
924 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
927 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
928 unsigned *GroupNo) const {
929 assert(isInlineAsm() && "Expected an inline asm instruction");
930 assert(OpIdx < getNumOperands() && "OpIdx out of range");
932 // Ignore queries about the initial operands.
933 if (OpIdx < InlineAsm::MIOp_FirstOperand)
938 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
940 const MachineOperand &FlagMO = getOperand(i);
941 // If we reach the implicit register operands, stop looking.
944 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
945 if (i + NumOps > OpIdx) {
955 const TargetRegisterClass*
956 MachineInstr::getRegClassConstraint(unsigned OpIdx,
957 const TargetInstrInfo *TII,
958 const TargetRegisterInfo *TRI) const {
959 assert(getParent() && "Can't have an MBB reference here!");
960 assert(getParent()->getParent() && "Can't have an MF reference here!");
961 const MachineFunction &MF = *getParent()->getParent();
963 // Most opcodes have fixed constraints in their MCInstrDesc.
965 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
967 if (!getOperand(OpIdx).isReg())
970 // For tied uses on inline asm, get the constraint from the def.
972 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
975 // Inline asm stores register class constraints in the flag word.
976 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
980 unsigned Flag = getOperand(FlagIdx).getImm();
982 if (InlineAsm::hasRegClassConstraint(Flag, RCID))
983 return TRI->getRegClass(RCID);
985 // Assume that all registers in a memory operand are pointers.
986 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
987 return TRI->getPointerRegClass(MF);
992 /// getBundleSize - Return the number of instructions inside the MI bundle.
993 unsigned MachineInstr::getBundleSize() const {
994 assert(isBundle() && "Expecting a bundle");
996 const MachineBasicBlock *MBB = getParent();
997 MachineBasicBlock::const_instr_iterator I = *this, E = MBB->instr_end();
999 while ((++I != E) && I->isInsideBundle()) {
1002 assert(Size > 1 && "Malformed bundle");
1007 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1008 /// the specific register or -1 if it is not found. It further tightens
1009 /// the search criteria to a use that kills the register if isKill is true.
1010 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
1011 const TargetRegisterInfo *TRI) const {
1012 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1013 const MachineOperand &MO = getOperand(i);
1014 if (!MO.isReg() || !MO.isUse())
1016 unsigned MOReg = MO.getReg();
1021 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1022 TargetRegisterInfo::isPhysicalRegister(Reg) &&
1023 TRI->isSubRegister(MOReg, Reg)))
1024 if (!isKill || MO.isKill())
1030 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1031 /// indicating if this instruction reads or writes Reg. This also considers
1032 /// partial defines.
1033 std::pair<bool,bool>
1034 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1035 SmallVectorImpl<unsigned> *Ops) const {
1036 bool PartDef = false; // Partial redefine.
1037 bool FullDef = false; // Full define.
1040 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1041 const MachineOperand &MO = getOperand(i);
1042 if (!MO.isReg() || MO.getReg() != Reg)
1047 Use |= !MO.isUndef();
1048 else if (MO.getSubReg() && !MO.isUndef())
1049 // A partial <def,undef> doesn't count as reading the register.
1054 // A partial redefine uses Reg unless there is also a full define.
1055 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1058 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1059 /// the specified register or -1 if it is not found. If isDead is true, defs
1060 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1061 /// also checks if there is a def of a super-register.
1063 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1064 const TargetRegisterInfo *TRI) const {
1065 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1066 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1067 const MachineOperand &MO = getOperand(i);
1068 // Accept regmask operands when Overlap is set.
1069 // Ignore them when looking for a specific def operand (Overlap == false).
1070 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1072 if (!MO.isReg() || !MO.isDef())
1074 unsigned MOReg = MO.getReg();
1075 bool Found = (MOReg == Reg);
1076 if (!Found && TRI && isPhys &&
1077 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1079 Found = TRI->regsOverlap(MOReg, Reg);
1081 Found = TRI->isSubRegister(MOReg, Reg);
1083 if (Found && (!isDead || MO.isDead()))
1089 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1090 /// operand list that is used to represent the predicate. It returns -1 if
1092 int MachineInstr::findFirstPredOperandIdx() const {
1093 // Don't call MCID.findFirstPredOperandIdx() because this variant
1094 // is sometimes called on an instruction that's not yet complete, and
1095 // so the number of operands is less than the MCID indicates. In
1096 // particular, the PTX target does this.
1097 const MCInstrDesc &MCID = getDesc();
1098 if (MCID.isPredicable()) {
1099 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1100 if (MCID.OpInfo[i].isPredicate())
1107 // MachineOperand::TiedTo is 4 bits wide.
1108 const unsigned TiedMax = 15;
1110 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1112 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1113 /// field. TiedTo can have these values:
1115 /// 0: Operand is not tied to anything.
1116 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1117 /// TiedMax: Tied to an operand >= TiedMax-1.
1119 /// The tied def must be one of the first TiedMax operands on a normal
1120 /// instruction. INLINEASM instructions allow more tied defs.
1122 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1123 MachineOperand &DefMO = getOperand(DefIdx);
1124 MachineOperand &UseMO = getOperand(UseIdx);
1125 assert(DefMO.isDef() && "DefIdx must be a def operand");
1126 assert(UseMO.isUse() && "UseIdx must be a use operand");
1127 assert(!DefMO.isTied() && "Def is already tied to another use");
1128 assert(!UseMO.isTied() && "Use is already tied to another def");
1130 if (DefIdx < TiedMax)
1131 UseMO.TiedTo = DefIdx + 1;
1133 // Inline asm can use the group descriptors to find tied operands, but on
1134 // normal instruction, the tied def must be within the first TiedMax
1136 assert(isInlineAsm() && "DefIdx out of range");
1137 UseMO.TiedTo = TiedMax;
1140 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1141 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1144 /// Given the index of a tied register operand, find the operand it is tied to.
1145 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1146 /// which must exist.
1147 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1148 const MachineOperand &MO = getOperand(OpIdx);
1149 assert(MO.isTied() && "Operand isn't tied");
1151 // Normally TiedTo is in range.
1152 if (MO.TiedTo < TiedMax)
1153 return MO.TiedTo - 1;
1155 // Uses on normal instructions can be out of range.
1156 if (!isInlineAsm()) {
1157 // Normal tied defs must be in the 0..TiedMax-1 range.
1160 // MO is a def. Search for the tied use.
1161 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1162 const MachineOperand &UseMO = getOperand(i);
1163 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1166 llvm_unreachable("Can't find tied use");
1169 // Now deal with inline asm by parsing the operand group descriptor flags.
1170 // Find the beginning of each operand group.
1171 SmallVector<unsigned, 8> GroupIdx;
1172 unsigned OpIdxGroup = ~0u;
1174 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1176 const MachineOperand &FlagMO = getOperand(i);
1177 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1178 unsigned CurGroup = GroupIdx.size();
1179 GroupIdx.push_back(i);
1180 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1181 // OpIdx belongs to this operand group.
1182 if (OpIdx > i && OpIdx < i + NumOps)
1183 OpIdxGroup = CurGroup;
1185 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1187 // Operands in this group are tied to operands in TiedGroup which must be
1188 // earlier. Find the number of operands between the two groups.
1189 unsigned Delta = i - GroupIdx[TiedGroup];
1191 // OpIdx is a use tied to TiedGroup.
1192 if (OpIdxGroup == CurGroup)
1193 return OpIdx - Delta;
1195 // OpIdx is a def tied to this use group.
1196 if (OpIdxGroup == TiedGroup)
1197 return OpIdx + Delta;
1199 llvm_unreachable("Invalid tied operand on inline asm");
1202 /// clearKillInfo - Clears kill flags on all operands.
1204 void MachineInstr::clearKillInfo() {
1205 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1206 MachineOperand &MO = getOperand(i);
1207 if (MO.isReg() && MO.isUse())
1208 MO.setIsKill(false);
1212 void MachineInstr::substituteRegister(unsigned FromReg,
1215 const TargetRegisterInfo &RegInfo) {
1216 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1218 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1219 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1220 MachineOperand &MO = getOperand(i);
1221 if (!MO.isReg() || MO.getReg() != FromReg)
1223 MO.substPhysReg(ToReg, RegInfo);
1226 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1227 MachineOperand &MO = getOperand(i);
1228 if (!MO.isReg() || MO.getReg() != FromReg)
1230 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1235 /// isSafeToMove - Return true if it is safe to move this instruction. If
1236 /// SawStore is set to true, it means that there is a store (or call) between
1237 /// the instruction's location and its intended destination.
1238 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1240 bool &SawStore) const {
1241 // Ignore stuff that we obviously can't move.
1243 // Treat volatile loads as stores. This is not strictly necessary for
1244 // volatiles, but it is required for atomic loads. It is not allowed to move
1245 // a load across an atomic load with Ordering > Monotonic.
1246 if (mayStore() || isCall() ||
1247 (mayLoad() && hasOrderedMemoryRef())) {
1252 if (isLabel() || isDebugValue() ||
1253 isTerminator() || hasUnmodeledSideEffects())
1256 // See if this instruction does a load. If so, we have to guarantee that the
1257 // loaded value doesn't change between the load and the its intended
1258 // destination. The check for isInvariantLoad gives the targe the chance to
1259 // classify the load as always returning a constant, e.g. a constant pool
1261 if (mayLoad() && !isInvariantLoad(AA))
1262 // Otherwise, this is a real load. If there is a store between the load and
1263 // end of block, we can't move it.
1269 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
1270 /// instruction which defined the specified register instead of copying it.
1271 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1273 unsigned DstReg) const {
1274 bool SawStore = false;
1275 if (!TII->isTriviallyReMaterializable(this, AA) ||
1276 !isSafeToMove(TII, AA, SawStore))
1278 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1279 const MachineOperand &MO = getOperand(i);
1282 // FIXME: For now, do not remat any instruction with register operands.
1283 // Later on, we can loosen the restriction is the register operands have
1284 // not been modified between the def and use. Note, this is different from
1285 // MachineSink because the code is no longer in two-address form (at least
1289 else if (!MO.isDead() && MO.getReg() != DstReg)
1295 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1296 /// or volatile memory reference, or if the information describing the memory
1297 /// reference is not available. Return false if it is known to have no ordered
1298 /// memory references.
1299 bool MachineInstr::hasOrderedMemoryRef() const {
1300 // An instruction known never to access memory won't have a volatile access.
1304 !hasUnmodeledSideEffects())
1307 // Otherwise, if the instruction has no memory reference information,
1308 // conservatively assume it wasn't preserved.
1309 if (memoperands_empty())
1312 // Check the memory reference information for ordered references.
1313 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1314 if (!(*I)->isUnordered())
1320 /// isInvariantLoad - Return true if this instruction is loading from a
1321 /// location whose value is invariant across the function. For example,
1322 /// loading a value from the constant pool or from the argument area
1323 /// of a function if it does not change. This should only return true of
1324 /// *all* loads the instruction does are invariant (if it does multiple loads).
1325 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1326 // If the instruction doesn't load at all, it isn't an invariant load.
1330 // If the instruction has lost its memoperands, conservatively assume that
1331 // it may not be an invariant load.
1332 if (memoperands_empty())
1335 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1337 for (mmo_iterator I = memoperands_begin(),
1338 E = memoperands_end(); I != E; ++I) {
1339 if ((*I)->isVolatile()) return false;
1340 if ((*I)->isStore()) return false;
1341 if ((*I)->isInvariant()) return true;
1343 if (const Value *V = (*I)->getValue()) {
1344 // A load from a constant PseudoSourceValue is invariant.
1345 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1346 if (PSV->isConstant(MFI))
1348 // If we have an AliasAnalysis, ask it whether the memory is constant.
1349 if (AA && AA->pointsToConstantMemory(
1350 AliasAnalysis::Location(V, (*I)->getSize(),
1351 (*I)->getTBAAInfo())))
1355 // Otherwise assume conservatively.
1359 // Everything checks out.
1363 /// isConstantValuePHI - If the specified instruction is a PHI that always
1364 /// merges together the same virtual register, return the register, otherwise
1366 unsigned MachineInstr::isConstantValuePHI() const {
1369 assert(getNumOperands() >= 3 &&
1370 "It's illegal to have a PHI without source operands");
1372 unsigned Reg = getOperand(1).getReg();
1373 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1374 if (getOperand(i).getReg() != Reg)
1379 bool MachineInstr::hasUnmodeledSideEffects() const {
1380 if (hasProperty(MCID::UnmodeledSideEffects))
1382 if (isInlineAsm()) {
1383 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1384 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1391 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1393 bool MachineInstr::allDefsAreDead() const {
1394 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1395 const MachineOperand &MO = getOperand(i);
1396 if (!MO.isReg() || MO.isUse())
1404 /// copyImplicitOps - Copy implicit register operands from specified
1405 /// instruction to this instruction.
1406 void MachineInstr::copyImplicitOps(MachineFunction &MF,
1407 const MachineInstr *MI) {
1408 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1410 const MachineOperand &MO = MI->getOperand(i);
1411 if (MO.isReg() && MO.isImplicit())
1416 void MachineInstr::dump() const {
1417 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1418 dbgs() << " " << *this;
1422 static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1423 raw_ostream &CommentOS) {
1424 const LLVMContext &Ctx = MF->getFunction()->getContext();
1425 if (!DL.isUnknown()) { // Print source line info.
1426 DIScope Scope(DL.getScope(Ctx));
1427 // Omit the directory, because it's likely to be long and uninteresting.
1429 CommentOS << Scope.getFilename();
1431 CommentOS << "<unknown>";
1432 CommentOS << ':' << DL.getLine();
1433 if (DL.getCol() != 0)
1434 CommentOS << ':' << DL.getCol();
1435 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1436 if (!InlinedAtDL.isUnknown()) {
1437 CommentOS << " @[ ";
1438 printDebugLoc(InlinedAtDL, MF, CommentOS);
1444 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1445 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1446 const MachineFunction *MF = 0;
1447 const MachineRegisterInfo *MRI = 0;
1448 if (const MachineBasicBlock *MBB = getParent()) {
1449 MF = MBB->getParent();
1451 TM = &MF->getTarget();
1453 MRI = &MF->getRegInfo();
1456 // Save a list of virtual registers.
1457 SmallVector<unsigned, 8> VirtRegs;
1459 // Print explicitly defined operands on the left of an assignment syntax.
1460 unsigned StartOp = 0, e = getNumOperands();
1461 for (; StartOp < e && getOperand(StartOp).isReg() &&
1462 getOperand(StartOp).isDef() &&
1463 !getOperand(StartOp).isImplicit();
1465 if (StartOp != 0) OS << ", ";
1466 getOperand(StartOp).print(OS, TM);
1467 unsigned Reg = getOperand(StartOp).getReg();
1468 if (TargetRegisterInfo::isVirtualRegister(Reg))
1469 VirtRegs.push_back(Reg);
1475 // Print the opcode name.
1476 if (TM && TM->getInstrInfo())
1477 OS << TM->getInstrInfo()->getName(getOpcode());
1481 // Print the rest of the operands.
1482 bool OmittedAnyCallClobbers = false;
1483 bool FirstOp = true;
1484 unsigned AsmDescOp = ~0u;
1485 unsigned AsmOpCount = 0;
1487 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1488 // Print asm string.
1490 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1492 // Print HasSideEffects, IsAlignStack
1493 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1494 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1495 OS << " [sideeffect]";
1496 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1497 OS << " [alignstack]";
1498 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1499 OS << " [attdialect]";
1500 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1501 OS << " [inteldialect]";
1503 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1508 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1509 const MachineOperand &MO = getOperand(i);
1511 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1512 VirtRegs.push_back(MO.getReg());
1514 // Omit call-clobbered registers which aren't used anywhere. This makes
1515 // call instructions much less noisy on targets where calls clobber lots
1516 // of registers. Don't rely on MO.isDead() because we may be called before
1517 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1518 if (MF && isCall() &&
1519 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1520 unsigned Reg = MO.getReg();
1521 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1522 const MachineRegisterInfo &MRI = MF->getRegInfo();
1523 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1524 bool HasAliasLive = false;
1525 for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true);
1526 AI.isValid(); ++AI) {
1527 unsigned AliasReg = *AI;
1528 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1529 HasAliasLive = true;
1533 if (!HasAliasLive) {
1534 OmittedAnyCallClobbers = true;
1541 if (FirstOp) FirstOp = false; else OS << ",";
1543 if (i < getDesc().NumOperands) {
1544 const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1545 if (MCOI.isPredicate())
1547 if (MCOI.isOptionalDef())
1550 if (isDebugValue() && MO.isMetadata()) {
1551 // Pretty print DBG_VALUE instructions.
1552 const MDNode *MD = MO.getMetadata();
1553 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1554 OS << "!\"" << MDS->getString() << '\"';
1557 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1558 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1559 } else if (i == AsmDescOp && MO.isImm()) {
1560 // Pretty print the inline asm operand descriptor.
1561 OS << '$' << AsmOpCount++;
1562 unsigned Flag = MO.getImm();
1563 switch (InlineAsm::getKind(Flag)) {
1564 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1565 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1566 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1567 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1568 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1569 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1570 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1574 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1576 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1578 OS << ":RC" << RCID;
1581 unsigned TiedTo = 0;
1582 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1583 OS << " tiedto:$" << TiedTo;
1587 // Compute the index of the next operand descriptor.
1588 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1593 // Briefly indicate whether any call clobbers were omitted.
1594 if (OmittedAnyCallClobbers) {
1595 if (!FirstOp) OS << ",";
1599 bool HaveSemi = false;
1601 if (!HaveSemi) OS << ";"; HaveSemi = true;
1604 if (Flags & FrameSetup)
1608 if (!memoperands_empty()) {
1609 if (!HaveSemi) OS << ";"; HaveSemi = true;
1612 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1615 if (llvm::next(i) != e)
1620 // Print the regclass of any virtual registers encountered.
1621 if (MRI && !VirtRegs.empty()) {
1622 if (!HaveSemi) OS << ";"; HaveSemi = true;
1623 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1624 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1625 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1626 for (unsigned j = i+1; j != VirtRegs.size();) {
1627 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1631 if (VirtRegs[i] != VirtRegs[j])
1632 OS << "," << PrintReg(VirtRegs[j]);
1633 VirtRegs.erase(VirtRegs.begin()+j);
1638 // Print debug location information.
1639 if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1640 if (!HaveSemi) OS << ";"; HaveSemi = true;
1641 DIVariable DV(getOperand(e - 1).getMetadata());
1642 OS << " line no:" << DV.getLineNumber();
1643 if (MDNode *InlinedAt = DV.getInlinedAt()) {
1644 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1645 if (!InlinedAtDL.isUnknown()) {
1646 OS << " inlined @[ ";
1647 printDebugLoc(InlinedAtDL, MF, OS);
1651 } else if (!debugLoc.isUnknown() && MF) {
1652 if (!HaveSemi) OS << ";"; HaveSemi = true;
1654 printDebugLoc(debugLoc, MF, OS);
1660 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1661 const TargetRegisterInfo *RegInfo,
1662 bool AddIfNotFound) {
1663 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1664 bool hasAliases = isPhysReg &&
1665 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1667 SmallVector<unsigned,4> DeadOps;
1668 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1669 MachineOperand &MO = getOperand(i);
1670 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1672 unsigned Reg = MO.getReg();
1676 if (Reg == IncomingReg) {
1679 // The register is already marked kill.
1681 if (isPhysReg && isRegTiedToDefOperand(i))
1682 // Two-address uses of physregs must not be marked kill.
1687 } else if (hasAliases && MO.isKill() &&
1688 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1689 // A super-register kill already exists.
1690 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1692 if (RegInfo->isSubRegister(IncomingReg, Reg))
1693 DeadOps.push_back(i);
1697 // Trim unneeded kill operands.
1698 while (!DeadOps.empty()) {
1699 unsigned OpIdx = DeadOps.back();
1700 if (getOperand(OpIdx).isImplicit())
1701 RemoveOperand(OpIdx);
1703 getOperand(OpIdx).setIsKill(false);
1707 // If not found, this means an alias of one of the operands is killed. Add a
1708 // new implicit operand if required.
1709 if (!Found && AddIfNotFound) {
1710 addOperand(MachineOperand::CreateReg(IncomingReg,
1719 void MachineInstr::clearRegisterKills(unsigned Reg,
1720 const TargetRegisterInfo *RegInfo) {
1721 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1723 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1724 MachineOperand &MO = getOperand(i);
1725 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1727 unsigned OpReg = MO.getReg();
1728 if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1729 MO.setIsKill(false);
1733 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1734 const TargetRegisterInfo *RegInfo,
1735 bool AddIfNotFound) {
1736 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1737 bool hasAliases = isPhysReg &&
1738 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1740 SmallVector<unsigned,4> DeadOps;
1741 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1742 MachineOperand &MO = getOperand(i);
1743 if (!MO.isReg() || !MO.isDef())
1745 unsigned Reg = MO.getReg();
1749 if (Reg == IncomingReg) {
1752 } else if (hasAliases && MO.isDead() &&
1753 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1754 // There exists a super-register that's marked dead.
1755 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1757 if (RegInfo->isSubRegister(IncomingReg, Reg))
1758 DeadOps.push_back(i);
1762 // Trim unneeded dead operands.
1763 while (!DeadOps.empty()) {
1764 unsigned OpIdx = DeadOps.back();
1765 if (getOperand(OpIdx).isImplicit())
1766 RemoveOperand(OpIdx);
1768 getOperand(OpIdx).setIsDead(false);
1772 // If not found, this means an alias of one of the operands is dead. Add a
1773 // new implicit operand if required.
1774 if (Found || !AddIfNotFound)
1777 addOperand(MachineOperand::CreateReg(IncomingReg,
1785 void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1786 const TargetRegisterInfo *RegInfo) {
1787 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1788 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1792 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1793 const MachineOperand &MO = getOperand(i);
1794 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1795 MO.getSubReg() == 0)
1799 addOperand(MachineOperand::CreateReg(IncomingReg,
1804 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1805 const TargetRegisterInfo &TRI) {
1806 bool HasRegMask = false;
1807 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1808 MachineOperand &MO = getOperand(i);
1809 if (MO.isRegMask()) {
1813 if (!MO.isReg() || !MO.isDef()) continue;
1814 unsigned Reg = MO.getReg();
1815 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1817 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1819 if (TRI.regsOverlap(*I, Reg)) {
1823 // If there are no uses, including partial uses, the def is dead.
1824 if (Dead) MO.setIsDead();
1827 // This is a call with a register mask operand.
1828 // Mask clobbers are always dead, so add defs for the non-dead defines.
1830 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1832 addRegisterDefined(*I, &TRI);
1836 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1837 // Build up a buffer of hash code components.
1838 SmallVector<size_t, 8> HashComponents;
1839 HashComponents.reserve(MI->getNumOperands() + 1);
1840 HashComponents.push_back(MI->getOpcode());
1841 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1842 const MachineOperand &MO = MI->getOperand(i);
1843 if (MO.isReg() && MO.isDef() &&
1844 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1845 continue; // Skip virtual register defs.
1847 HashComponents.push_back(hash_value(MO));
1849 return hash_combine_range(HashComponents.begin(), HashComponents.end());
1852 void MachineInstr::emitError(StringRef Msg) const {
1853 // Find the source location cookie.
1854 unsigned LocCookie = 0;
1855 const MDNode *LocMD = 0;
1856 for (unsigned i = getNumOperands(); i != 0; --i) {
1857 if (getOperand(i-1).isMetadata() &&
1858 (LocMD = getOperand(i-1).getMetadata()) &&
1859 LocMD->getNumOperands() != 0) {
1860 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1861 LocCookie = CI->getZExtValue();
1867 if (const MachineBasicBlock *MBB = getParent())
1868 if (const MachineFunction *MF = MBB->getParent())
1869 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1870 report_fatal_error(Msg);