1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/InlineAsm.h"
17 #include "llvm/Value.h"
18 #include "llvm/Assembly/Writer.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetInstrDesc.h"
25 #include "llvm/Target/TargetRegisterInfo.h"
26 #include "llvm/Analysis/DebugInfo.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/LeakDetector.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/ADT/FoldingSet.h"
34 //===----------------------------------------------------------------------===//
35 // MachineOperand Implementation
36 //===----------------------------------------------------------------------===//
38 /// AddRegOperandToRegInfo - Add this register operand to the specified
39 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
40 /// explicitly nulled out.
41 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
42 assert(isReg() && "Can only add reg operand to use lists");
44 // If the reginfo pointer is null, just explicitly null out or next/prev
45 // pointers, to ensure they are not garbage.
47 Contents.Reg.Prev = 0;
48 Contents.Reg.Next = 0;
52 // Otherwise, add this operand to the head of the registers use/def list.
53 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
55 // For SSA values, we prefer to keep the definition at the start of the list.
56 // we do this by skipping over the definition if it is at the head of the
58 if (*Head && (*Head)->isDef())
59 Head = &(*Head)->Contents.Reg.Next;
61 Contents.Reg.Next = *Head;
62 if (Contents.Reg.Next) {
63 assert(getReg() == Contents.Reg.Next->getReg() &&
64 "Different regs on the same list!");
65 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
68 Contents.Reg.Prev = Head;
72 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
73 /// MachineRegisterInfo it is linked with.
74 void MachineOperand::RemoveRegOperandFromRegInfo() {
75 assert(isOnRegUseList() && "Reg operand is not on a use list");
76 // Unlink this from the doubly linked list of operands.
77 MachineOperand *NextOp = Contents.Reg.Next;
78 *Contents.Reg.Prev = NextOp;
80 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
81 NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
83 Contents.Reg.Prev = 0;
84 Contents.Reg.Next = 0;
87 void MachineOperand::setReg(unsigned Reg) {
88 if (getReg() == Reg) return; // No change.
90 // Otherwise, we have to change the register. If this operand is embedded
91 // into a machine function, we need to update the old and new register's
93 if (MachineInstr *MI = getParent())
94 if (MachineBasicBlock *MBB = MI->getParent())
95 if (MachineFunction *MF = MBB->getParent()) {
96 RemoveRegOperandFromRegInfo();
97 Contents.Reg.RegNo = Reg;
98 AddRegOperandToRegInfo(&MF->getRegInfo());
102 // Otherwise, just change the register, no problem. :)
103 Contents.Reg.RegNo = Reg;
106 /// ChangeToImmediate - Replace this operand with a new immediate operand of
107 /// the specified value. If an operand is known to be an immediate already,
108 /// the setImm method should be used.
109 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
110 // If this operand is currently a register operand, and if this is in a
111 // function, deregister the operand from the register's use/def list.
112 if (isReg() && getParent() && getParent()->getParent() &&
113 getParent()->getParent()->getParent())
114 RemoveRegOperandFromRegInfo();
116 OpKind = MO_Immediate;
117 Contents.ImmVal = ImmVal;
120 /// ChangeToRegister - Replace this operand with a new register operand of
121 /// the specified value. If an operand is known to be an register already,
122 /// the setReg method should be used.
123 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
124 bool isKill, bool isDead, bool isUndef) {
125 // If this operand is already a register operand, use setReg to update the
126 // register's use/def lists.
128 assert(!isEarlyClobber());
131 // Otherwise, change this to a register and set the reg#.
132 OpKind = MO_Register;
133 Contents.Reg.RegNo = Reg;
135 // If this operand is embedded in a function, add the operand to the
136 // register's use/def list.
137 if (MachineInstr *MI = getParent())
138 if (MachineBasicBlock *MBB = MI->getParent())
139 if (MachineFunction *MF = MBB->getParent())
140 AddRegOperandToRegInfo(&MF->getRegInfo());
148 IsEarlyClobber = false;
152 /// isIdenticalTo - Return true if this operand is identical to the specified
154 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
155 if (getType() != Other.getType() ||
156 getTargetFlags() != Other.getTargetFlags())
160 default: llvm_unreachable("Unrecognized operand type");
161 case MachineOperand::MO_Register:
162 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
163 getSubReg() == Other.getSubReg();
164 case MachineOperand::MO_Immediate:
165 return getImm() == Other.getImm();
166 case MachineOperand::MO_FPImmediate:
167 return getFPImm() == Other.getFPImm();
168 case MachineOperand::MO_MachineBasicBlock:
169 return getMBB() == Other.getMBB();
170 case MachineOperand::MO_FrameIndex:
171 return getIndex() == Other.getIndex();
172 case MachineOperand::MO_ConstantPoolIndex:
173 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
174 case MachineOperand::MO_JumpTableIndex:
175 return getIndex() == Other.getIndex();
176 case MachineOperand::MO_GlobalAddress:
177 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
178 case MachineOperand::MO_ExternalSymbol:
179 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
180 getOffset() == Other.getOffset();
184 /// print - Print the specified machine operand.
186 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
188 case MachineOperand::MO_Register:
189 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
190 OS << "%reg" << getReg();
192 // If the instruction is embedded into a basic block, we can find the
193 // target info for the instruction.
195 if (const MachineInstr *MI = getParent())
196 if (const MachineBasicBlock *MBB = MI->getParent())
197 if (const MachineFunction *MF = MBB->getParent())
198 TM = &MF->getTarget();
201 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
203 OS << "%mreg" << getReg();
206 if (getSubReg() != 0)
207 OS << ':' << getSubReg();
209 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
212 bool NeedComma = false;
214 if (NeedComma) OS << ',';
215 OS << (isDef() ? "imp-def" : "imp-use");
217 } else if (isDef()) {
218 if (NeedComma) OS << ',';
219 if (isEarlyClobber())
220 OS << "earlyclobber,";
224 if (isKill() || isDead() || isUndef()) {
225 if (NeedComma) OS << ',';
226 if (isKill()) OS << "kill";
227 if (isDead()) OS << "dead";
229 if (isKill() || isDead())
237 case MachineOperand::MO_Immediate:
240 case MachineOperand::MO_FPImmediate:
241 if (getFPImm()->getType() == Type::getFloatTy(getFPImm()->getContext()))
242 OS << getFPImm()->getValueAPF().convertToFloat();
244 OS << getFPImm()->getValueAPF().convertToDouble();
246 case MachineOperand::MO_MachineBasicBlock:
248 << ((Value*)getMBB()->getBasicBlock())->getName()
249 << "," << (void*)getMBB() << '>';
251 case MachineOperand::MO_FrameIndex:
252 OS << "<fi#" << getIndex() << '>';
254 case MachineOperand::MO_ConstantPoolIndex:
255 OS << "<cp#" << getIndex();
256 if (getOffset()) OS << "+" << getOffset();
259 case MachineOperand::MO_JumpTableIndex:
260 OS << "<jt#" << getIndex() << '>';
262 case MachineOperand::MO_GlobalAddress:
263 OS << "<ga:" << ((Value*)getGlobal())->getName();
264 if (getOffset()) OS << "+" << getOffset();
267 case MachineOperand::MO_ExternalSymbol:
268 OS << "<es:" << getSymbolName();
269 if (getOffset()) OS << "+" << getOffset();
273 llvm_unreachable("Unrecognized operand type");
276 if (unsigned TF = getTargetFlags())
277 OS << "[TF=" << TF << ']';
280 //===----------------------------------------------------------------------===//
281 // MachineMemOperand Implementation
282 //===----------------------------------------------------------------------===//
284 MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
285 int64_t o, uint64_t s, unsigned int a)
286 : Offset(o), Size(s), V(v),
287 Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
288 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
289 assert((isLoad() || isStore()) && "Not a load/store!");
292 /// Profile - Gather unique data for the object.
294 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
295 ID.AddInteger(Offset);
298 ID.AddInteger(Flags);
301 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MRO) {
302 assert((MRO.isLoad() || MRO.isStore()) &&
303 "SV has to be a load, store or both.");
305 if (MRO.isVolatile())
314 // Print the address information.
319 WriteAsOperand(OS, MRO.getValue(), /*PrintType=*/false);
321 // If the alignment of the memory reference itself differs from the alignment
322 // of the base pointer, print the base alignment explicitly, next to the base
324 if (MRO.getBaseAlignment() != MRO.getAlignment())
325 OS << "(align=" << MRO.getBaseAlignment() << ")";
327 if (MRO.getOffset() != 0)
328 OS << "+" << MRO.getOffset();
331 // Print the alignment of the reference.
332 if (MRO.getBaseAlignment() != MRO.getAlignment() ||
333 MRO.getBaseAlignment() != MRO.getSize())
334 OS << "(align=" << MRO.getAlignment() << ")";
339 //===----------------------------------------------------------------------===//
340 // MachineInstr Implementation
341 //===----------------------------------------------------------------------===//
343 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
344 /// TID NULL and no operands.
345 MachineInstr::MachineInstr()
346 : TID(0), NumImplicitOps(0), Parent(0), debugLoc(DebugLoc::getUnknownLoc()) {
347 // Make sure that we get added to a machine basicblock
348 LeakDetector::addGarbageObject(this);
351 void MachineInstr::addImplicitDefUseOperands() {
352 if (TID->ImplicitDefs)
353 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
354 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
355 if (TID->ImplicitUses)
356 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
357 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
360 /// MachineInstr ctor - This constructor create a MachineInstr and add the
361 /// implicit operands. It reserves space for number of operands specified by
362 /// TargetInstrDesc or the numOperands if it is not zero. (for
363 /// instructions with variable number of operands).
364 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
365 : TID(&tid), NumImplicitOps(0), Parent(0),
366 debugLoc(DebugLoc::getUnknownLoc()) {
367 if (!NoImp && TID->getImplicitDefs())
368 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
370 if (!NoImp && TID->getImplicitUses())
371 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
373 Operands.reserve(NumImplicitOps + TID->getNumOperands());
375 addImplicitDefUseOperands();
376 // Make sure that we get added to a machine basicblock
377 LeakDetector::addGarbageObject(this);
380 /// MachineInstr ctor - As above, but with a DebugLoc.
381 MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
383 : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) {
384 if (!NoImp && TID->getImplicitDefs())
385 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
387 if (!NoImp && TID->getImplicitUses())
388 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
390 Operands.reserve(NumImplicitOps + TID->getNumOperands());
392 addImplicitDefUseOperands();
393 // Make sure that we get added to a machine basicblock
394 LeakDetector::addGarbageObject(this);
397 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
398 /// that the MachineInstr is created and added to the end of the specified
401 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
402 : TID(&tid), NumImplicitOps(0), Parent(0),
403 debugLoc(DebugLoc::getUnknownLoc()) {
404 assert(MBB && "Cannot use inserting ctor with null basic block!");
405 if (TID->ImplicitDefs)
406 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
408 if (TID->ImplicitUses)
409 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
411 Operands.reserve(NumImplicitOps + TID->getNumOperands());
412 addImplicitDefUseOperands();
413 // Make sure that we get added to a machine basicblock
414 LeakDetector::addGarbageObject(this);
415 MBB->push_back(this); // Add instruction to end of basic block!
418 /// MachineInstr ctor - As above, but with a DebugLoc.
420 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
421 const TargetInstrDesc &tid)
422 : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) {
423 assert(MBB && "Cannot use inserting ctor with null basic block!");
424 if (TID->ImplicitDefs)
425 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
427 if (TID->ImplicitUses)
428 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
430 Operands.reserve(NumImplicitOps + TID->getNumOperands());
431 addImplicitDefUseOperands();
432 // Make sure that we get added to a machine basicblock
433 LeakDetector::addGarbageObject(this);
434 MBB->push_back(this); // Add instruction to end of basic block!
437 /// MachineInstr ctor - Copies MachineInstr arg exactly
439 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
440 : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0),
441 debugLoc(MI.getDebugLoc()) {
442 Operands.reserve(MI.getNumOperands());
445 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
446 addOperand(MI.getOperand(i));
447 NumImplicitOps = MI.NumImplicitOps;
449 // Add memory operands.
450 for (std::list<MachineMemOperand>::const_iterator i = MI.memoperands_begin(),
451 j = MI.memoperands_end(); i != j; ++i)
452 addMemOperand(MF, *i);
454 // Set parent to null.
457 LeakDetector::addGarbageObject(this);
460 MachineInstr::~MachineInstr() {
461 LeakDetector::removeGarbageObject(this);
462 assert(MemOperands.empty() &&
463 "MachineInstr being deleted with live memoperands!");
465 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
466 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
467 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
468 "Reg operand def/use list corrupted");
473 /// getRegInfo - If this instruction is embedded into a MachineFunction,
474 /// return the MachineRegisterInfo object for the current function, otherwise
476 MachineRegisterInfo *MachineInstr::getRegInfo() {
477 if (MachineBasicBlock *MBB = getParent())
478 return &MBB->getParent()->getRegInfo();
482 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
483 /// this instruction from their respective use lists. This requires that the
484 /// operands already be on their use lists.
485 void MachineInstr::RemoveRegOperandsFromUseLists() {
486 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
487 if (Operands[i].isReg())
488 Operands[i].RemoveRegOperandFromRegInfo();
492 /// AddRegOperandsToUseLists - Add all of the register operands in
493 /// this instruction from their respective use lists. This requires that the
494 /// operands not be on their use lists yet.
495 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
496 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
497 if (Operands[i].isReg())
498 Operands[i].AddRegOperandToRegInfo(&RegInfo);
503 /// addOperand - Add the specified operand to the instruction. If it is an
504 /// implicit operand, it is added to the end of the operand list. If it is
505 /// an explicit operand it is added at the end of the explicit operand list
506 /// (before the first implicit operand).
507 void MachineInstr::addOperand(const MachineOperand &Op) {
508 bool isImpReg = Op.isReg() && Op.isImplicit();
509 assert((isImpReg || !OperandsComplete()) &&
510 "Trying to add an operand to a machine instr that is already done!");
512 MachineRegisterInfo *RegInfo = getRegInfo();
514 // If we are adding the operand to the end of the list, our job is simpler.
515 // This is true most of the time, so this is a reasonable optimization.
516 if (isImpReg || NumImplicitOps == 0) {
517 // We can only do this optimization if we know that the operand list won't
519 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
520 Operands.push_back(Op);
522 // Set the parent of the operand.
523 Operands.back().ParentMI = this;
525 // If the operand is a register, update the operand's use list.
527 Operands.back().AddRegOperandToRegInfo(RegInfo);
532 // Otherwise, we have to insert a real operand before any implicit ones.
533 unsigned OpNo = Operands.size()-NumImplicitOps;
535 // If this instruction isn't embedded into a function, then we don't need to
536 // update any operand lists.
538 // Simple insertion, no reginfo update needed for other register operands.
539 Operands.insert(Operands.begin()+OpNo, Op);
540 Operands[OpNo].ParentMI = this;
542 // Do explicitly set the reginfo for this operand though, to ensure the
543 // next/prev fields are properly nulled out.
544 if (Operands[OpNo].isReg())
545 Operands[OpNo].AddRegOperandToRegInfo(0);
547 } else if (Operands.size()+1 <= Operands.capacity()) {
548 // Otherwise, we have to remove register operands from their register use
549 // list, add the operand, then add the register operands back to their use
550 // list. This also must handle the case when the operand list reallocates
551 // to somewhere else.
553 // If insertion of this operand won't cause reallocation of the operand
554 // list, just remove the implicit operands, add the operand, then re-add all
555 // the rest of the operands.
556 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
557 assert(Operands[i].isReg() && "Should only be an implicit reg!");
558 Operands[i].RemoveRegOperandFromRegInfo();
561 // Add the operand. If it is a register, add it to the reg list.
562 Operands.insert(Operands.begin()+OpNo, Op);
563 Operands[OpNo].ParentMI = this;
565 if (Operands[OpNo].isReg())
566 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
568 // Re-add all the implicit ops.
569 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
570 assert(Operands[i].isReg() && "Should only be an implicit reg!");
571 Operands[i].AddRegOperandToRegInfo(RegInfo);
574 // Otherwise, we will be reallocating the operand list. Remove all reg
575 // operands from their list, then readd them after the operand list is
577 RemoveRegOperandsFromUseLists();
579 Operands.insert(Operands.begin()+OpNo, Op);
580 Operands[OpNo].ParentMI = this;
582 // Re-add all the operands.
583 AddRegOperandsToUseLists(*RegInfo);
587 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
588 /// fewer operand than it started with.
590 void MachineInstr::RemoveOperand(unsigned OpNo) {
591 assert(OpNo < Operands.size() && "Invalid operand number");
593 // Special case removing the last one.
594 if (OpNo == Operands.size()-1) {
595 // If needed, remove from the reg def/use list.
596 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
597 Operands.back().RemoveRegOperandFromRegInfo();
603 // Otherwise, we are removing an interior operand. If we have reginfo to
604 // update, remove all operands that will be shifted down from their reg lists,
605 // move everything down, then re-add them.
606 MachineRegisterInfo *RegInfo = getRegInfo();
608 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
609 if (Operands[i].isReg())
610 Operands[i].RemoveRegOperandFromRegInfo();
614 Operands.erase(Operands.begin()+OpNo);
617 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
618 if (Operands[i].isReg())
619 Operands[i].AddRegOperandToRegInfo(RegInfo);
624 /// addMemOperand - Add a MachineMemOperand to the machine instruction,
625 /// referencing arbitrary storage.
626 void MachineInstr::addMemOperand(MachineFunction &MF,
627 const MachineMemOperand &MO) {
628 MemOperands.push_back(MO);
631 /// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
632 void MachineInstr::clearMemOperands(MachineFunction &MF) {
637 /// removeFromParent - This method unlinks 'this' from the containing basic
638 /// block, and returns it, but does not delete it.
639 MachineInstr *MachineInstr::removeFromParent() {
640 assert(getParent() && "Not embedded in a basic block!");
641 getParent()->remove(this);
646 /// eraseFromParent - This method unlinks 'this' from the containing basic
647 /// block, and deletes it.
648 void MachineInstr::eraseFromParent() {
649 assert(getParent() && "Not embedded in a basic block!");
650 getParent()->erase(this);
654 /// OperandComplete - Return true if it's illegal to add a new operand
656 bool MachineInstr::OperandsComplete() const {
657 unsigned short NumOperands = TID->getNumOperands();
658 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
659 return true; // Broken: we have all the operands of this instruction!
663 /// getNumExplicitOperands - Returns the number of non-implicit operands.
665 unsigned MachineInstr::getNumExplicitOperands() const {
666 unsigned NumOperands = TID->getNumOperands();
667 if (!TID->isVariadic())
670 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
671 const MachineOperand &MO = getOperand(i);
672 if (!MO.isReg() || !MO.isImplicit())
679 /// isLabel - Returns true if the MachineInstr represents a label.
681 bool MachineInstr::isLabel() const {
682 return getOpcode() == TargetInstrInfo::DBG_LABEL ||
683 getOpcode() == TargetInstrInfo::EH_LABEL ||
684 getOpcode() == TargetInstrInfo::GC_LABEL;
687 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
689 bool MachineInstr::isDebugLabel() const {
690 return getOpcode() == TargetInstrInfo::DBG_LABEL;
693 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
694 /// the specific register or -1 if it is not found. It further tightens
695 /// the search criteria to a use that kills the register if isKill is true.
696 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
697 const TargetRegisterInfo *TRI) const {
698 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
699 const MachineOperand &MO = getOperand(i);
700 if (!MO.isReg() || !MO.isUse())
702 unsigned MOReg = MO.getReg();
707 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
708 TargetRegisterInfo::isPhysicalRegister(Reg) &&
709 TRI->isSubRegister(MOReg, Reg)))
710 if (!isKill || MO.isKill())
716 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
717 /// the specified register or -1 if it is not found. If isDead is true, defs
718 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
719 /// also checks if there is a def of a super-register.
720 int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
721 const TargetRegisterInfo *TRI) const {
722 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
723 const MachineOperand &MO = getOperand(i);
724 if (!MO.isReg() || !MO.isDef())
726 unsigned MOReg = MO.getReg();
729 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
730 TargetRegisterInfo::isPhysicalRegister(Reg) &&
731 TRI->isSubRegister(MOReg, Reg)))
732 if (!isDead || MO.isDead())
738 /// findFirstPredOperandIdx() - Find the index of the first operand in the
739 /// operand list that is used to represent the predicate. It returns -1 if
741 int MachineInstr::findFirstPredOperandIdx() const {
742 const TargetInstrDesc &TID = getDesc();
743 if (TID.isPredicable()) {
744 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
745 if (TID.OpInfo[i].isPredicate())
752 /// isRegTiedToUseOperand - Given the index of a register def operand,
753 /// check if the register def is tied to a source operand, due to either
754 /// two-address elimination or inline assembly constraints. Returns the
755 /// first tied use operand index by reference is UseOpIdx is not null.
757 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
758 if (getOpcode() == TargetInstrInfo::INLINEASM) {
759 assert(DefOpIdx >= 2);
760 const MachineOperand &MO = getOperand(DefOpIdx);
761 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
763 // Determine the actual operand index that corresponds to this index.
765 unsigned DefPart = 0;
766 for (unsigned i = 1, e = getNumOperands(); i < e; ) {
767 const MachineOperand &FMO = getOperand(i);
768 // After the normal asm operands there may be additional imp-def regs.
771 // Skip over this def.
772 unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
773 unsigned PrevDef = i + 1;
774 i = PrevDef + NumOps;
776 DefPart = DefOpIdx - PrevDef;
781 for (unsigned i = 1, e = getNumOperands(); i != e; ++i) {
782 const MachineOperand &FMO = getOperand(i);
785 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
788 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
791 *UseOpIdx = (unsigned)i + 1 + DefPart;
798 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
799 const TargetInstrDesc &TID = getDesc();
800 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
801 const MachineOperand &MO = getOperand(i);
802 if (MO.isReg() && MO.isUse() &&
803 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
805 *UseOpIdx = (unsigned)i;
812 /// isRegTiedToDefOperand - Return true if the operand of the specified index
813 /// is a register use and it is tied to an def operand. It also returns the def
814 /// operand index by reference.
816 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
817 if (getOpcode() == TargetInstrInfo::INLINEASM) {
818 const MachineOperand &MO = getOperand(UseOpIdx);
819 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
822 // Find the flag operand corresponding to UseOpIdx
823 unsigned FlagIdx, NumOps=0;
824 for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
825 const MachineOperand &UFMO = getOperand(FlagIdx);
826 // After the normal asm operands there may be additional imp-def regs.
829 NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
830 assert(NumOps < getNumOperands() && "Invalid inline asm flag");
831 if (UseOpIdx < FlagIdx+NumOps+1)
834 if (FlagIdx >= UseOpIdx)
836 const MachineOperand &UFMO = getOperand(FlagIdx);
838 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
843 // Remember to adjust the index. First operand is asm string, then there
844 // is a flag for each.
846 const MachineOperand &FMO = getOperand(DefIdx);
848 // Skip over this def.
849 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
852 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
858 const TargetInstrDesc &TID = getDesc();
859 if (UseOpIdx >= TID.getNumOperands())
861 const MachineOperand &MO = getOperand(UseOpIdx);
862 if (!MO.isReg() || !MO.isUse())
864 int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
868 *DefOpIdx = (unsigned)DefIdx;
872 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
874 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
875 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
876 const MachineOperand &MO = MI->getOperand(i);
877 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
879 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
880 MachineOperand &MOp = getOperand(j);
881 if (!MOp.isIdenticalTo(MO))
892 /// copyPredicates - Copies predicate operand(s) from MI.
893 void MachineInstr::copyPredicates(const MachineInstr *MI) {
894 const TargetInstrDesc &TID = MI->getDesc();
895 if (!TID.isPredicable())
897 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
898 if (TID.OpInfo[i].isPredicate()) {
899 // Predicated operands must be last operands.
900 addOperand(MI->getOperand(i));
905 /// isSafeToMove - Return true if it is safe to move this instruction. If
906 /// SawStore is set to true, it means that there is a store (or call) between
907 /// the instruction's location and its intended destination.
908 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
909 bool &SawStore) const {
910 // Ignore stuff that we obviously can't move.
911 if (TID->mayStore() || TID->isCall()) {
915 if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
918 // See if this instruction does a load. If so, we have to guarantee that the
919 // loaded value doesn't change between the load and the its intended
920 // destination. The check for isInvariantLoad gives the targe the chance to
921 // classify the load as always returning a constant, e.g. a constant pool
923 if (TID->mayLoad() && !TII->isInvariantLoad(this))
924 // Otherwise, this is a real load. If there is a store between the load and
925 // end of block, or if the load is volatile, we can't move it.
926 return !SawStore && !hasVolatileMemoryRef();
931 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
932 /// instruction which defined the specified register instead of copying it.
933 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
934 unsigned DstReg) const {
935 bool SawStore = false;
936 if (!getDesc().isRematerializable() ||
937 !TII->isTriviallyReMaterializable(this) ||
938 !isSafeToMove(TII, SawStore))
940 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
941 const MachineOperand &MO = getOperand(i);
944 // FIXME: For now, do not remat any instruction with register operands.
945 // Later on, we can loosen the restriction is the register operands have
946 // not been modified between the def and use. Note, this is different from
947 // MachineSink because the code is no longer in two-address form (at least
951 else if (!MO.isDead() && MO.getReg() != DstReg)
957 /// hasVolatileMemoryRef - Return true if this instruction may have a
958 /// volatile memory reference, or if the information describing the
959 /// memory reference is not available. Return false if it is known to
960 /// have no volatile memory references.
961 bool MachineInstr::hasVolatileMemoryRef() const {
962 // An instruction known never to access memory won't have a volatile access.
963 if (!TID->mayStore() &&
966 !TID->hasUnmodeledSideEffects())
969 // Otherwise, if the instruction has no memory reference information,
970 // conservatively assume it wasn't preserved.
971 if (memoperands_empty())
974 // Check the memory reference information for volatile references.
975 for (std::list<MachineMemOperand>::const_iterator I = memoperands_begin(),
976 E = memoperands_end(); I != E; ++I)
983 void MachineInstr::dump() const {
984 errs() << " " << *this;
987 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
988 // Specialize printing if op#0 is definition
989 unsigned StartOp = 0;
990 if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
991 getOperand(0).print(OS, TM);
993 ++StartOp; // Don't print this operand again!
996 OS << getDesc().getName();
998 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1002 getOperand(i).print(OS, TM);
1005 if (!memoperands_empty()) {
1007 for (std::list<MachineMemOperand>::const_iterator i = memoperands_begin(),
1008 e = memoperands_end(); i != e; ++i) {
1015 if (!debugLoc.isUnknown()) {
1016 const MachineFunction *MF = getParent()->getParent();
1017 DebugLocTuple DLT = MF->getDebugLocTuple(debugLoc);
1018 DICompileUnit CU(DLT.CompileUnit);
1019 std::string Dir, Fn;
1021 << CU.getDirectory(Dir) << '/' << CU.getFilename(Fn) << ","
1029 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1030 const TargetRegisterInfo *RegInfo,
1031 bool AddIfNotFound) {
1032 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1033 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1035 SmallVector<unsigned,4> DeadOps;
1036 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1037 MachineOperand &MO = getOperand(i);
1038 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1040 unsigned Reg = MO.getReg();
1044 if (Reg == IncomingReg) {
1047 // The register is already marked kill.
1049 if (isPhysReg && isRegTiedToDefOperand(i))
1050 // Two-address uses of physregs must not be marked kill.
1055 } else if (hasAliases && MO.isKill() &&
1056 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1057 // A super-register kill already exists.
1058 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1060 if (RegInfo->isSubRegister(IncomingReg, Reg))
1061 DeadOps.push_back(i);
1065 // Trim unneeded kill operands.
1066 while (!DeadOps.empty()) {
1067 unsigned OpIdx = DeadOps.back();
1068 if (getOperand(OpIdx).isImplicit())
1069 RemoveOperand(OpIdx);
1071 getOperand(OpIdx).setIsKill(false);
1075 // If not found, this means an alias of one of the operands is killed. Add a
1076 // new implicit operand if required.
1077 if (!Found && AddIfNotFound) {
1078 addOperand(MachineOperand::CreateReg(IncomingReg,
1087 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1088 const TargetRegisterInfo *RegInfo,
1089 bool AddIfNotFound) {
1090 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1091 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1093 SmallVector<unsigned,4> DeadOps;
1094 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1095 MachineOperand &MO = getOperand(i);
1096 if (!MO.isReg() || !MO.isDef())
1098 unsigned Reg = MO.getReg();
1102 if (Reg == IncomingReg) {
1105 // The register is already marked dead.
1110 } else if (hasAliases && MO.isDead() &&
1111 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1112 // There exists a super-register that's marked dead.
1113 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1115 if (RegInfo->getSubRegisters(IncomingReg) &&
1116 RegInfo->getSuperRegisters(Reg) &&
1117 RegInfo->isSubRegister(IncomingReg, Reg))
1118 DeadOps.push_back(i);
1122 // Trim unneeded dead operands.
1123 while (!DeadOps.empty()) {
1124 unsigned OpIdx = DeadOps.back();
1125 if (getOperand(OpIdx).isImplicit())
1126 RemoveOperand(OpIdx);
1128 getOperand(OpIdx).setIsDead(false);
1132 // If not found, this means an alias of one of the operands is dead. Add a
1133 // new implicit operand if required.
1134 if (Found || !AddIfNotFound)
1137 addOperand(MachineOperand::CreateReg(IncomingReg,