1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 //===----------------------------------------------------------------------===//
5 #include "llvm/CodeGen/MachineInstr.h"
6 #include "llvm/CodeGen/MachineBasicBlock.h"
7 #include "llvm/Value.h"
8 #include "llvm/Target/TargetMachine.h"
9 #include "llvm/Target/TargetInstrInfo.h"
10 #include "llvm/Target/MRegisterInfo.h"
12 // Global variable holding an array of descriptors for machine instructions.
13 // The actual object needs to be created separately for each target machine.
14 // This variable is initialized and reset by class TargetInstrInfo.
16 // FIXME: This should be a property of the target so that more than one target
17 // at a time can be active...
19 extern const TargetInstrDescriptor *TargetInstrDescriptors;
21 // Constructor for instructions with variable #operands
22 MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
25 operands(numOperands, MachineOperand()),
30 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
31 /// not a resize for them. It is expected that if you use this that you call
32 /// add* methods below to fill up the operands, instead of the Set methods.
33 /// Eventually, the "resizing" ctors will be phased out.
35 MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
41 operands.reserve(numOperands);
44 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
45 /// MachineInstr is created and added to the end of the specified basic block.
47 MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
53 assert(MBB && "Cannot use inserting ctor with null basic block!");
54 operands.reserve(numOperands);
55 MBB->push_back(this); // Add instruction to end of basic block!
59 // OperandComplete - Return true if it's illegal to add a new operand
60 bool MachineInstr::OperandsComplete() const
62 int NumOperands = TargetInstrDescriptors[opCode].numOperands;
63 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
64 return true; // Broken: we have all the operands of this instruction!
70 // Support for replacing opcode and operands of a MachineInstr in place.
71 // This only resets the size of the operand vector and initializes it.
72 // The new operands must be set explicitly later.
74 void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands)
76 assert(getNumImplicitRefs() == 0 &&
77 "This is probably broken because implicit refs are going to be lost.");
80 operands.resize(numOperands, MachineOperand());
84 MachineInstr::SetMachineOperandVal(unsigned i,
85 MachineOperand::MachineOperandType opType,
90 assert(i < operands.size()); // may be explicit or implicit op
91 operands[i].opType = opType;
92 operands[i].value = V;
93 operands[i].regNum = -1;
96 operands[i].flags = MachineOperand::DEFUSEFLAG;
97 else if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
98 operands[i].flags = MachineOperand::DEFONLYFLAG;
100 operands[i].flags = 0;
104 MachineInstr::SetMachineOperandConst(unsigned i,
105 MachineOperand::MachineOperandType operandType,
108 assert(i < getNumOperands()); // must be explicit op
109 assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
110 "immed. constant cannot be defined");
112 operands[i].opType = operandType;
113 operands[i].value = NULL;
114 operands[i].immedVal = intValue;
115 operands[i].regNum = -1;
116 operands[i].flags = 0;
120 MachineInstr::SetMachineOperandReg(unsigned i,
123 assert(i < getNumOperands()); // must be explicit op
125 operands[i].opType = MachineOperand::MO_MachineRegister;
126 operands[i].value = NULL;
127 operands[i].regNum = regNum;
129 if (isdef || TargetInstrDescriptors[opCode].resultPos == (int)i) {
130 assert(operands[i].flags == MachineOperand::DEFONLYFLAG &&
131 "Shouldn't be changing a register type once set!");
132 operands[i].flags = MachineOperand::DEFONLYFLAG;
135 insertUsedReg(regNum);
139 MachineInstr::SetRegForOperand(unsigned i, int regNum)
141 assert(i < getNumOperands()); // must be explicit op
142 operands[i].setRegForValue(regNum);
143 insertUsedReg(regNum);
147 MachineInstr::SetRegForImplicitRef(unsigned i, int regNum)
149 getImplicitOp(i).setRegForValue(regNum);
150 insertUsedReg(regNum);
154 // Subsitute all occurrences of Value* oldVal with newVal in all operands
155 // and all implicit refs.
156 // If defsOnly == true, substitute defs only.
158 MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
159 bool defsOnly, bool notDefsAndUses,
160 bool& someArgsWereIgnored)
162 assert((defsOnly || !notDefsAndUses) &&
163 "notDefsAndUses is irrelevant if defsOnly == false.");
165 unsigned numSubst = 0;
167 // Subsitute operands
168 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
171 notDefsAndUses && O.isDefOnly() ||
172 !notDefsAndUses && !O.isUseOnly())
174 O.getMachineOperand().value = newVal;
178 someArgsWereIgnored = true;
180 // Subsitute implicit refs
181 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
182 if (getImplicitRef(i) == oldVal)
184 notDefsAndUses && getImplicitOp(i).opIsDefOnly() ||
185 !notDefsAndUses && !getImplicitOp(i).opIsUse())
187 getImplicitOp(i).value = newVal;
191 someArgsWereIgnored = true;
198 MachineInstr::dump() const
200 std::cerr << " " << *this;
203 static inline std::ostream&
204 OutputValue(std::ostream &os, const Value* val)
207 os << (void*) val; // print address always
208 if (val && val->hasName())
209 os << " " << val->getName() << ")"; // print name also, if available
213 static inline void OutputReg(std::ostream &os, unsigned RegNo,
214 const MRegisterInfo *MRI = 0) {
216 if (RegNo < MRegisterInfo::FirstVirtualRegister)
217 os << "%" << MRI->get(RegNo).Name;
219 os << "%reg" << RegNo;
221 os << "%mreg(" << RegNo << ")";
224 static void print(const MachineOperand &MO, std::ostream &OS,
225 const TargetMachine &TM) {
226 const MRegisterInfo *MRI = TM.getRegisterInfo();
227 bool CloseParen = true;
230 else if (MO.opLoBits32())
232 else if (MO.opHiBits64())
234 else if (MO.opLoBits64())
239 switch (MO.getType()) {
240 case MachineOperand::MO_VirtualRegister:
241 if (MO.getVRegValue()) {
243 OutputValue(OS, MO.getVRegValue());
244 if (MO.hasAllocatedReg())
247 if (MO.hasAllocatedReg())
248 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
250 case MachineOperand::MO_CCRegister:
252 OutputValue(OS, MO.getVRegValue());
253 if (MO.hasAllocatedReg()) {
255 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
258 case MachineOperand::MO_MachineRegister:
259 OutputReg(OS, MO.getMachineRegNum(), MRI);
261 case MachineOperand::MO_SignExtendedImmed:
262 OS << (long)MO.getImmedValue();
264 case MachineOperand::MO_UnextendedImmed:
265 OS << (long)MO.getImmedValue();
267 case MachineOperand::MO_PCRelativeDisp: {
268 const Value* opVal = MO.getVRegValue();
269 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
270 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
271 if (opVal->hasName())
272 OS << opVal->getName();
274 OS << (const void*) opVal;
278 case MachineOperand::MO_MachineBasicBlock:
280 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
281 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
283 case MachineOperand::MO_FrameIndex:
284 OS << "<fi#" << MO.getFrameIndex() << ">";
286 case MachineOperand::MO_ConstantPoolIndex:
287 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
289 case MachineOperand::MO_GlobalAddress:
290 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
292 case MachineOperand::MO_ExternalSymbol:
293 OS << "<es:" << MO.getSymbolName() << ">";
296 assert(0 && "Unrecognized operand type");
303 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
304 unsigned StartOp = 0;
306 // Specialize printing if op#0 is definition
307 if (getNumOperands() &&
308 (getOperand(0).opIsDefOnly() || getOperand(0).opIsDefAndUse())) {
309 ::print(getOperand(0), OS, TM);
311 ++StartOp; // Don't print this operand again!
313 OS << TM.getInstrInfo().getName(getOpcode());
315 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
316 const MachineOperand& mop = getOperand(i);
320 ::print(mop, OS, TM);
322 if (mop.opIsDefAndUse())
324 else if (mop.opIsDefOnly())
328 // code for printing implict references
329 if (getNumImplicitRefs()) {
330 OS << "\tImplicitRefs: ";
331 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
333 OutputValue(OS, getImplicitRef(i));
334 if (getImplicitOp(i).opIsDefAndUse())
336 else if (getImplicitOp(i).opIsDefOnly())
345 std::ostream &operator<<(std::ostream& os, const MachineInstr& MI)
347 os << TargetInstrDescriptors[MI.opCode].Name;
349 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
350 os << "\t" << MI.getOperand(i);
351 if (MI.getOperand(i).opIsDefOnly())
353 if (MI.getOperand(i).opIsDefAndUse())
357 // code for printing implict references
358 unsigned NumOfImpRefs = MI.getNumImplicitRefs();
359 if (NumOfImpRefs > 0) {
360 os << "\tImplicit: ";
361 for (unsigned z=0; z < NumOfImpRefs; z++) {
362 OutputValue(os, MI.getImplicitRef(z));
363 if (MI.getImplicitOp(z).opIsDefOnly()) os << "<d>";
364 if (MI.getImplicitOp(z).opIsDefAndUse()) os << "<d&u>";
372 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO)
376 else if (MO.opLoBits32())
378 else if (MO.opHiBits64())
380 else if (MO.opLoBits64())
383 switch (MO.getType())
385 case MachineOperand::MO_VirtualRegister:
386 if (MO.hasAllocatedReg())
387 OutputReg(OS, MO.getAllocatedRegNum());
389 if (MO.getVRegValue()) {
390 if (MO.hasAllocatedReg()) OS << "==";
392 OutputValue(OS, MO.getVRegValue());
395 case MachineOperand::MO_CCRegister:
397 OutputValue(OS, MO.getVRegValue());
398 if (MO.hasAllocatedReg()) {
400 OutputReg(OS, MO.getAllocatedRegNum());
403 case MachineOperand::MO_MachineRegister:
404 OutputReg(OS, MO.getMachineRegNum());
406 case MachineOperand::MO_SignExtendedImmed:
407 OS << (long)MO.getImmedValue();
409 case MachineOperand::MO_UnextendedImmed:
410 OS << (long)MO.getImmedValue();
412 case MachineOperand::MO_PCRelativeDisp:
414 const Value* opVal = MO.getVRegValue();
415 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
416 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
417 if (opVal->hasName())
418 OS << opVal->getName();
420 OS << (const void*) opVal;
424 case MachineOperand::MO_MachineBasicBlock:
426 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
427 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
429 case MachineOperand::MO_FrameIndex:
430 OS << "<fi#" << MO.getFrameIndex() << ">";
432 case MachineOperand::MO_ConstantPoolIndex:
433 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
435 case MachineOperand::MO_GlobalAddress:
436 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
438 case MachineOperand::MO_ExternalSymbol:
439 OS << "<es:" << MO.getSymbolName() << ">";
442 assert(0 && "Unrecognized operand type");
447 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
448 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))