1 //===-- lib/CodeGen/MachineInstrBundle.cpp --------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/CodeGen/MachineInstrBundle.h"
11 #include "llvm/ADT/SmallSet.h"
12 #include "llvm/ADT/SmallVector.h"
13 #include "llvm/CodeGen/MachineFunctionPass.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "llvm/Target/TargetSubtargetInfo.h"
23 class UnpackMachineBundles : public MachineFunctionPass {
25 static char ID; // Pass identification
26 UnpackMachineBundles(std::function<bool(const Function &)> Ftor = nullptr)
27 : MachineFunctionPass(ID), PredicateFtor(Ftor) {
28 initializeUnpackMachineBundlesPass(*PassRegistry::getPassRegistry());
31 bool runOnMachineFunction(MachineFunction &MF) override;
34 std::function<bool(const Function &)> PredicateFtor;
36 } // end anonymous namespace
38 char UnpackMachineBundles::ID = 0;
39 char &llvm::UnpackMachineBundlesID = UnpackMachineBundles::ID;
40 INITIALIZE_PASS(UnpackMachineBundles, "unpack-mi-bundles",
41 "Unpack machine instruction bundles", false, false)
43 bool UnpackMachineBundles::runOnMachineFunction(MachineFunction &MF) {
44 if (PredicateFtor && !PredicateFtor(*MF.getFunction()))
48 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
49 MachineBasicBlock *MBB = &*I;
51 for (MachineBasicBlock::instr_iterator MII = MBB->instr_begin(),
52 MIE = MBB->instr_end(); MII != MIE; ) {
53 MachineInstr *MI = &*MII;
55 // Remove BUNDLE instruction and the InsideBundle flags from bundled
58 while (++MII != MIE && MII->isBundledWithPred()) {
59 MII->unbundleFromPred();
60 for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
61 MachineOperand &MO = MII->getOperand(i);
62 if (MO.isReg() && MO.isInternalRead())
63 MO.setIsInternalRead(false);
66 MI->eraseFromParent();
80 llvm::createUnpackMachineBundles(std::function<bool(const Function &)> Ftor) {
81 return new UnpackMachineBundles(Ftor);
85 class FinalizeMachineBundles : public MachineFunctionPass {
87 static char ID; // Pass identification
88 FinalizeMachineBundles() : MachineFunctionPass(ID) {
89 initializeFinalizeMachineBundlesPass(*PassRegistry::getPassRegistry());
92 bool runOnMachineFunction(MachineFunction &MF) override;
94 } // end anonymous namespace
96 char FinalizeMachineBundles::ID = 0;
97 char &llvm::FinalizeMachineBundlesID = FinalizeMachineBundles::ID;
98 INITIALIZE_PASS(FinalizeMachineBundles, "finalize-mi-bundles",
99 "Finalize machine instruction bundles", false, false)
101 bool FinalizeMachineBundles::runOnMachineFunction(MachineFunction &MF) {
102 return llvm::finalizeBundles(MF);
106 /// finalizeBundle - Finalize a machine instruction bundle which includes
107 /// a sequence of instructions starting from FirstMI to LastMI (exclusive).
108 /// This routine adds a BUNDLE instruction to represent the bundle, it adds
109 /// IsInternalRead markers to MachineOperands which are defined inside the
110 /// bundle, and it copies externally visible defs and uses to the BUNDLE
112 void llvm::finalizeBundle(MachineBasicBlock &MBB,
113 MachineBasicBlock::instr_iterator FirstMI,
114 MachineBasicBlock::instr_iterator LastMI) {
115 assert(FirstMI != LastMI && "Empty bundle?");
116 MIBundleBuilder Bundle(MBB, FirstMI, LastMI);
118 MachineFunction &MF = *MBB.getParent();
119 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
120 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
122 MachineInstrBuilder MIB =
123 BuildMI(MF, FirstMI->getDebugLoc(), TII->get(TargetOpcode::BUNDLE));
126 SmallVector<unsigned, 32> LocalDefs;
127 SmallSet<unsigned, 32> LocalDefSet;
128 SmallSet<unsigned, 8> DeadDefSet;
129 SmallSet<unsigned, 16> KilledDefSet;
130 SmallVector<unsigned, 8> ExternUses;
131 SmallSet<unsigned, 8> ExternUseSet;
132 SmallSet<unsigned, 8> KilledUseSet;
133 SmallSet<unsigned, 8> UndefUseSet;
134 SmallVector<MachineOperand*, 4> Defs;
135 for (; FirstMI != LastMI; ++FirstMI) {
136 for (unsigned i = 0, e = FirstMI->getNumOperands(); i != e; ++i) {
137 MachineOperand &MO = FirstMI->getOperand(i);
145 unsigned Reg = MO.getReg();
148 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
149 if (LocalDefSet.count(Reg)) {
150 MO.setIsInternalRead();
152 // Internal def is now killed.
153 KilledDefSet.insert(Reg);
155 if (ExternUseSet.insert(Reg).second) {
156 ExternUses.push_back(Reg);
158 UndefUseSet.insert(Reg);
161 // External def is now killed.
162 KilledUseSet.insert(Reg);
166 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
167 MachineOperand &MO = *Defs[i];
168 unsigned Reg = MO.getReg();
172 if (LocalDefSet.insert(Reg).second) {
173 LocalDefs.push_back(Reg);
175 DeadDefSet.insert(Reg);
178 // Re-defined inside the bundle, it's no longer killed.
179 KilledDefSet.erase(Reg);
181 // Previously defined but dead.
182 DeadDefSet.erase(Reg);
186 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
187 unsigned SubReg = *SubRegs;
188 if (LocalDefSet.insert(SubReg).second)
189 LocalDefs.push_back(SubReg);
197 SmallSet<unsigned, 32> Added;
198 for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) {
199 unsigned Reg = LocalDefs[i];
200 if (Added.insert(Reg).second) {
201 // If it's not live beyond end of the bundle, mark it dead.
202 bool isDead = DeadDefSet.count(Reg) || KilledDefSet.count(Reg);
203 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
204 getImplRegState(true));
208 for (unsigned i = 0, e = ExternUses.size(); i != e; ++i) {
209 unsigned Reg = ExternUses[i];
210 bool isKill = KilledUseSet.count(Reg);
211 bool isUndef = UndefUseSet.count(Reg);
212 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
213 getImplRegState(true));
217 /// finalizeBundle - Same functionality as the previous finalizeBundle except
218 /// the last instruction in the bundle is not provided as an input. This is
219 /// used in cases where bundles are pre-determined by marking instructions
220 /// with 'InsideBundle' marker. It returns the MBB instruction iterator that
221 /// points to the end of the bundle.
222 MachineBasicBlock::instr_iterator
223 llvm::finalizeBundle(MachineBasicBlock &MBB,
224 MachineBasicBlock::instr_iterator FirstMI) {
225 MachineBasicBlock::instr_iterator E = MBB.instr_end();
226 MachineBasicBlock::instr_iterator LastMI = std::next(FirstMI);
227 while (LastMI != E && LastMI->isInsideBundle())
229 finalizeBundle(MBB, FirstMI, LastMI);
233 /// finalizeBundles - Finalize instruction bundles in the specified
234 /// MachineFunction. Return true if any bundles are finalized.
235 bool llvm::finalizeBundles(MachineFunction &MF) {
236 bool Changed = false;
237 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
238 MachineBasicBlock &MBB = *I;
239 MachineBasicBlock::instr_iterator MII = MBB.instr_begin();
240 MachineBasicBlock::instr_iterator MIE = MBB.instr_end();
243 assert(!MII->isInsideBundle() &&
244 "First instr cannot be inside bundle before finalization!");
246 for (++MII; MII != MIE; ) {
247 if (!MII->isInsideBundle())
250 MII = finalizeBundle(MBB, std::prev(MII));
259 //===----------------------------------------------------------------------===//
260 // MachineOperand iterator
261 //===----------------------------------------------------------------------===//
263 MachineOperandIteratorBase::VirtRegInfo
264 MachineOperandIteratorBase::analyzeVirtReg(unsigned Reg,
265 SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops) {
266 VirtRegInfo RI = { false, false, false };
267 for(; isValid(); ++*this) {
268 MachineOperand &MO = deref();
269 if (!MO.isReg() || MO.getReg() != Reg)
272 // Remember each (MI, OpNo) that refers to Reg.
274 Ops->push_back(std::make_pair(MO.getParent(), getOperandNo()));
276 // Both defs and uses can read virtual registers.
283 // Only defs can write.
286 else if (!RI.Tied && MO.getParent()->isRegTiedToDefOperand(getOperandNo()))
292 MachineOperandIteratorBase::PhysRegInfo
293 MachineOperandIteratorBase::analyzePhysReg(unsigned Reg,
294 const TargetRegisterInfo *TRI) {
295 bool AllDefsDead = true;
296 PhysRegInfo PRI = {false, false, false, false, false, false, false};
298 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
299 "analyzePhysReg not given a physical register!");
300 for (; isValid(); ++*this) {
301 MachineOperand &MO = deref();
303 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) {
304 PRI.Clobbered = true;
311 unsigned MOReg = MO.getReg();
312 if (!MOReg || !TargetRegisterInfo::isPhysicalRegister(MOReg))
315 if (!TRI->regsOverlap(MOReg, Reg))
318 bool Covered = TRI->isSuperRegisterEq(Reg, MOReg);
322 PRI.FullyRead = true;
326 } else if (MO.isDef()) {
329 PRI.FullyDefined = true;
335 if (AllDefsDead && PRI.FullyDefined)