1 //===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs loop invariant code motion on machine instructions. We
11 // attempt to remove as much code from the body of a loop as possible.
13 // This pass does not attempt to throttle itself to limit register pressure.
14 // The register allocation phases are expected to perform rematerialization
15 // to recover when register pressure is high.
17 // This pass is not intended to be a replacement or a complete alternative
18 // for the LLVM-IR-level LICM pass. It is only designed to hoist simple
19 // constructs that are not exposed before lowering and instruction selection.
21 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "machine-licm"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/PseudoSourceValue.h"
31 #include "llvm/MC/MCInstrItineraries.h"
32 #include "llvm/Target/TargetLowering.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Analysis/AliasAnalysis.h"
37 #include "llvm/ADT/DenseMap.h"
38 #include "llvm/ADT/SmallSet.h"
39 #include "llvm/ADT/Statistic.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/raw_ostream.h"
46 AvoidSpeculation("avoid-speculation",
47 cl::desc("MachineLICM should avoid speculation"),
48 cl::init(true), cl::Hidden);
51 "Number of machine instructions hoisted out of loops");
53 "Number of instructions hoisted in low reg pressure situation");
54 STATISTIC(NumHighLatency,
55 "Number of high latency instructions hoisted");
57 "Number of hoisted machine instructions CSEed");
58 STATISTIC(NumPostRAHoisted,
59 "Number of machine instructions hoisted out of loops post regalloc");
62 class MachineLICM : public MachineFunctionPass {
65 const TargetMachine *TM;
66 const TargetInstrInfo *TII;
67 const TargetLowering *TLI;
68 const TargetRegisterInfo *TRI;
69 const MachineFrameInfo *MFI;
70 MachineRegisterInfo *MRI;
71 const InstrItineraryData *InstrItins;
73 // Various analyses that we use...
74 AliasAnalysis *AA; // Alias analysis info.
75 MachineLoopInfo *MLI; // Current MachineLoopInfo
76 MachineDominatorTree *DT; // Machine dominator tree for the cur loop
78 // State that is updated as we process loops
79 bool Changed; // True if a loop is changed.
80 bool FirstInLoop; // True if it's the first LICM in the loop.
81 MachineLoop *CurLoop; // The current loop we are working on.
82 MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
84 BitVector AllocatableSet;
86 // Track 'estimated' register pressure.
87 SmallSet<unsigned, 32> RegSeen;
88 SmallVector<unsigned, 8> RegPressure;
90 // Register pressure "limit" per register class. If the pressure
91 // is higher than the limit, then it's considered high.
92 SmallVector<unsigned, 8> RegLimit;
94 // Register pressure on path leading from loop preheader to current BB.
95 SmallVector<SmallVector<unsigned, 8>, 16> BackTrace;
97 // For each opcode, keep a list of potential CSE instructions.
98 DenseMap<unsigned, std::vector<const MachineInstr*> > CSEMap;
106 // If a MBB does not dominate loop exiting blocks then it may not safe
107 // to hoist loads from this block.
108 // Tri-state: 0 - false, 1 - true, 2 - unknown
109 unsigned SpeculationState;
112 static char ID; // Pass identification, replacement for typeid
114 MachineFunctionPass(ID), PreRegAlloc(true) {
115 initializeMachineLICMPass(*PassRegistry::getPassRegistry());
118 explicit MachineLICM(bool PreRA) :
119 MachineFunctionPass(ID), PreRegAlloc(PreRA) {
120 initializeMachineLICMPass(*PassRegistry::getPassRegistry());
123 virtual bool runOnMachineFunction(MachineFunction &MF);
125 const char *getPassName() const { return "Machine Instruction LICM"; }
127 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
128 AU.addRequired<MachineLoopInfo>();
129 AU.addRequired<MachineDominatorTree>();
130 AU.addRequired<AliasAnalysis>();
131 AU.addPreserved<MachineLoopInfo>();
132 AU.addPreserved<MachineDominatorTree>();
133 MachineFunctionPass::getAnalysisUsage(AU);
136 virtual void releaseMemory() {
141 for (DenseMap<unsigned,std::vector<const MachineInstr*> >::iterator
142 CI = CSEMap.begin(), CE = CSEMap.end(); CI != CE; ++CI)
148 /// CandidateInfo - Keep track of information about hoisting candidates.
149 struct CandidateInfo {
153 CandidateInfo(MachineInstr *mi, unsigned def, int fi)
154 : MI(mi), Def(def), FI(fi) {}
157 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
158 /// invariants out to the preheader.
159 void HoistRegionPostRA();
161 /// HoistPostRA - When an instruction is found to only use loop invariant
162 /// operands that is safe to hoist, this instruction is called to do the
164 void HoistPostRA(MachineInstr *MI, unsigned Def);
166 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
167 /// gather register def and frame object update information.
168 void ProcessMI(MachineInstr *MI, unsigned *PhysRegDefs,
169 SmallSet<int, 32> &StoredFIs,
170 SmallVector<CandidateInfo, 32> &Candidates);
172 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the
174 void AddToLiveIns(unsigned Reg);
176 /// IsLICMCandidate - Returns true if the instruction may be a suitable
177 /// candidate for LICM. e.g. If the instruction is a call, then it's
178 /// obviously not safe to hoist it.
179 bool IsLICMCandidate(MachineInstr &I);
181 /// IsLoopInvariantInst - Returns true if the instruction is loop
182 /// invariant. I.e., all virtual register operands are defined outside of
183 /// the loop, physical registers aren't accessed (explicitly or implicitly),
184 /// and the instruction is hoistable.
186 bool IsLoopInvariantInst(MachineInstr &I);
188 /// HasAnyPHIUse - Return true if the specified register is used by any
190 bool HasAnyPHIUse(unsigned Reg) const;
192 /// HasHighOperandLatency - Compute operand latency between a def of 'Reg'
193 /// and an use in the current loop, return true if the target considered
195 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
198 bool IsCheapInstruction(MachineInstr &MI) const;
200 /// CanCauseHighRegPressure - Visit BBs from header to current BB,
201 /// check if hoisting an instruction of the given cost matrix can cause high
202 /// register pressure.
203 bool CanCauseHighRegPressure(DenseMap<unsigned, int> &Cost);
205 /// UpdateBackTraceRegPressure - Traverse the back trace from header to
206 /// the current block and update their register pressures to reflect the
207 /// effect of hoisting MI from the current block to the preheader.
208 void UpdateBackTraceRegPressure(const MachineInstr *MI);
210 /// IsProfitableToHoist - Return true if it is potentially profitable to
211 /// hoist the given loop invariant.
212 bool IsProfitableToHoist(MachineInstr &MI);
214 /// IsGuaranteedToExecute - Check if this mbb is guaranteed to execute.
215 /// If not then a load from this mbb may not be safe to hoist.
216 bool IsGuaranteedToExecute(MachineBasicBlock *BB);
218 /// HoistRegion - Walk the specified region of the CFG (defined by all
219 /// blocks dominated by the specified block, and that are in the current
220 /// loop) in depth first order w.r.t the DominatorTree. This allows us to
221 /// visit definitions before uses, allowing us to hoist a loop body in one
222 /// pass without iteration.
224 void HoistRegion(MachineDomTreeNode *N, bool IsHeader = false);
226 /// getRegisterClassIDAndCost - For a given MI, register, and the operand
227 /// index, return the ID and cost of its representative register class by
229 void getRegisterClassIDAndCost(const MachineInstr *MI,
230 unsigned Reg, unsigned OpIdx,
231 unsigned &RCId, unsigned &RCCost) const;
233 /// InitRegPressure - Find all virtual register references that are liveout
234 /// of the preheader to initialize the starting "register pressure". Note
235 /// this does not count live through (livein but not used) registers.
236 void InitRegPressure(MachineBasicBlock *BB);
238 /// UpdateRegPressure - Update estimate of register pressure after the
239 /// specified instruction.
240 void UpdateRegPressure(const MachineInstr *MI);
242 /// ExtractHoistableLoad - Unfold a load from the given machineinstr if
243 /// the load itself could be hoisted. Return the unfolded and hoistable
244 /// load, or null if the load couldn't be unfolded or if it wouldn't
246 MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
248 /// LookForDuplicate - Find an instruction amount PrevMIs that is a
249 /// duplicate of MI. Return this instruction if it's found.
250 const MachineInstr *LookForDuplicate(const MachineInstr *MI,
251 std::vector<const MachineInstr*> &PrevMIs);
253 /// EliminateCSE - Given a LICM'ed instruction, look for an instruction on
254 /// the preheader that compute the same value. If it's found, do a RAU on
255 /// with the definition of the existing instruction rather than hoisting
256 /// the instruction to the preheader.
257 bool EliminateCSE(MachineInstr *MI,
258 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI);
260 /// MayCSE - Return true if the given instruction will be CSE'd if it's
261 /// hoisted out of the loop.
262 bool MayCSE(MachineInstr *MI);
264 /// Hoist - When an instruction is found to only use loop invariant operands
265 /// that is safe to hoist, this instruction is called to do the dirty work.
266 /// It returns true if the instruction is hoisted.
267 bool Hoist(MachineInstr *MI, MachineBasicBlock *Preheader);
269 /// InitCSEMap - Initialize the CSE map with instructions that are in the
270 /// current loop preheader that may become duplicates of instructions that
271 /// are hoisted out of the loop.
272 void InitCSEMap(MachineBasicBlock *BB);
274 /// getCurPreheader - Get the preheader for the current loop, splitting
275 /// a critical edge if needed.
276 MachineBasicBlock *getCurPreheader();
278 } // end anonymous namespace
280 char MachineLICM::ID = 0;
281 INITIALIZE_PASS_BEGIN(MachineLICM, "machinelicm",
282 "Machine Loop Invariant Code Motion", false, false)
283 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
284 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
285 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
286 INITIALIZE_PASS_END(MachineLICM, "machinelicm",
287 "Machine Loop Invariant Code Motion", false, false)
289 FunctionPass *llvm::createMachineLICMPass(bool PreRegAlloc) {
290 return new MachineLICM(PreRegAlloc);
293 /// LoopIsOuterMostWithPredecessor - Test if the given loop is the outer-most
294 /// loop that has a unique predecessor.
295 static bool LoopIsOuterMostWithPredecessor(MachineLoop *CurLoop) {
296 // Check whether this loop even has a unique predecessor.
297 if (!CurLoop->getLoopPredecessor())
299 // Ok, now check to see if any of its outer loops do.
300 for (MachineLoop *L = CurLoop->getParentLoop(); L; L = L->getParentLoop())
301 if (L->getLoopPredecessor())
303 // None of them did, so this is the outermost with a unique predecessor.
307 bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
309 DEBUG(dbgs() << "******** Pre-regalloc Machine LICM: ");
311 DEBUG(dbgs() << "******** Post-regalloc Machine LICM: ");
312 DEBUG(dbgs() << MF.getFunction()->getName() << " ********\n");
314 Changed = FirstInLoop = false;
315 TM = &MF.getTarget();
316 TII = TM->getInstrInfo();
317 TLI = TM->getTargetLowering();
318 TRI = TM->getRegisterInfo();
319 MFI = MF.getFrameInfo();
320 MRI = &MF.getRegInfo();
321 InstrItins = TM->getInstrItineraryData();
322 AllocatableSet = TRI->getAllocatableSet(MF);
325 // Estimate register pressure during pre-regalloc pass.
326 unsigned NumRC = TRI->getNumRegClasses();
327 RegPressure.resize(NumRC);
328 std::fill(RegPressure.begin(), RegPressure.end(), 0);
329 RegLimit.resize(NumRC);
330 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
331 E = TRI->regclass_end(); I != E; ++I)
332 RegLimit[(*I)->getID()] = TRI->getRegPressureLimit(*I, MF);
335 // Get our Loop information...
336 MLI = &getAnalysis<MachineLoopInfo>();
337 DT = &getAnalysis<MachineDominatorTree>();
338 AA = &getAnalysis<AliasAnalysis>();
340 SmallVector<MachineLoop *, 8> Worklist(MLI->begin(), MLI->end());
341 while (!Worklist.empty()) {
342 CurLoop = Worklist.pop_back_val();
345 // If this is done before regalloc, only visit outer-most preheader-sporting
347 if (PreRegAlloc && !LoopIsOuterMostWithPredecessor(CurLoop)) {
348 Worklist.append(CurLoop->begin(), CurLoop->end());
355 // CSEMap is initialized for loop header when the first instruction is
357 MachineDomTreeNode *N = DT->getNode(CurLoop->getHeader());
359 HoistRegion(N, true);
367 /// InstructionStoresToFI - Return true if instruction stores to the
369 static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
370 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
371 oe = MI->memoperands_end(); o != oe; ++o) {
372 if (!(*o)->isStore() || !(*o)->getValue())
374 if (const FixedStackPseudoSourceValue *Value =
375 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
376 if (Value->getFrameIndex() == FI)
383 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
384 /// gather register def and frame object update information.
385 void MachineLICM::ProcessMI(MachineInstr *MI,
386 unsigned *PhysRegDefs,
387 SmallSet<int, 32> &StoredFIs,
388 SmallVector<CandidateInfo, 32> &Candidates) {
389 bool RuledOut = false;
390 bool HasNonInvariantUse = false;
392 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
393 const MachineOperand &MO = MI->getOperand(i);
395 // Remember if the instruction stores to the frame index.
396 int FI = MO.getIndex();
397 if (!StoredFIs.count(FI) &&
398 MFI->isSpillSlotObjectIndex(FI) &&
399 InstructionStoresToFI(MI, FI))
400 StoredFIs.insert(FI);
401 HasNonInvariantUse = true;
407 unsigned Reg = MO.getReg();
410 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
411 "Not expecting virtual register!");
414 if (Reg && PhysRegDefs[Reg])
415 // If it's using a non-loop-invariant register, then it's obviously not
417 HasNonInvariantUse = true;
421 if (MO.isImplicit()) {
423 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
426 // Non-dead implicit def? This cannot be hoisted.
428 // No need to check if a dead implicit def is also defined by
429 // another instruction.
433 // FIXME: For now, avoid instructions with multiple defs, unless
434 // it's a dead implicit def.
440 // If we have already seen another instruction that defines the same
441 // register, then this is not safe.
442 if (++PhysRegDefs[Reg] > 1)
443 // MI defined register is seen defined by another instruction in
444 // the loop, it cannot be a LICM candidate.
446 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
447 if (++PhysRegDefs[*AS] > 1)
451 // Only consider reloads for now and remats which do not have register
452 // operands. FIXME: Consider unfold load folding instructions.
453 if (Def && !RuledOut) {
455 if ((!HasNonInvariantUse && IsLICMCandidate(*MI)) ||
456 (TII->isLoadFromStackSlot(MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
457 Candidates.push_back(CandidateInfo(MI, Def, FI));
461 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
462 /// invariants out to the preheader.
463 void MachineLICM::HoistRegionPostRA() {
464 unsigned NumRegs = TRI->getNumRegs();
465 unsigned *PhysRegDefs = new unsigned[NumRegs];
466 std::fill(PhysRegDefs, PhysRegDefs + NumRegs, 0);
468 SmallVector<CandidateInfo, 32> Candidates;
469 SmallSet<int, 32> StoredFIs;
471 // Walk the entire region, count number of defs for each register, and
472 // collect potential LICM candidates.
473 const std::vector<MachineBasicBlock*> Blocks = CurLoop->getBlocks();
474 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
475 MachineBasicBlock *BB = Blocks[i];
477 // If the header of the loop containing this basic block is a landing pad,
478 // then don't try to hoist instructions out of this loop.
479 const MachineLoop *ML = MLI->getLoopFor(BB);
480 if (ML && ML->getHeader()->isLandingPad()) continue;
482 // Conservatively treat live-in's as an external def.
483 // FIXME: That means a reload that're reused in successor block(s) will not
485 for (MachineBasicBlock::livein_iterator I = BB->livein_begin(),
486 E = BB->livein_end(); I != E; ++I) {
489 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
493 SpeculationState = SpeculateUnknown;
494 for (MachineBasicBlock::iterator
495 MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
496 MachineInstr *MI = &*MII;
497 ProcessMI(MI, PhysRegDefs, StoredFIs, Candidates);
501 // Now evaluate whether the potential candidates qualify.
502 // 1. Check if the candidate defined register is defined by another
503 // instruction in the loop.
504 // 2. If the candidate is a load from stack slot (always true for now),
505 // check if the slot is stored anywhere in the loop.
506 for (unsigned i = 0, e = Candidates.size(); i != e; ++i) {
507 if (Candidates[i].FI != INT_MIN &&
508 StoredFIs.count(Candidates[i].FI))
511 if (PhysRegDefs[Candidates[i].Def] == 1) {
513 MachineInstr *MI = Candidates[i].MI;
514 for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
515 const MachineOperand &MO = MI->getOperand(j);
516 if (!MO.isReg() || MO.isDef() || !MO.getReg())
518 if (PhysRegDefs[MO.getReg()]) {
519 // If it's using a non-loop-invariant register, then it's obviously
520 // not safe to hoist.
526 HoistPostRA(MI, Candidates[i].Def);
530 delete[] PhysRegDefs;
533 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the current
534 /// loop, and make sure it is not killed by any instructions in the loop.
535 void MachineLICM::AddToLiveIns(unsigned Reg) {
536 const std::vector<MachineBasicBlock*> Blocks = CurLoop->getBlocks();
537 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
538 MachineBasicBlock *BB = Blocks[i];
539 if (!BB->isLiveIn(Reg))
541 for (MachineBasicBlock::iterator
542 MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
543 MachineInstr *MI = &*MII;
544 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
545 MachineOperand &MO = MI->getOperand(i);
546 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
547 if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
554 /// HoistPostRA - When an instruction is found to only use loop invariant
555 /// operands that is safe to hoist, this instruction is called to do the
557 void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
558 MachineBasicBlock *Preheader = getCurPreheader();
559 if (!Preheader) return;
561 // Now move the instructions to the predecessor, inserting it before any
562 // terminator instructions.
564 dbgs() << "Hoisting " << *MI;
565 if (Preheader->getBasicBlock())
566 dbgs() << " to MachineBasicBlock "
567 << Preheader->getName();
568 if (MI->getParent()->getBasicBlock())
569 dbgs() << " from MachineBasicBlock "
570 << MI->getParent()->getName();
574 // Splice the instruction to the preheader.
575 MachineBasicBlock *MBB = MI->getParent();
576 Preheader->splice(Preheader->getFirstTerminator(), MBB, MI);
578 // Add register to livein list to all the BBs in the current loop since a
579 // loop invariant must be kept live throughout the whole loop. This is
580 // important to ensure later passes do not scavenge the def register.
587 // IsGuaranteedToExecute - Check if this mbb is guaranteed to execute.
588 // If not then a load from this mbb may not be safe to hoist.
589 bool MachineLICM::IsGuaranteedToExecute(MachineBasicBlock *BB) {
590 if (SpeculationState != SpeculateUnknown)
591 return SpeculationState == SpeculateFalse;
593 if (BB != CurLoop->getHeader()) {
594 // Check loop exiting blocks.
595 SmallVector<MachineBasicBlock*, 8> CurrentLoopExitingBlocks;
596 CurLoop->getExitingBlocks(CurrentLoopExitingBlocks);
597 for (unsigned i = 0, e = CurrentLoopExitingBlocks.size(); i != e; ++i)
598 if (!DT->dominates(BB, CurrentLoopExitingBlocks[i])) {
599 SpeculationState = SpeculateTrue;
604 SpeculationState = SpeculateFalse;
608 /// HoistRegion - Walk the specified region of the CFG (defined by all blocks
609 /// dominated by the specified block, and that are in the current loop) in depth
610 /// first order w.r.t the DominatorTree. This allows us to visit definitions
611 /// before uses, allowing us to hoist a loop body in one pass without iteration.
613 void MachineLICM::HoistRegion(MachineDomTreeNode *N, bool IsHeader) {
614 assert(N != 0 && "Null dominator tree node?");
615 MachineBasicBlock *BB = N->getBlock();
617 // If the header of the loop containing this basic block is a landing pad,
618 // then don't try to hoist instructions out of this loop.
619 const MachineLoop *ML = MLI->getLoopFor(BB);
620 if (ML && ML->getHeader()->isLandingPad()) return;
622 // If this subregion is not in the top level loop at all, exit.
623 if (!CurLoop->contains(BB)) return;
625 MachineBasicBlock *Preheader = getCurPreheader();
630 // Compute registers which are livein into the loop headers.
633 InitRegPressure(Preheader);
636 // Remember livein register pressure.
637 BackTrace.push_back(RegPressure);
639 SpeculationState = SpeculateUnknown;
640 for (MachineBasicBlock::iterator
641 MII = BB->begin(), E = BB->end(); MII != E; ) {
642 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
643 MachineInstr *MI = &*MII;
644 if (!Hoist(MI, Preheader))
645 UpdateRegPressure(MI);
649 // Don't hoist things out of a large switch statement. This often causes
650 // code to be hoisted that wasn't going to be executed, and increases
651 // register pressure in a situation where it's likely to matter.
652 if (BB->succ_size() < 25) {
653 const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
654 for (unsigned I = 0, E = Children.size(); I != E; ++I)
655 HoistRegion(Children[I]);
658 BackTrace.pop_back();
661 static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI) {
662 return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg());
665 /// getRegisterClassIDAndCost - For a given MI, register, and the operand
666 /// index, return the ID and cost of its representative register class.
668 MachineLICM::getRegisterClassIDAndCost(const MachineInstr *MI,
669 unsigned Reg, unsigned OpIdx,
670 unsigned &RCId, unsigned &RCCost) const {
671 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
672 EVT VT = *RC->vt_begin();
673 if (VT == MVT::Untyped) {
677 RCId = TLI->getRepRegClassFor(VT)->getID();
678 RCCost = TLI->getRepRegClassCostFor(VT);
682 /// InitRegPressure - Find all virtual register references that are liveout of
683 /// the preheader to initialize the starting "register pressure". Note this
684 /// does not count live through (livein but not used) registers.
685 void MachineLICM::InitRegPressure(MachineBasicBlock *BB) {
686 std::fill(RegPressure.begin(), RegPressure.end(), 0);
688 // If the preheader has only a single predecessor and it ends with a
689 // fallthrough or an unconditional branch, then scan its predecessor for live
690 // defs as well. This happens whenever the preheader is created by splitting
691 // the critical edge from the loop predecessor to the loop header.
692 if (BB->pred_size() == 1) {
693 MachineBasicBlock *TBB = 0, *FBB = 0;
694 SmallVector<MachineOperand, 4> Cond;
695 if (!TII->AnalyzeBranch(*BB, TBB, FBB, Cond, false) && Cond.empty())
696 InitRegPressure(*BB->pred_begin());
699 for (MachineBasicBlock::iterator MII = BB->begin(), E = BB->end();
701 MachineInstr *MI = &*MII;
702 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
703 const MachineOperand &MO = MI->getOperand(i);
704 if (!MO.isReg() || MO.isImplicit())
706 unsigned Reg = MO.getReg();
707 if (!TargetRegisterInfo::isVirtualRegister(Reg))
710 bool isNew = RegSeen.insert(Reg);
711 unsigned RCId, RCCost;
712 getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
714 RegPressure[RCId] += RCCost;
716 bool isKill = isOperandKill(MO, MRI);
717 if (isNew && !isKill)
718 // Haven't seen this, it must be a livein.
719 RegPressure[RCId] += RCCost;
720 else if (!isNew && isKill)
721 RegPressure[RCId] -= RCCost;
727 /// UpdateRegPressure - Update estimate of register pressure after the
728 /// specified instruction.
729 void MachineLICM::UpdateRegPressure(const MachineInstr *MI) {
730 if (MI->isImplicitDef())
733 SmallVector<unsigned, 4> Defs;
734 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
735 const MachineOperand &MO = MI->getOperand(i);
736 if (!MO.isReg() || MO.isImplicit())
738 unsigned Reg = MO.getReg();
739 if (!TargetRegisterInfo::isVirtualRegister(Reg))
742 bool isNew = RegSeen.insert(Reg);
745 else if (!isNew && isOperandKill(MO, MRI)) {
746 unsigned RCId, RCCost;
747 getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
748 if (RCCost > RegPressure[RCId])
749 RegPressure[RCId] = 0;
751 RegPressure[RCId] -= RCCost;
756 while (!Defs.empty()) {
757 unsigned Reg = Defs.pop_back_val();
758 unsigned RCId, RCCost;
759 getRegisterClassIDAndCost(MI, Reg, Idx, RCId, RCCost);
760 RegPressure[RCId] += RCCost;
765 /// isLoadFromGOTOrConstantPool - Return true if this machine instruction
766 /// loads from global offset table or constant pool.
767 static bool isLoadFromGOTOrConstantPool(MachineInstr &MI) {
768 assert (MI.mayLoad() && "Expected MI that loads!");
769 for (MachineInstr::mmo_iterator I = MI.memoperands_begin(),
770 E = MI.memoperands_end(); I != E; ++I) {
771 if (const Value *V = (*I)->getValue()) {
772 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
773 if (PSV == PSV->getGOT() || PSV == PSV->getConstantPool())
780 /// IsLICMCandidate - Returns true if the instruction may be a suitable
781 /// candidate for LICM. e.g. If the instruction is a call, then it's obviously
782 /// not safe to hoist it.
783 bool MachineLICM::IsLICMCandidate(MachineInstr &I) {
784 // Check if it's safe to move the instruction.
785 bool DontMoveAcrossStore = true;
786 if (!I.isSafeToMove(TII, AA, DontMoveAcrossStore))
789 // If it is load then check if it is guaranteed to execute by making sure that
790 // it dominates all exiting blocks. If it doesn't, then there is a path out of
791 // the loop which does not execute this load, so we can't hoist it. Loads
792 // from constant memory are not safe to speculate all the time, for example
793 // indexed load from a jump table.
794 // Stores and side effects are already checked by isSafeToMove.
795 if (I.mayLoad() && !isLoadFromGOTOrConstantPool(I) &&
796 !IsGuaranteedToExecute(I.getParent()))
802 /// IsLoopInvariantInst - Returns true if the instruction is loop
803 /// invariant. I.e., all virtual register operands are defined outside of the
804 /// loop, physical registers aren't accessed explicitly, and there are no side
805 /// effects that aren't captured by the operands or other flags.
807 bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
808 if (!IsLICMCandidate(I))
811 // The instruction is loop invariant if all of its operands are.
812 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
813 const MachineOperand &MO = I.getOperand(i);
818 unsigned Reg = MO.getReg();
819 if (Reg == 0) continue;
821 // Don't hoist an instruction that uses or defines a physical register.
822 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
824 // If the physreg has no defs anywhere, it's just an ambient register
825 // and we can freely move its uses. Alternatively, if it's allocatable,
826 // it could get allocated to something with a def during allocation.
827 if (!MRI->def_empty(Reg))
829 if (AllocatableSet.test(Reg))
831 // Check for a def among the register's aliases too.
832 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
833 unsigned AliasReg = *Alias;
834 if (!MRI->def_empty(AliasReg))
836 if (AllocatableSet.test(AliasReg))
839 // Otherwise it's safe to move.
841 } else if (!MO.isDead()) {
842 // A def that isn't dead. We can't move it.
844 } else if (CurLoop->getHeader()->isLiveIn(Reg)) {
845 // If the reg is live into the loop, we can't hoist an instruction
846 // which would clobber it.
854 assert(MRI->getVRegDef(Reg) &&
855 "Machine instr not mapped for this vreg?!");
857 // If the loop contains the definition of an operand, then the instruction
858 // isn't loop invariant.
859 if (CurLoop->contains(MRI->getVRegDef(Reg)))
863 // If we got this far, the instruction is loop invariant!
868 /// HasAnyPHIUse - Return true if the specified register is used by any
870 bool MachineLICM::HasAnyPHIUse(unsigned Reg) const {
871 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
872 UE = MRI->use_end(); UI != UE; ++UI) {
873 MachineInstr *UseMI = &*UI;
876 // Look pass copies as well.
877 if (UseMI->isCopy()) {
878 unsigned Def = UseMI->getOperand(0).getReg();
879 if (TargetRegisterInfo::isVirtualRegister(Def) &&
887 /// HasHighOperandLatency - Compute operand latency between a def of 'Reg'
888 /// and an use in the current loop, return true if the target considered
890 bool MachineLICM::HasHighOperandLatency(MachineInstr &MI,
891 unsigned DefIdx, unsigned Reg) const {
892 if (!InstrItins || InstrItins->isEmpty() || MRI->use_nodbg_empty(Reg))
895 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
896 E = MRI->use_nodbg_end(); I != E; ++I) {
897 MachineInstr *UseMI = &*I;
898 if (UseMI->isCopyLike())
900 if (!CurLoop->contains(UseMI->getParent()))
902 for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
903 const MachineOperand &MO = UseMI->getOperand(i);
904 if (!MO.isReg() || !MO.isUse())
906 unsigned MOReg = MO.getReg();
910 if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, UseMI, i))
914 // Only look at the first in loop use.
921 /// IsCheapInstruction - Return true if the instruction is marked "cheap" or
922 /// the operand latency between its def and a use is one or less.
923 bool MachineLICM::IsCheapInstruction(MachineInstr &MI) const {
924 if (MI.isAsCheapAsAMove() || MI.isCopyLike())
926 if (!InstrItins || InstrItins->isEmpty())
929 bool isCheap = false;
930 unsigned NumDefs = MI.getDesc().getNumDefs();
931 for (unsigned i = 0, e = MI.getNumOperands(); NumDefs && i != e; ++i) {
932 MachineOperand &DefMO = MI.getOperand(i);
933 if (!DefMO.isReg() || !DefMO.isDef())
936 unsigned Reg = DefMO.getReg();
937 if (TargetRegisterInfo::isPhysicalRegister(Reg))
940 if (!TII->hasLowDefLatency(InstrItins, &MI, i))
948 /// CanCauseHighRegPressure - Visit BBs from header to current BB, check
949 /// if hoisting an instruction of the given cost matrix can cause high
950 /// register pressure.
951 bool MachineLICM::CanCauseHighRegPressure(DenseMap<unsigned, int> &Cost) {
952 for (DenseMap<unsigned, int>::iterator CI = Cost.begin(), CE = Cost.end();
957 unsigned RCId = CI->first;
958 for (unsigned i = BackTrace.size(); i != 0; --i) {
959 SmallVector<unsigned, 8> &RP = BackTrace[i-1];
960 if (RP[RCId] + CI->second >= RegLimit[RCId])
968 /// UpdateBackTraceRegPressure - Traverse the back trace from header to the
969 /// current block and update their register pressures to reflect the effect
970 /// of hoisting MI from the current block to the preheader.
971 void MachineLICM::UpdateBackTraceRegPressure(const MachineInstr *MI) {
972 if (MI->isImplicitDef())
975 // First compute the 'cost' of the instruction, i.e. its contribution
976 // to register pressure.
977 DenseMap<unsigned, int> Cost;
978 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
979 const MachineOperand &MO = MI->getOperand(i);
980 if (!MO.isReg() || MO.isImplicit())
982 unsigned Reg = MO.getReg();
983 if (!TargetRegisterInfo::isVirtualRegister(Reg))
986 unsigned RCId, RCCost;
987 getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
989 DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
990 if (CI != Cost.end())
991 CI->second += RCCost;
993 Cost.insert(std::make_pair(RCId, RCCost));
994 } else if (isOperandKill(MO, MRI)) {
995 DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
996 if (CI != Cost.end())
997 CI->second -= RCCost;
999 Cost.insert(std::make_pair(RCId, -RCCost));
1003 // Update register pressure of blocks from loop header to current block.
1004 for (unsigned i = 0, e = BackTrace.size(); i != e; ++i) {
1005 SmallVector<unsigned, 8> &RP = BackTrace[i];
1006 for (DenseMap<unsigned, int>::iterator CI = Cost.begin(), CE = Cost.end();
1008 unsigned RCId = CI->first;
1009 RP[RCId] += CI->second;
1014 /// IsProfitableToHoist - Return true if it is potentially profitable to hoist
1015 /// the given loop invariant.
1016 bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
1017 if (MI.isImplicitDef())
1020 // If the instruction is cheap, only hoist if it is re-materilizable. LICM
1021 // will increase register pressure. It's probably not worth it if the
1022 // instruction is cheap.
1023 // Also hoist loads from constant memory, e.g. load from stubs, GOT. Hoisting
1024 // these tend to help performance in low register pressure situation. The
1025 // trade off is it may cause spill in high pressure situation. It will end up
1026 // adding a store in the loop preheader. But the reload is no more expensive.
1027 // The side benefit is these loads are frequently CSE'ed.
1028 if (IsCheapInstruction(MI)) {
1029 if (!TII->isTriviallyReMaterializable(&MI, AA))
1032 // Estimate register pressure to determine whether to LICM the instruction.
1033 // In low register pressure situation, we can be more aggressive about
1034 // hoisting. Also, favors hoisting long latency instructions even in
1035 // moderately high pressure situation.
1036 // FIXME: If there are long latency loop-invariant instructions inside the
1037 // loop at this point, why didn't the optimizer's LICM hoist them?
1038 DenseMap<unsigned, int> Cost;
1039 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
1040 const MachineOperand &MO = MI.getOperand(i);
1041 if (!MO.isReg() || MO.isImplicit())
1043 unsigned Reg = MO.getReg();
1044 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1047 unsigned RCId, RCCost;
1048 getRegisterClassIDAndCost(&MI, Reg, i, RCId, RCCost);
1050 if (HasHighOperandLatency(MI, i, Reg)) {
1055 DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
1056 if (CI != Cost.end())
1057 CI->second += RCCost;
1059 Cost.insert(std::make_pair(RCId, RCCost));
1060 } else if (isOperandKill(MO, MRI)) {
1061 // Is a virtual register use is a kill, hoisting it out of the loop
1062 // may actually reduce register pressure or be register pressure
1064 DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
1065 if (CI != Cost.end())
1066 CI->second -= RCCost;
1068 Cost.insert(std::make_pair(RCId, -RCCost));
1072 // Visit BBs from header to current BB, if hoisting this doesn't cause
1073 // high register pressure, then it's safe to proceed.
1074 if (!CanCauseHighRegPressure(Cost)) {
1079 // Do not "speculate" in high register pressure situation. If an
1080 // instruction is not guaranteed to be executed in the loop, it's best to be
1082 if (AvoidSpeculation &&
1083 (!IsGuaranteedToExecute(MI.getParent()) && !MayCSE(&MI)))
1086 // High register pressure situation, only hoist if the instruction is going to
1088 if (!TII->isTriviallyReMaterializable(&MI, AA) &&
1089 !MI.isInvariantLoad(AA))
1093 // If result(s) of this instruction is used by PHIs outside of the loop, then
1094 // don't hoist it if the instruction because it will introduce an extra copy.
1095 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1096 const MachineOperand &MO = MI.getOperand(i);
1097 if (!MO.isReg() || !MO.isDef())
1099 if (HasAnyPHIUse(MO.getReg()))
1106 MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
1107 // Don't unfold simple loads.
1108 if (MI->canFoldAsLoad())
1111 // If not, we may be able to unfold a load and hoist that.
1112 // First test whether the instruction is loading from an amenable
1114 if (!MI->isInvariantLoad(AA))
1117 // Next determine the register class for a temporary register.
1118 unsigned LoadRegIndex;
1120 TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(),
1121 /*UnfoldLoad=*/true,
1122 /*UnfoldStore=*/false,
1124 if (NewOpc == 0) return 0;
1125 const MCInstrDesc &MID = TII->get(NewOpc);
1126 if (MID.getNumDefs() != 1) return 0;
1127 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI);
1128 // Ok, we're unfolding. Create a temporary register and do the unfold.
1129 unsigned Reg = MRI->createVirtualRegister(RC);
1131 MachineFunction &MF = *MI->getParent()->getParent();
1132 SmallVector<MachineInstr *, 2> NewMIs;
1134 TII->unfoldMemoryOperand(MF, MI, Reg,
1135 /*UnfoldLoad=*/true, /*UnfoldStore=*/false,
1139 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
1141 assert(NewMIs.size() == 2 &&
1142 "Unfolded a load into multiple instructions!");
1143 MachineBasicBlock *MBB = MI->getParent();
1144 MachineBasicBlock::iterator Pos = MI;
1145 MBB->insert(Pos, NewMIs[0]);
1146 MBB->insert(Pos, NewMIs[1]);
1147 // If unfolding produced a load that wasn't loop-invariant or profitable to
1148 // hoist, discard the new instructions and bail.
1149 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
1150 NewMIs[0]->eraseFromParent();
1151 NewMIs[1]->eraseFromParent();
1155 // Update register pressure for the unfolded instruction.
1156 UpdateRegPressure(NewMIs[1]);
1158 // Otherwise we successfully unfolded a load that we can hoist.
1159 MI->eraseFromParent();
1163 void MachineLICM::InitCSEMap(MachineBasicBlock *BB) {
1164 for (MachineBasicBlock::iterator I = BB->begin(),E = BB->end(); I != E; ++I) {
1165 const MachineInstr *MI = &*I;
1166 unsigned Opcode = MI->getOpcode();
1167 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
1168 CI = CSEMap.find(Opcode);
1169 if (CI != CSEMap.end())
1170 CI->second.push_back(MI);
1172 std::vector<const MachineInstr*> CSEMIs;
1173 CSEMIs.push_back(MI);
1174 CSEMap.insert(std::make_pair(Opcode, CSEMIs));
1180 MachineLICM::LookForDuplicate(const MachineInstr *MI,
1181 std::vector<const MachineInstr*> &PrevMIs) {
1182 for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) {
1183 const MachineInstr *PrevMI = PrevMIs[i];
1184 if (TII->produceSameValue(MI, PrevMI, (PreRegAlloc ? MRI : 0)))
1190 bool MachineLICM::EliminateCSE(MachineInstr *MI,
1191 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI) {
1192 // Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
1193 // the undef property onto uses.
1194 if (CI == CSEMap.end() || MI->isImplicitDef())
1197 if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
1198 DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
1200 // Replace virtual registers defined by MI by their counterparts defined
1202 SmallVector<unsigned, 2> Defs;
1203 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1204 const MachineOperand &MO = MI->getOperand(i);
1206 // Physical registers may not differ here.
1207 assert((!MO.isReg() || MO.getReg() == 0 ||
1208 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
1209 MO.getReg() == Dup->getOperand(i).getReg()) &&
1210 "Instructions with different phys regs are not identical!");
1212 if (MO.isReg() && MO.isDef() &&
1213 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1217 SmallVector<const TargetRegisterClass*, 2> OrigRCs;
1218 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
1219 unsigned Idx = Defs[i];
1220 unsigned Reg = MI->getOperand(Idx).getReg();
1221 unsigned DupReg = Dup->getOperand(Idx).getReg();
1222 OrigRCs.push_back(MRI->getRegClass(DupReg));
1224 if (!MRI->constrainRegClass(DupReg, MRI->getRegClass(Reg))) {
1225 // Restore old RCs if more than one defs.
1226 for (unsigned j = 0; j != i; ++j)
1227 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]);
1232 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
1233 unsigned Idx = Defs[i];
1234 unsigned Reg = MI->getOperand(Idx).getReg();
1235 unsigned DupReg = Dup->getOperand(Idx).getReg();
1236 MRI->replaceRegWith(Reg, DupReg);
1237 MRI->clearKillFlags(DupReg);
1240 MI->eraseFromParent();
1247 /// MayCSE - Return true if the given instruction will be CSE'd if it's
1248 /// hoisted out of the loop.
1249 bool MachineLICM::MayCSE(MachineInstr *MI) {
1250 unsigned Opcode = MI->getOpcode();
1251 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
1252 CI = CSEMap.find(Opcode);
1253 // Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
1254 // the undef property onto uses.
1255 if (CI == CSEMap.end() || MI->isImplicitDef())
1258 return LookForDuplicate(MI, CI->second) != 0;
1261 /// Hoist - When an instruction is found to use only loop invariant operands
1262 /// that are safe to hoist, this instruction is called to do the dirty work.
1264 bool MachineLICM::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
1265 // First check whether we should hoist this instruction.
1266 if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
1267 // If not, try unfolding a hoistable load.
1268 MI = ExtractHoistableLoad(MI);
1269 if (!MI) return false;
1272 // Now move the instructions to the predecessor, inserting it before any
1273 // terminator instructions.
1275 dbgs() << "Hoisting " << *MI;
1276 if (Preheader->getBasicBlock())
1277 dbgs() << " to MachineBasicBlock "
1278 << Preheader->getName();
1279 if (MI->getParent()->getBasicBlock())
1280 dbgs() << " from MachineBasicBlock "
1281 << MI->getParent()->getName();
1285 // If this is the first instruction being hoisted to the preheader,
1286 // initialize the CSE map with potential common expressions.
1288 InitCSEMap(Preheader);
1289 FirstInLoop = false;
1292 // Look for opportunity to CSE the hoisted instruction.
1293 unsigned Opcode = MI->getOpcode();
1294 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
1295 CI = CSEMap.find(Opcode);
1296 if (!EliminateCSE(MI, CI)) {
1297 // Otherwise, splice the instruction to the preheader.
1298 Preheader->splice(Preheader->getFirstTerminator(),MI->getParent(),MI);
1300 // Update register pressure for BBs from header to this block.
1301 UpdateBackTraceRegPressure(MI);
1303 // Clear the kill flags of any register this instruction defines,
1304 // since they may need to be live throughout the entire loop
1305 // rather than just live for part of it.
1306 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1307 MachineOperand &MO = MI->getOperand(i);
1308 if (MO.isReg() && MO.isDef() && !MO.isDead())
1309 MRI->clearKillFlags(MO.getReg());
1312 // Add to the CSE map.
1313 if (CI != CSEMap.end())
1314 CI->second.push_back(MI);
1316 std::vector<const MachineInstr*> CSEMIs;
1317 CSEMIs.push_back(MI);
1318 CSEMap.insert(std::make_pair(Opcode, CSEMIs));
1328 MachineBasicBlock *MachineLICM::getCurPreheader() {
1329 // Determine the block to which to hoist instructions. If we can't find a
1330 // suitable loop predecessor, we can't do any hoisting.
1332 // If we've tried to get a preheader and failed, don't try again.
1333 if (CurPreheader == reinterpret_cast<MachineBasicBlock *>(-1))
1336 if (!CurPreheader) {
1337 CurPreheader = CurLoop->getLoopPreheader();
1338 if (!CurPreheader) {
1339 MachineBasicBlock *Pred = CurLoop->getLoopPredecessor();
1341 CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
1345 CurPreheader = Pred->SplitCriticalEdge(CurLoop->getHeader(), this);
1346 if (!CurPreheader) {
1347 CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
1352 return CurPreheader;