1 //===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs loop invariant code motion on machine instructions. We
11 // attempt to remove as much code from the body of a loop as possible.
13 // This pass does not attempt to throttle itself to limit register pressure.
14 // The register allocation phases are expected to perform rematerialization
15 // to recover when register pressure is high.
17 // This pass is not intended to be a replacement or a complete alternative
18 // for the LLVM-IR-level LICM pass. It is only designed to hoist simple
19 // constructs that are not exposed before lowering and instruction selection.
21 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "machine-licm"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/PseudoSourceValue.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Analysis/AliasAnalysis.h"
35 #include "llvm/ADT/DenseMap.h"
36 #include "llvm/ADT/SmallSet.h"
37 #include "llvm/ADT/Statistic.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops");
44 STATISTIC(NumCSEed, "Number of hoisted machine instructions CSEed");
45 STATISTIC(NumPostRAHoisted,
46 "Number of machine instructions hoisted out of loops post regalloc");
49 class MachineLICM : public MachineFunctionPass {
52 const TargetMachine *TM;
53 const TargetInstrInfo *TII;
54 const TargetRegisterInfo *TRI;
55 const MachineFrameInfo *MFI;
56 MachineRegisterInfo *RegInfo;
58 // Various analyses that we use...
59 AliasAnalysis *AA; // Alias analysis info.
60 MachineLoopInfo *MLI; // Current MachineLoopInfo
61 MachineDominatorTree *DT; // Machine dominator tree for the cur loop
63 // State that is updated as we process loops
64 bool Changed; // True if a loop is changed.
65 bool FirstInLoop; // True if it's the first LICM in the loop.
66 MachineLoop *CurLoop; // The current loop we are working on.
67 MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
69 BitVector AllocatableSet;
71 // For each opcode, keep a list of potentail CSE instructions.
72 DenseMap<unsigned, std::vector<const MachineInstr*> > CSEMap;
75 static char ID; // Pass identification, replacement for typeid
77 MachineFunctionPass(&ID), PreRegAlloc(true) {}
79 explicit MachineLICM(bool PreRA) :
80 MachineFunctionPass(&ID), PreRegAlloc(PreRA) {}
82 virtual bool runOnMachineFunction(MachineFunction &MF);
84 const char *getPassName() const { return "Machine Instruction LICM"; }
86 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
88 AU.addRequired<MachineLoopInfo>();
89 AU.addRequired<MachineDominatorTree>();
90 AU.addRequired<AliasAnalysis>();
91 AU.addPreserved<MachineLoopInfo>();
92 AU.addPreserved<MachineDominatorTree>();
93 MachineFunctionPass::getAnalysisUsage(AU);
96 virtual void releaseMemory() {
101 /// CandidateInfo - Keep track of information about hoisting candidates.
102 struct CandidateInfo {
106 CandidateInfo(MachineInstr *mi, unsigned def, int fi)
107 : MI(mi), Def(def), FI(fi) {}
110 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
111 /// invariants out to the preheader.
112 void HoistRegionPostRA();
114 /// HoistPostRA - When an instruction is found to only use loop invariant
115 /// operands that is safe to hoist, this instruction is called to do the
117 void HoistPostRA(MachineInstr *MI, unsigned Def);
119 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
120 /// gather register def and frame object update information.
121 void ProcessMI(MachineInstr *MI, unsigned *PhysRegDefs,
122 SmallSet<int, 32> &StoredFIs,
123 SmallVector<CandidateInfo, 32> &Candidates);
125 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the
127 void AddToLiveIns(unsigned Reg);
129 /// IsLICMCandidate - Returns true if the instruction may be a suitable
130 /// candidate for LICM. e.g. If the instruction is a call, then it's
131 /// obviously not safe to hoist it.
132 bool IsLICMCandidate(MachineInstr &I);
134 /// IsLoopInvariantInst - Returns true if the instruction is loop
135 /// invariant. I.e., all virtual register operands are defined outside of
136 /// the loop, physical registers aren't accessed (explicitly or implicitly),
137 /// and the instruction is hoistable.
139 bool IsLoopInvariantInst(MachineInstr &I);
141 /// IsProfitableToHoist - Return true if it is potentially profitable to
142 /// hoist the given loop invariant.
143 bool IsProfitableToHoist(MachineInstr &MI);
145 /// HoistRegion - Walk the specified region of the CFG (defined by all
146 /// blocks dominated by the specified block, and that are in the current
147 /// loop) in depth first order w.r.t the DominatorTree. This allows us to
148 /// visit definitions before uses, allowing us to hoist a loop body in one
149 /// pass without iteration.
151 void HoistRegion(MachineDomTreeNode *N);
153 /// isLoadFromConstantMemory - Return true if the given instruction is a
154 /// load from constant memory.
155 bool isLoadFromConstantMemory(MachineInstr *MI);
157 /// ExtractHoistableLoad - Unfold a load from the given machineinstr if
158 /// the load itself could be hoisted. Return the unfolded and hoistable
159 /// load, or null if the load couldn't be unfolded or if it wouldn't
161 MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
163 /// LookForDuplicate - Find an instruction amount PrevMIs that is a
164 /// duplicate of MI. Return this instruction if it's found.
165 const MachineInstr *LookForDuplicate(const MachineInstr *MI,
166 std::vector<const MachineInstr*> &PrevMIs);
168 /// EliminateCSE - Given a LICM'ed instruction, look for an instruction on
169 /// the preheader that compute the same value. If it's found, do a RAU on
170 /// with the definition of the existing instruction rather than hoisting
171 /// the instruction to the preheader.
172 bool EliminateCSE(MachineInstr *MI,
173 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI);
175 /// Hoist - When an instruction is found to only use loop invariant operands
176 /// that is safe to hoist, this instruction is called to do the dirty work.
178 void Hoist(MachineInstr *MI);
180 /// InitCSEMap - Initialize the CSE map with instructions that are in the
181 /// current loop preheader that may become duplicates of instructions that
182 /// are hoisted out of the loop.
183 void InitCSEMap(MachineBasicBlock *BB);
185 /// getCurPreheader - Get the preheader for the current loop, splitting
186 /// a critical edge if needed.
187 MachineBasicBlock *getCurPreheader();
189 } // end anonymous namespace
191 char MachineLICM::ID = 0;
192 static RegisterPass<MachineLICM>
193 X("machinelicm", "Machine Loop Invariant Code Motion");
195 FunctionPass *llvm::createMachineLICMPass(bool PreRegAlloc) {
196 return new MachineLICM(PreRegAlloc);
199 /// LoopIsOuterMostWithPredecessor - Test if the given loop is the outer-most
200 /// loop that has a unique predecessor.
201 static bool LoopIsOuterMostWithPredecessor(MachineLoop *CurLoop) {
202 // Check whether this loop even has a unique predecessor.
203 if (!CurLoop->getLoopPredecessor())
205 // Ok, now check to see if any of its outer loops do.
206 for (MachineLoop *L = CurLoop->getParentLoop(); L; L = L->getParentLoop())
207 if (L->getLoopPredecessor())
209 // None of them did, so this is the outermost with a unique predecessor.
213 bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
215 DEBUG(dbgs() << "******** Pre-regalloc Machine LICM ********\n");
217 DEBUG(dbgs() << "******** Post-regalloc Machine LICM ********\n");
219 Changed = FirstInLoop = false;
220 TM = &MF.getTarget();
221 TII = TM->getInstrInfo();
222 TRI = TM->getRegisterInfo();
223 MFI = MF.getFrameInfo();
224 RegInfo = &MF.getRegInfo();
225 AllocatableSet = TRI->getAllocatableSet(MF);
227 // Get our Loop information...
228 MLI = &getAnalysis<MachineLoopInfo>();
229 DT = &getAnalysis<MachineDominatorTree>();
230 AA = &getAnalysis<AliasAnalysis>();
232 SmallVector<MachineLoop *, 8> Worklist(MLI->begin(), MLI->end());
233 while (!Worklist.empty()) {
234 CurLoop = Worklist.pop_back_val();
237 // If this is done before regalloc, only visit outer-most preheader-sporting
239 if (PreRegAlloc && !LoopIsOuterMostWithPredecessor(CurLoop)) {
240 Worklist.append(CurLoop->begin(), CurLoop->end());
247 // CSEMap is initialized for loop header when the first instruction is
249 MachineDomTreeNode *N = DT->getNode(CurLoop->getHeader());
259 /// InstructionStoresToFI - Return true if instruction stores to the
261 static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
262 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
263 oe = MI->memoperands_end(); o != oe; ++o) {
264 if (!(*o)->isStore() || !(*o)->getValue())
266 if (const FixedStackPseudoSourceValue *Value =
267 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
268 if (Value->getFrameIndex() == FI)
275 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
276 /// gather register def and frame object update information.
277 void MachineLICM::ProcessMI(MachineInstr *MI,
278 unsigned *PhysRegDefs,
279 SmallSet<int, 32> &StoredFIs,
280 SmallVector<CandidateInfo, 32> &Candidates) {
281 bool RuledOut = false;
282 bool HasNonInvariantUse = false;
284 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
285 const MachineOperand &MO = MI->getOperand(i);
287 // Remember if the instruction stores to the frame index.
288 int FI = MO.getIndex();
289 if (!StoredFIs.count(FI) &&
290 MFI->isSpillSlotObjectIndex(FI) &&
291 InstructionStoresToFI(MI, FI))
292 StoredFIs.insert(FI);
293 HasNonInvariantUse = true;
299 unsigned Reg = MO.getReg();
302 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
303 "Not expecting virtual register!");
306 if (Reg && PhysRegDefs[Reg])
307 // If it's using a non-loop-invariant register, then it's obviously not
309 HasNonInvariantUse = true;
313 if (MO.isImplicit()) {
315 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
318 // Non-dead implicit def? This cannot be hoisted.
320 // No need to check if a dead implicit def is also defined by
321 // another instruction.
325 // FIXME: For now, avoid instructions with multiple defs, unless
326 // it's a dead implicit def.
332 // If we have already seen another instruction that defines the same
333 // register, then this is not safe.
334 if (++PhysRegDefs[Reg] > 1)
335 // MI defined register is seen defined by another instruction in
336 // the loop, it cannot be a LICM candidate.
338 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
339 if (++PhysRegDefs[*AS] > 1)
343 // Only consider reloads for now and remats which do not have register
344 // operands. FIXME: Consider unfold load folding instructions.
345 if (Def && !RuledOut) {
347 if ((!HasNonInvariantUse && IsLICMCandidate(*MI)) ||
348 (TII->isLoadFromStackSlot(MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
349 Candidates.push_back(CandidateInfo(MI, Def, FI));
353 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
354 /// invariants out to the preheader.
355 void MachineLICM::HoistRegionPostRA() {
356 unsigned NumRegs = TRI->getNumRegs();
357 unsigned *PhysRegDefs = new unsigned[NumRegs];
358 std::fill(PhysRegDefs, PhysRegDefs + NumRegs, 0);
360 SmallVector<CandidateInfo, 32> Candidates;
361 SmallSet<int, 32> StoredFIs;
363 // Walk the entire region, count number of defs for each register, and
364 // collect potential LICM candidates.
365 const std::vector<MachineBasicBlock*> Blocks = CurLoop->getBlocks();
366 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
367 MachineBasicBlock *BB = Blocks[i];
368 // Conservatively treat live-in's as an external def.
369 // FIXME: That means a reload that're reused in successor block(s) will not
371 for (MachineBasicBlock::livein_iterator I = BB->livein_begin(),
372 E = BB->livein_end(); I != E; ++I) {
375 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
379 for (MachineBasicBlock::iterator
380 MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
381 MachineInstr *MI = &*MII;
382 ProcessMI(MI, PhysRegDefs, StoredFIs, Candidates);
386 // Now evaluate whether the potential candidates qualify.
387 // 1. Check if the candidate defined register is defined by another
388 // instruction in the loop.
389 // 2. If the candidate is a load from stack slot (always true for now),
390 // check if the slot is stored anywhere in the loop.
391 for (unsigned i = 0, e = Candidates.size(); i != e; ++i) {
392 if (Candidates[i].FI != INT_MIN &&
393 StoredFIs.count(Candidates[i].FI))
396 if (PhysRegDefs[Candidates[i].Def] == 1) {
398 MachineInstr *MI = Candidates[i].MI;
399 for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
400 const MachineOperand &MO = MI->getOperand(j);
401 if (!MO.isReg() || MO.isDef() || !MO.getReg())
403 if (PhysRegDefs[MO.getReg()]) {
404 // If it's using a non-loop-invariant register, then it's obviously
405 // not safe to hoist.
411 HoistPostRA(MI, Candidates[i].Def);
415 delete[] PhysRegDefs;
418 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the current
419 /// loop, and make sure it is not killed by any instructions in the loop.
420 void MachineLICM::AddToLiveIns(unsigned Reg) {
421 const std::vector<MachineBasicBlock*> Blocks = CurLoop->getBlocks();
422 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
423 MachineBasicBlock *BB = Blocks[i];
424 if (!BB->isLiveIn(Reg))
426 for (MachineBasicBlock::iterator
427 MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
428 MachineInstr *MI = &*MII;
429 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
430 MachineOperand &MO = MI->getOperand(i);
431 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
432 if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
439 /// HoistPostRA - When an instruction is found to only use loop invariant
440 /// operands that is safe to hoist, this instruction is called to do the
442 void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
443 MachineBasicBlock *Preheader = getCurPreheader();
444 if (!Preheader) return;
446 // Now move the instructions to the predecessor, inserting it before any
447 // terminator instructions.
449 dbgs() << "Hoisting " << *MI;
450 if (Preheader->getBasicBlock())
451 dbgs() << " to MachineBasicBlock "
452 << Preheader->getName();
453 if (MI->getParent()->getBasicBlock())
454 dbgs() << " from MachineBasicBlock "
455 << MI->getParent()->getName();
459 // Splice the instruction to the preheader.
460 MachineBasicBlock *MBB = MI->getParent();
461 Preheader->splice(Preheader->getFirstTerminator(), MBB, MI);
463 // Add register to livein list to all the BBs in the current loop since a
464 // loop invariant must be kept live throughout the whole loop. This is
465 // important to ensure later passes do not scavenge the def register.
472 /// HoistRegion - Walk the specified region of the CFG (defined by all blocks
473 /// dominated by the specified block, and that are in the current loop) in depth
474 /// first order w.r.t the DominatorTree. This allows us to visit definitions
475 /// before uses, allowing us to hoist a loop body in one pass without iteration.
477 void MachineLICM::HoistRegion(MachineDomTreeNode *N) {
478 assert(N != 0 && "Null dominator tree node?");
479 MachineBasicBlock *BB = N->getBlock();
481 // If this subregion is not in the top level loop at all, exit.
482 if (!CurLoop->contains(BB)) return;
484 for (MachineBasicBlock::iterator
485 MII = BB->begin(), E = BB->end(); MII != E; ) {
486 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
491 const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
492 // Don't hoist things out of a large switch statement. This often causes
493 // code to be hoisted that wasn't going to be executed, and increases
494 // register pressure in a situation where it's likely to matter.
495 if (Children.size() < 10)
496 for (unsigned I = 0, E = Children.size(); I != E; ++I)
497 HoistRegion(Children[I]);
500 /// IsLICMCandidate - Returns true if the instruction may be a suitable
501 /// candidate for LICM. e.g. If the instruction is a call, then it's obviously
502 /// not safe to hoist it.
503 bool MachineLICM::IsLICMCandidate(MachineInstr &I) {
504 // Check if it's safe to move the instruction.
505 bool DontMoveAcrossStore = true;
506 if (!I.isSafeToMove(TII, AA, DontMoveAcrossStore))
512 /// IsLoopInvariantInst - Returns true if the instruction is loop
513 /// invariant. I.e., all virtual register operands are defined outside of the
514 /// loop, physical registers aren't accessed explicitly, and there are no side
515 /// effects that aren't captured by the operands or other flags.
517 bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
518 if (!IsLICMCandidate(I))
521 // The instruction is loop invariant if all of its operands are.
522 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
523 const MachineOperand &MO = I.getOperand(i);
528 unsigned Reg = MO.getReg();
529 if (Reg == 0) continue;
531 // Don't hoist an instruction that uses or defines a physical register.
532 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
534 // If the physreg has no defs anywhere, it's just an ambient register
535 // and we can freely move its uses. Alternatively, if it's allocatable,
536 // it could get allocated to something with a def during allocation.
537 if (!RegInfo->def_empty(Reg))
539 if (AllocatableSet.test(Reg))
541 // Check for a def among the register's aliases too.
542 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
543 unsigned AliasReg = *Alias;
544 if (!RegInfo->def_empty(AliasReg))
546 if (AllocatableSet.test(AliasReg))
549 // Otherwise it's safe to move.
551 } else if (!MO.isDead()) {
552 // A def that isn't dead. We can't move it.
554 } else if (CurLoop->getHeader()->isLiveIn(Reg)) {
555 // If the reg is live into the loop, we can't hoist an instruction
556 // which would clobber it.
564 assert(RegInfo->getVRegDef(Reg) &&
565 "Machine instr not mapped for this vreg?!");
567 // If the loop contains the definition of an operand, then the instruction
568 // isn't loop invariant.
569 if (CurLoop->contains(RegInfo->getVRegDef(Reg)))
573 // If we got this far, the instruction is loop invariant!
578 /// HasPHIUses - Return true if the specified register has any PHI use.
579 static bool HasPHIUses(unsigned Reg, MachineRegisterInfo *RegInfo) {
580 for (MachineRegisterInfo::use_iterator UI = RegInfo->use_begin(Reg),
581 UE = RegInfo->use_end(); UI != UE; ++UI) {
582 MachineInstr *UseMI = &*UI;
589 /// isLoadFromConstantMemory - Return true if the given instruction is a
590 /// load from constant memory. Machine LICM will hoist these even if they are
591 /// not re-materializable.
592 bool MachineLICM::isLoadFromConstantMemory(MachineInstr *MI) {
593 if (!MI->getDesc().mayLoad()) return false;
594 if (!MI->hasOneMemOperand()) return false;
595 MachineMemOperand *MMO = *MI->memoperands_begin();
596 if (MMO->isVolatile()) return false;
597 if (!MMO->getValue()) return false;
598 const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(MMO->getValue());
600 MachineFunction &MF = *MI->getParent()->getParent();
601 return PSV->isConstant(MF.getFrameInfo());
603 return AA->pointsToConstantMemory(MMO->getValue());
607 /// IsProfitableToHoist - Return true if it is potentially profitable to hoist
608 /// the given loop invariant.
609 bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
610 // FIXME: For now, only hoist re-materilizable instructions. LICM will
611 // increase register pressure. We want to make sure it doesn't increase
613 // Also hoist loads from constant memory, e.g. load from stubs, GOT. Hoisting
614 // these tend to help performance in low register pressure situation. The
615 // trade off is it may cause spill in high pressure situation. It will end up
616 // adding a store in the loop preheader. But the reload is no more expensive.
617 // The side benefit is these loads are frequently CSE'ed.
618 if (!TII->isTriviallyReMaterializable(&MI, AA)) {
619 if (!isLoadFromConstantMemory(&MI))
623 // If result(s) of this instruction is used by PHIs, then don't hoist it.
624 // The presence of joins makes it difficult for current register allocator
625 // implementation to perform remat.
626 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
627 const MachineOperand &MO = MI.getOperand(i);
628 if (!MO.isReg() || !MO.isDef())
630 if (HasPHIUses(MO.getReg(), RegInfo))
637 MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
638 // If not, we may be able to unfold a load and hoist that.
639 // First test whether the instruction is loading from an amenable
641 if (!isLoadFromConstantMemory(MI))
644 // Next determine the register class for a temporary register.
645 unsigned LoadRegIndex;
647 TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(),
649 /*UnfoldStore=*/false,
651 if (NewOpc == 0) return 0;
652 const TargetInstrDesc &TID = TII->get(NewOpc);
653 if (TID.getNumDefs() != 1) return 0;
654 const TargetRegisterClass *RC = TID.OpInfo[LoadRegIndex].getRegClass(TRI);
655 // Ok, we're unfolding. Create a temporary register and do the unfold.
656 unsigned Reg = RegInfo->createVirtualRegister(RC);
658 MachineFunction &MF = *MI->getParent()->getParent();
659 SmallVector<MachineInstr *, 2> NewMIs;
661 TII->unfoldMemoryOperand(MF, MI, Reg,
662 /*UnfoldLoad=*/true, /*UnfoldStore=*/false,
666 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
668 assert(NewMIs.size() == 2 &&
669 "Unfolded a load into multiple instructions!");
670 MachineBasicBlock *MBB = MI->getParent();
671 MBB->insert(MI, NewMIs[0]);
672 MBB->insert(MI, NewMIs[1]);
673 // If unfolding produced a load that wasn't loop-invariant or profitable to
674 // hoist, discard the new instructions and bail.
675 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
676 NewMIs[0]->eraseFromParent();
677 NewMIs[1]->eraseFromParent();
680 // Otherwise we successfully unfolded a load that we can hoist.
681 MI->eraseFromParent();
685 void MachineLICM::InitCSEMap(MachineBasicBlock *BB) {
686 for (MachineBasicBlock::iterator I = BB->begin(),E = BB->end(); I != E; ++I) {
687 const MachineInstr *MI = &*I;
688 // FIXME: For now, only hoist re-materilizable instructions. LICM will
689 // increase register pressure. We want to make sure it doesn't increase
691 if (TII->isTriviallyReMaterializable(MI, AA)) {
692 unsigned Opcode = MI->getOpcode();
693 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
694 CI = CSEMap.find(Opcode);
695 if (CI != CSEMap.end())
696 CI->second.push_back(MI);
698 std::vector<const MachineInstr*> CSEMIs;
699 CSEMIs.push_back(MI);
700 CSEMap.insert(std::make_pair(Opcode, CSEMIs));
707 MachineLICM::LookForDuplicate(const MachineInstr *MI,
708 std::vector<const MachineInstr*> &PrevMIs) {
709 for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) {
710 const MachineInstr *PrevMI = PrevMIs[i];
711 if (TII->produceSameValue(MI, PrevMI))
717 bool MachineLICM::EliminateCSE(MachineInstr *MI,
718 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI) {
719 // Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
720 // the undef property onto uses.
721 if (CI == CSEMap.end() || MI->isImplicitDef())
724 if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
725 DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
727 // Replace virtual registers defined by MI by their counterparts defined
729 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
730 const MachineOperand &MO = MI->getOperand(i);
732 // Physical registers may not differ here.
733 assert((!MO.isReg() || MO.getReg() == 0 ||
734 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
735 MO.getReg() == Dup->getOperand(i).getReg()) &&
736 "Instructions with different phys regs are not identical!");
738 if (MO.isReg() && MO.isDef() &&
739 !TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
740 RegInfo->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg());
741 RegInfo->clearKillFlags(Dup->getOperand(i).getReg());
744 MI->eraseFromParent();
751 /// Hoist - When an instruction is found to use only loop invariant operands
752 /// that are safe to hoist, this instruction is called to do the dirty work.
754 void MachineLICM::Hoist(MachineInstr *MI) {
755 MachineBasicBlock *Preheader = getCurPreheader();
756 if (!Preheader) return;
758 // First check whether we should hoist this instruction.
759 if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
760 // If not, try unfolding a hoistable load.
761 MI = ExtractHoistableLoad(MI);
765 // Now move the instructions to the predecessor, inserting it before any
766 // terminator instructions.
768 dbgs() << "Hoisting " << *MI;
769 if (Preheader->getBasicBlock())
770 dbgs() << " to MachineBasicBlock "
771 << Preheader->getName();
772 if (MI->getParent()->getBasicBlock())
773 dbgs() << " from MachineBasicBlock "
774 << MI->getParent()->getName();
778 // If this is the first instruction being hoisted to the preheader,
779 // initialize the CSE map with potential common expressions.
781 InitCSEMap(Preheader);
785 // Look for opportunity to CSE the hoisted instruction.
786 unsigned Opcode = MI->getOpcode();
787 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
788 CI = CSEMap.find(Opcode);
789 if (!EliminateCSE(MI, CI)) {
790 // Otherwise, splice the instruction to the preheader.
791 Preheader->splice(Preheader->getFirstTerminator(),MI->getParent(),MI);
793 // Clear the kill flags of any register this instruction defines,
794 // since they may need to be live throughout the entire loop
795 // rather than just live for part of it.
796 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
797 MachineOperand &MO = MI->getOperand(i);
798 if (MO.isReg() && MO.isDef() && !MO.isDead())
799 RegInfo->clearKillFlags(MO.getReg());
802 // Add to the CSE map.
803 if (CI != CSEMap.end())
804 CI->second.push_back(MI);
806 std::vector<const MachineInstr*> CSEMIs;
807 CSEMIs.push_back(MI);
808 CSEMap.insert(std::make_pair(Opcode, CSEMIs));
816 MachineBasicBlock *MachineLICM::getCurPreheader() {
817 // Determine the block to which to hoist instructions. If we can't find a
818 // suitable loop predecessor, we can't do any hoisting.
820 // If we've tried to get a preheader and failed, don't try again.
821 if (CurPreheader == reinterpret_cast<MachineBasicBlock *>(-1))
825 CurPreheader = CurLoop->getLoopPreheader();
827 MachineBasicBlock *Pred = CurLoop->getLoopPredecessor();
829 CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
833 CurPreheader = Pred->SplitCriticalEdge(CurLoop->getHeader(), this);
835 CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);