1 //===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs loop invariant code motion on machine instructions. We
11 // attempt to remove as much code from the body of a loop as possible.
13 // This pass does not attempt to throttle itself to limit register pressure.
14 // The register allocation phases are expected to perform rematerialization
15 // to recover when register pressure is high.
17 // This pass is not intended to be a replacement or a complete alternative
18 // for the LLVM-IR-level LICM pass. It is only designed to hoist simple
19 // constructs that are not exposed before lowering and instruction selection.
21 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "machine-licm"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/ADT/DenseMap.h"
26 #include "llvm/ADT/SmallSet.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Analysis/AliasAnalysis.h"
29 #include "llvm/CodeGen/MachineDominators.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineLoopInfo.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/PseudoSourceValue.h"
35 #include "llvm/MC/MCInstrItineraries.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetLowering.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
46 AvoidSpeculation("avoid-speculation",
47 cl::desc("MachineLICM should avoid speculation"),
48 cl::init(true), cl::Hidden);
51 "Number of machine instructions hoisted out of loops");
53 "Number of instructions hoisted in low reg pressure situation");
54 STATISTIC(NumHighLatency,
55 "Number of high latency instructions hoisted");
57 "Number of hoisted machine instructions CSEed");
58 STATISTIC(NumPostRAHoisted,
59 "Number of machine instructions hoisted out of loops post regalloc");
62 class MachineLICM : public MachineFunctionPass {
63 const TargetMachine *TM;
64 const TargetInstrInfo *TII;
65 const TargetLoweringBase *TLI;
66 const TargetRegisterInfo *TRI;
67 const MachineFrameInfo *MFI;
68 MachineRegisterInfo *MRI;
69 const InstrItineraryData *InstrItins;
72 // Various analyses that we use...
73 AliasAnalysis *AA; // Alias analysis info.
74 MachineLoopInfo *MLI; // Current MachineLoopInfo
75 MachineDominatorTree *DT; // Machine dominator tree for the cur loop
77 // State that is updated as we process loops
78 bool Changed; // True if a loop is changed.
79 bool FirstInLoop; // True if it's the first LICM in the loop.
80 MachineLoop *CurLoop; // The current loop we are working on.
81 MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
83 // Exit blocks for CurLoop.
84 SmallVector<MachineBasicBlock*, 8> ExitBlocks;
86 bool isExitBlock(const MachineBasicBlock *MBB) const {
87 return std::find(ExitBlocks.begin(), ExitBlocks.end(), MBB) !=
91 // Track 'estimated' register pressure.
92 SmallSet<unsigned, 32> RegSeen;
93 SmallVector<unsigned, 8> RegPressure;
95 // Register pressure "limit" per register class. If the pressure
96 // is higher than the limit, then it's considered high.
97 SmallVector<unsigned, 8> RegLimit;
99 // Register pressure on path leading from loop preheader to current BB.
100 SmallVector<SmallVector<unsigned, 8>, 16> BackTrace;
102 // For each opcode, keep a list of potential CSE instructions.
103 DenseMap<unsigned, std::vector<const MachineInstr*> > CSEMap;
111 // If a MBB does not dominate loop exiting blocks then it may not safe
112 // to hoist loads from this block.
113 // Tri-state: 0 - false, 1 - true, 2 - unknown
114 unsigned SpeculationState;
117 static char ID; // Pass identification, replacement for typeid
119 MachineFunctionPass(ID), PreRegAlloc(true) {
120 initializeMachineLICMPass(*PassRegistry::getPassRegistry());
123 explicit MachineLICM(bool PreRA) :
124 MachineFunctionPass(ID), PreRegAlloc(PreRA) {
125 initializeMachineLICMPass(*PassRegistry::getPassRegistry());
128 bool runOnMachineFunction(MachineFunction &MF) override;
130 void getAnalysisUsage(AnalysisUsage &AU) const override {
131 AU.addRequired<MachineLoopInfo>();
132 AU.addRequired<MachineDominatorTree>();
133 AU.addRequired<AliasAnalysis>();
134 AU.addPreserved<MachineLoopInfo>();
135 AU.addPreserved<MachineDominatorTree>();
136 MachineFunctionPass::getAnalysisUsage(AU);
139 void releaseMemory() override {
144 for (DenseMap<unsigned,std::vector<const MachineInstr*> >::iterator
145 CI = CSEMap.begin(), CE = CSEMap.end(); CI != CE; ++CI)
151 /// CandidateInfo - Keep track of information about hoisting candidates.
152 struct CandidateInfo {
156 CandidateInfo(MachineInstr *mi, unsigned def, int fi)
157 : MI(mi), Def(def), FI(fi) {}
160 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
161 /// invariants out to the preheader.
162 void HoistRegionPostRA();
164 /// HoistPostRA - When an instruction is found to only use loop invariant
165 /// operands that is safe to hoist, this instruction is called to do the
167 void HoistPostRA(MachineInstr *MI, unsigned Def);
169 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
170 /// gather register def and frame object update information.
171 void ProcessMI(MachineInstr *MI,
172 BitVector &PhysRegDefs,
173 BitVector &PhysRegClobbers,
174 SmallSet<int, 32> &StoredFIs,
175 SmallVectorImpl<CandidateInfo> &Candidates);
177 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the
179 void AddToLiveIns(unsigned Reg);
181 /// IsLICMCandidate - Returns true if the instruction may be a suitable
182 /// candidate for LICM. e.g. If the instruction is a call, then it's
183 /// obviously not safe to hoist it.
184 bool IsLICMCandidate(MachineInstr &I);
186 /// IsLoopInvariantInst - Returns true if the instruction is loop
187 /// invariant. I.e., all virtual register operands are defined outside of
188 /// the loop, physical registers aren't accessed (explicitly or implicitly),
189 /// and the instruction is hoistable.
191 bool IsLoopInvariantInst(MachineInstr &I);
193 /// HasLoopPHIUse - Return true if the specified instruction is used by any
194 /// phi node in the current loop.
195 bool HasLoopPHIUse(const MachineInstr *MI) const;
197 /// HasHighOperandLatency - Compute operand latency between a def of 'Reg'
198 /// and an use in the current loop, return true if the target considered
200 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
203 bool IsCheapInstruction(MachineInstr &MI) const;
205 /// CanCauseHighRegPressure - Visit BBs from header to current BB,
206 /// check if hoisting an instruction of the given cost matrix can cause high
207 /// register pressure.
208 bool CanCauseHighRegPressure(DenseMap<unsigned, int> &Cost, bool Cheap);
210 /// UpdateBackTraceRegPressure - Traverse the back trace from header to
211 /// the current block and update their register pressures to reflect the
212 /// effect of hoisting MI from the current block to the preheader.
213 void UpdateBackTraceRegPressure(const MachineInstr *MI);
215 /// IsProfitableToHoist - Return true if it is potentially profitable to
216 /// hoist the given loop invariant.
217 bool IsProfitableToHoist(MachineInstr &MI);
219 /// IsGuaranteedToExecute - Check if this mbb is guaranteed to execute.
220 /// If not then a load from this mbb may not be safe to hoist.
221 bool IsGuaranteedToExecute(MachineBasicBlock *BB);
223 void EnterScope(MachineBasicBlock *MBB);
225 void ExitScope(MachineBasicBlock *MBB);
227 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to given
228 /// dominator tree node if its a leaf or all of its children are done. Walk
229 /// up the dominator tree to destroy ancestors which are now done.
230 void ExitScopeIfDone(MachineDomTreeNode *Node,
231 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
232 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> &ParentMap);
234 /// HoistOutOfLoop - Walk the specified loop in the CFG (defined by all
235 /// blocks dominated by the specified header block, and that are in the
236 /// current loop) in depth first order w.r.t the DominatorTree. This allows
237 /// us to visit definitions before uses, allowing us to hoist a loop body in
238 /// one pass without iteration.
240 void HoistOutOfLoop(MachineDomTreeNode *LoopHeaderNode);
241 void HoistRegion(MachineDomTreeNode *N, bool IsHeader);
243 /// getRegisterClassIDAndCost - For a given MI, register, and the operand
244 /// index, return the ID and cost of its representative register class by
246 void getRegisterClassIDAndCost(const MachineInstr *MI,
247 unsigned Reg, unsigned OpIdx,
248 unsigned &RCId, unsigned &RCCost) const;
250 /// InitRegPressure - Find all virtual register references that are liveout
251 /// of the preheader to initialize the starting "register pressure". Note
252 /// this does not count live through (livein but not used) registers.
253 void InitRegPressure(MachineBasicBlock *BB);
255 /// UpdateRegPressure - Update estimate of register pressure after the
256 /// specified instruction.
257 void UpdateRegPressure(const MachineInstr *MI);
259 /// ExtractHoistableLoad - Unfold a load from the given machineinstr if
260 /// the load itself could be hoisted. Return the unfolded and hoistable
261 /// load, or null if the load couldn't be unfolded or if it wouldn't
263 MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
265 /// LookForDuplicate - Find an instruction amount PrevMIs that is a
266 /// duplicate of MI. Return this instruction if it's found.
267 const MachineInstr *LookForDuplicate(const MachineInstr *MI,
268 std::vector<const MachineInstr*> &PrevMIs);
270 /// EliminateCSE - Given a LICM'ed instruction, look for an instruction on
271 /// the preheader that compute the same value. If it's found, do a RAU on
272 /// with the definition of the existing instruction rather than hoisting
273 /// the instruction to the preheader.
274 bool EliminateCSE(MachineInstr *MI,
275 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI);
277 /// MayCSE - Return true if the given instruction will be CSE'd if it's
278 /// hoisted out of the loop.
279 bool MayCSE(MachineInstr *MI);
281 /// Hoist - When an instruction is found to only use loop invariant operands
282 /// that is safe to hoist, this instruction is called to do the dirty work.
283 /// It returns true if the instruction is hoisted.
284 bool Hoist(MachineInstr *MI, MachineBasicBlock *Preheader);
286 /// InitCSEMap - Initialize the CSE map with instructions that are in the
287 /// current loop preheader that may become duplicates of instructions that
288 /// are hoisted out of the loop.
289 void InitCSEMap(MachineBasicBlock *BB);
291 /// getCurPreheader - Get the preheader for the current loop, splitting
292 /// a critical edge if needed.
293 MachineBasicBlock *getCurPreheader();
295 } // end anonymous namespace
297 char MachineLICM::ID = 0;
298 char &llvm::MachineLICMID = MachineLICM::ID;
299 INITIALIZE_PASS_BEGIN(MachineLICM, "machinelicm",
300 "Machine Loop Invariant Code Motion", false, false)
301 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
302 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
303 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
304 INITIALIZE_PASS_END(MachineLICM, "machinelicm",
305 "Machine Loop Invariant Code Motion", false, false)
307 /// LoopIsOuterMostWithPredecessor - Test if the given loop is the outer-most
308 /// loop that has a unique predecessor.
309 static bool LoopIsOuterMostWithPredecessor(MachineLoop *CurLoop) {
310 // Check whether this loop even has a unique predecessor.
311 if (!CurLoop->getLoopPredecessor())
313 // Ok, now check to see if any of its outer loops do.
314 for (MachineLoop *L = CurLoop->getParentLoop(); L; L = L->getParentLoop())
315 if (L->getLoopPredecessor())
317 // None of them did, so this is the outermost with a unique predecessor.
321 bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
322 if (skipOptnoneFunction(*MF.getFunction()))
325 Changed = FirstInLoop = false;
326 TM = &MF.getTarget();
327 TII = TM->getInstrInfo();
328 TLI = TM->getTargetLowering();
329 TRI = TM->getRegisterInfo();
330 MFI = MF.getFrameInfo();
331 MRI = &MF.getRegInfo();
332 InstrItins = TM->getInstrItineraryData();
334 PreRegAlloc = MRI->isSSA();
337 DEBUG(dbgs() << "******** Pre-regalloc Machine LICM: ");
339 DEBUG(dbgs() << "******** Post-regalloc Machine LICM: ");
340 DEBUG(dbgs() << MF.getName() << " ********\n");
343 // Estimate register pressure during pre-regalloc pass.
344 unsigned NumRC = TRI->getNumRegClasses();
345 RegPressure.resize(NumRC);
346 std::fill(RegPressure.begin(), RegPressure.end(), 0);
347 RegLimit.resize(NumRC);
348 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
349 E = TRI->regclass_end(); I != E; ++I)
350 RegLimit[(*I)->getID()] = TRI->getRegPressureLimit(*I, MF);
353 // Get our Loop information...
354 MLI = &getAnalysis<MachineLoopInfo>();
355 DT = &getAnalysis<MachineDominatorTree>();
356 AA = &getAnalysis<AliasAnalysis>();
358 SmallVector<MachineLoop *, 8> Worklist(MLI->begin(), MLI->end());
359 while (!Worklist.empty()) {
360 CurLoop = Worklist.pop_back_val();
361 CurPreheader = nullptr;
364 // If this is done before regalloc, only visit outer-most preheader-sporting
366 if (PreRegAlloc && !LoopIsOuterMostWithPredecessor(CurLoop)) {
367 Worklist.append(CurLoop->begin(), CurLoop->end());
371 CurLoop->getExitBlocks(ExitBlocks);
376 // CSEMap is initialized for loop header when the first instruction is
378 MachineDomTreeNode *N = DT->getNode(CurLoop->getHeader());
388 /// InstructionStoresToFI - Return true if instruction stores to the
390 static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
391 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
392 oe = MI->memoperands_end(); o != oe; ++o) {
393 if (!(*o)->isStore() || !(*o)->getPseudoValue())
395 if (const FixedStackPseudoSourceValue *Value =
396 dyn_cast<FixedStackPseudoSourceValue>((*o)->getPseudoValue())) {
397 if (Value->getFrameIndex() == FI)
404 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
405 /// gather register def and frame object update information.
406 void MachineLICM::ProcessMI(MachineInstr *MI,
407 BitVector &PhysRegDefs,
408 BitVector &PhysRegClobbers,
409 SmallSet<int, 32> &StoredFIs,
410 SmallVectorImpl<CandidateInfo> &Candidates) {
411 bool RuledOut = false;
412 bool HasNonInvariantUse = false;
414 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
415 const MachineOperand &MO = MI->getOperand(i);
417 // Remember if the instruction stores to the frame index.
418 int FI = MO.getIndex();
419 if (!StoredFIs.count(FI) &&
420 MFI->isSpillSlotObjectIndex(FI) &&
421 InstructionStoresToFI(MI, FI))
422 StoredFIs.insert(FI);
423 HasNonInvariantUse = true;
427 // We can't hoist an instruction defining a physreg that is clobbered in
429 if (MO.isRegMask()) {
430 PhysRegClobbers.setBitsNotInMask(MO.getRegMask());
436 unsigned Reg = MO.getReg();
439 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
440 "Not expecting virtual register!");
443 if (Reg && (PhysRegDefs.test(Reg) || PhysRegClobbers.test(Reg)))
444 // If it's using a non-loop-invariant register, then it's obviously not
446 HasNonInvariantUse = true;
450 if (MO.isImplicit()) {
451 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
452 PhysRegClobbers.set(*AI);
454 // Non-dead implicit def? This cannot be hoisted.
456 // No need to check if a dead implicit def is also defined by
457 // another instruction.
461 // FIXME: For now, avoid instructions with multiple defs, unless
462 // it's a dead implicit def.
468 // If we have already seen another instruction that defines the same
469 // register, then this is not safe. Two defs is indicated by setting a
470 // PhysRegClobbers bit.
471 for (MCRegAliasIterator AS(Reg, TRI, true); AS.isValid(); ++AS) {
472 if (PhysRegDefs.test(*AS))
473 PhysRegClobbers.set(*AS);
474 PhysRegDefs.set(*AS);
476 if (PhysRegClobbers.test(Reg))
477 // MI defined register is seen defined by another instruction in
478 // the loop, it cannot be a LICM candidate.
482 // Only consider reloads for now and remats which do not have register
483 // operands. FIXME: Consider unfold load folding instructions.
484 if (Def && !RuledOut) {
486 if ((!HasNonInvariantUse && IsLICMCandidate(*MI)) ||
487 (TII->isLoadFromStackSlot(MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
488 Candidates.push_back(CandidateInfo(MI, Def, FI));
492 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
493 /// invariants out to the preheader.
494 void MachineLICM::HoistRegionPostRA() {
495 MachineBasicBlock *Preheader = getCurPreheader();
499 unsigned NumRegs = TRI->getNumRegs();
500 BitVector PhysRegDefs(NumRegs); // Regs defined once in the loop.
501 BitVector PhysRegClobbers(NumRegs); // Regs defined more than once.
503 SmallVector<CandidateInfo, 32> Candidates;
504 SmallSet<int, 32> StoredFIs;
506 // Walk the entire region, count number of defs for each register, and
507 // collect potential LICM candidates.
508 const std::vector<MachineBasicBlock *> &Blocks = CurLoop->getBlocks();
509 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
510 MachineBasicBlock *BB = Blocks[i];
512 // If the header of the loop containing this basic block is a landing pad,
513 // then don't try to hoist instructions out of this loop.
514 const MachineLoop *ML = MLI->getLoopFor(BB);
515 if (ML && ML->getHeader()->isLandingPad()) continue;
517 // Conservatively treat live-in's as an external def.
518 // FIXME: That means a reload that're reused in successor block(s) will not
520 for (MachineBasicBlock::livein_iterator I = BB->livein_begin(),
521 E = BB->livein_end(); I != E; ++I) {
523 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
524 PhysRegDefs.set(*AI);
527 SpeculationState = SpeculateUnknown;
528 for (MachineBasicBlock::iterator
529 MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
530 MachineInstr *MI = &*MII;
531 ProcessMI(MI, PhysRegDefs, PhysRegClobbers, StoredFIs, Candidates);
535 // Gather the registers read / clobbered by the terminator.
536 BitVector TermRegs(NumRegs);
537 MachineBasicBlock::iterator TI = Preheader->getFirstTerminator();
538 if (TI != Preheader->end()) {
539 for (unsigned i = 0, e = TI->getNumOperands(); i != e; ++i) {
540 const MachineOperand &MO = TI->getOperand(i);
543 unsigned Reg = MO.getReg();
546 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
551 // Now evaluate whether the potential candidates qualify.
552 // 1. Check if the candidate defined register is defined by another
553 // instruction in the loop.
554 // 2. If the candidate is a load from stack slot (always true for now),
555 // check if the slot is stored anywhere in the loop.
556 // 3. Make sure candidate def should not clobber
557 // registers read by the terminator. Similarly its def should not be
558 // clobbered by the terminator.
559 for (unsigned i = 0, e = Candidates.size(); i != e; ++i) {
560 if (Candidates[i].FI != INT_MIN &&
561 StoredFIs.count(Candidates[i].FI))
564 unsigned Def = Candidates[i].Def;
565 if (!PhysRegClobbers.test(Def) && !TermRegs.test(Def)) {
567 MachineInstr *MI = Candidates[i].MI;
568 for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
569 const MachineOperand &MO = MI->getOperand(j);
570 if (!MO.isReg() || MO.isDef() || !MO.getReg())
572 unsigned Reg = MO.getReg();
573 if (PhysRegDefs.test(Reg) ||
574 PhysRegClobbers.test(Reg)) {
575 // If it's using a non-loop-invariant register, then it's obviously
576 // not safe to hoist.
582 HoistPostRA(MI, Candidates[i].Def);
587 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the current
588 /// loop, and make sure it is not killed by any instructions in the loop.
589 void MachineLICM::AddToLiveIns(unsigned Reg) {
590 const std::vector<MachineBasicBlock *> &Blocks = CurLoop->getBlocks();
591 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
592 MachineBasicBlock *BB = Blocks[i];
593 if (!BB->isLiveIn(Reg))
595 for (MachineBasicBlock::iterator
596 MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
597 MachineInstr *MI = &*MII;
598 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
599 MachineOperand &MO = MI->getOperand(i);
600 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
601 if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
608 /// HoistPostRA - When an instruction is found to only use loop invariant
609 /// operands that is safe to hoist, this instruction is called to do the
611 void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
612 MachineBasicBlock *Preheader = getCurPreheader();
614 // Now move the instructions to the predecessor, inserting it before any
615 // terminator instructions.
616 DEBUG(dbgs() << "Hoisting to BB#" << Preheader->getNumber() << " from BB#"
617 << MI->getParent()->getNumber() << ": " << *MI);
619 // Splice the instruction to the preheader.
620 MachineBasicBlock *MBB = MI->getParent();
621 Preheader->splice(Preheader->getFirstTerminator(), MBB, MI);
623 // Add register to livein list to all the BBs in the current loop since a
624 // loop invariant must be kept live throughout the whole loop. This is
625 // important to ensure later passes do not scavenge the def register.
632 // IsGuaranteedToExecute - Check if this mbb is guaranteed to execute.
633 // If not then a load from this mbb may not be safe to hoist.
634 bool MachineLICM::IsGuaranteedToExecute(MachineBasicBlock *BB) {
635 if (SpeculationState != SpeculateUnknown)
636 return SpeculationState == SpeculateFalse;
638 if (BB != CurLoop->getHeader()) {
639 // Check loop exiting blocks.
640 SmallVector<MachineBasicBlock*, 8> CurrentLoopExitingBlocks;
641 CurLoop->getExitingBlocks(CurrentLoopExitingBlocks);
642 for (unsigned i = 0, e = CurrentLoopExitingBlocks.size(); i != e; ++i)
643 if (!DT->dominates(BB, CurrentLoopExitingBlocks[i])) {
644 SpeculationState = SpeculateTrue;
649 SpeculationState = SpeculateFalse;
653 void MachineLICM::EnterScope(MachineBasicBlock *MBB) {
654 DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
656 // Remember livein register pressure.
657 BackTrace.push_back(RegPressure);
660 void MachineLICM::ExitScope(MachineBasicBlock *MBB) {
661 DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
662 BackTrace.pop_back();
665 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
666 /// dominator tree node if its a leaf or all of its children are done. Walk
667 /// up the dominator tree to destroy ancestors which are now done.
668 void MachineLICM::ExitScopeIfDone(MachineDomTreeNode *Node,
669 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
670 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> &ParentMap) {
671 if (OpenChildren[Node])
675 ExitScope(Node->getBlock());
677 // Now traverse upwards to pop ancestors whose offsprings are all done.
678 while (MachineDomTreeNode *Parent = ParentMap[Node]) {
679 unsigned Left = --OpenChildren[Parent];
682 ExitScope(Parent->getBlock());
687 /// HoistOutOfLoop - Walk the specified loop in the CFG (defined by all
688 /// blocks dominated by the specified header block, and that are in the
689 /// current loop) in depth first order w.r.t the DominatorTree. This allows
690 /// us to visit definitions before uses, allowing us to hoist a loop body in
691 /// one pass without iteration.
693 void MachineLICM::HoistOutOfLoop(MachineDomTreeNode *HeaderN) {
694 SmallVector<MachineDomTreeNode*, 32> Scopes;
695 SmallVector<MachineDomTreeNode*, 8> WorkList;
696 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> ParentMap;
697 DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
699 // Perform a DFS walk to determine the order of visit.
700 WorkList.push_back(HeaderN);
702 MachineDomTreeNode *Node = WorkList.pop_back_val();
703 assert(Node && "Null dominator tree node?");
704 MachineBasicBlock *BB = Node->getBlock();
706 // If the header of the loop containing this basic block is a landing pad,
707 // then don't try to hoist instructions out of this loop.
708 const MachineLoop *ML = MLI->getLoopFor(BB);
709 if (ML && ML->getHeader()->isLandingPad())
712 // If this subregion is not in the top level loop at all, exit.
713 if (!CurLoop->contains(BB))
716 Scopes.push_back(Node);
717 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
718 unsigned NumChildren = Children.size();
720 // Don't hoist things out of a large switch statement. This often causes
721 // code to be hoisted that wasn't going to be executed, and increases
722 // register pressure in a situation where it's likely to matter.
723 if (BB->succ_size() >= 25)
726 OpenChildren[Node] = NumChildren;
727 // Add children in reverse order as then the next popped worklist node is
728 // the first child of this node. This means we ultimately traverse the
729 // DOM tree in exactly the same order as if we'd recursed.
730 for (int i = (int)NumChildren-1; i >= 0; --i) {
731 MachineDomTreeNode *Child = Children[i];
732 ParentMap[Child] = Node;
733 WorkList.push_back(Child);
735 } while (!WorkList.empty());
737 if (Scopes.size() != 0) {
738 MachineBasicBlock *Preheader = getCurPreheader();
742 // Compute registers which are livein into the loop headers.
745 InitRegPressure(Preheader);
749 for (unsigned i = 0, e = Scopes.size(); i != e; ++i) {
750 MachineDomTreeNode *Node = Scopes[i];
751 MachineBasicBlock *MBB = Node->getBlock();
753 MachineBasicBlock *Preheader = getCurPreheader();
760 SpeculationState = SpeculateUnknown;
761 for (MachineBasicBlock::iterator
762 MII = MBB->begin(), E = MBB->end(); MII != E; ) {
763 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
764 MachineInstr *MI = &*MII;
765 if (!Hoist(MI, Preheader))
766 UpdateRegPressure(MI);
770 // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
771 ExitScopeIfDone(Node, OpenChildren, ParentMap);
775 static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI) {
776 return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg());
779 /// getRegisterClassIDAndCost - For a given MI, register, and the operand
780 /// index, return the ID and cost of its representative register class.
782 MachineLICM::getRegisterClassIDAndCost(const MachineInstr *MI,
783 unsigned Reg, unsigned OpIdx,
784 unsigned &RCId, unsigned &RCCost) const {
785 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
786 MVT VT = *RC->vt_begin();
787 if (VT == MVT::Untyped) {
791 RCId = TLI->getRepRegClassFor(VT)->getID();
792 RCCost = TLI->getRepRegClassCostFor(VT);
796 /// InitRegPressure - Find all virtual register references that are liveout of
797 /// the preheader to initialize the starting "register pressure". Note this
798 /// does not count live through (livein but not used) registers.
799 void MachineLICM::InitRegPressure(MachineBasicBlock *BB) {
800 std::fill(RegPressure.begin(), RegPressure.end(), 0);
802 // If the preheader has only a single predecessor and it ends with a
803 // fallthrough or an unconditional branch, then scan its predecessor for live
804 // defs as well. This happens whenever the preheader is created by splitting
805 // the critical edge from the loop predecessor to the loop header.
806 if (BB->pred_size() == 1) {
807 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
808 SmallVector<MachineOperand, 4> Cond;
809 if (!TII->AnalyzeBranch(*BB, TBB, FBB, Cond, false) && Cond.empty())
810 InitRegPressure(*BB->pred_begin());
813 for (MachineBasicBlock::iterator MII = BB->begin(), E = BB->end();
815 MachineInstr *MI = &*MII;
816 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
817 const MachineOperand &MO = MI->getOperand(i);
818 if (!MO.isReg() || MO.isImplicit())
820 unsigned Reg = MO.getReg();
821 if (!TargetRegisterInfo::isVirtualRegister(Reg))
824 bool isNew = RegSeen.insert(Reg);
825 unsigned RCId, RCCost;
826 getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
828 RegPressure[RCId] += RCCost;
830 bool isKill = isOperandKill(MO, MRI);
831 if (isNew && !isKill)
832 // Haven't seen this, it must be a livein.
833 RegPressure[RCId] += RCCost;
834 else if (!isNew && isKill)
835 RegPressure[RCId] -= RCCost;
841 /// UpdateRegPressure - Update estimate of register pressure after the
842 /// specified instruction.
843 void MachineLICM::UpdateRegPressure(const MachineInstr *MI) {
844 if (MI->isImplicitDef())
847 SmallVector<unsigned, 4> Defs;
848 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
849 const MachineOperand &MO = MI->getOperand(i);
850 if (!MO.isReg() || MO.isImplicit())
852 unsigned Reg = MO.getReg();
853 if (!TargetRegisterInfo::isVirtualRegister(Reg))
856 bool isNew = RegSeen.insert(Reg);
859 else if (!isNew && isOperandKill(MO, MRI)) {
860 unsigned RCId, RCCost;
861 getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
862 if (RCCost > RegPressure[RCId])
863 RegPressure[RCId] = 0;
865 RegPressure[RCId] -= RCCost;
870 while (!Defs.empty()) {
871 unsigned Reg = Defs.pop_back_val();
872 unsigned RCId, RCCost;
873 getRegisterClassIDAndCost(MI, Reg, Idx, RCId, RCCost);
874 RegPressure[RCId] += RCCost;
879 /// isLoadFromGOTOrConstantPool - Return true if this machine instruction
880 /// loads from global offset table or constant pool.
881 static bool isLoadFromGOTOrConstantPool(MachineInstr &MI) {
882 assert (MI.mayLoad() && "Expected MI that loads!");
883 for (MachineInstr::mmo_iterator I = MI.memoperands_begin(),
884 E = MI.memoperands_end(); I != E; ++I) {
885 if (const PseudoSourceValue *PSV = (*I)->getPseudoValue()) {
886 if (PSV == PSV->getGOT() || PSV == PSV->getConstantPool())
893 /// IsLICMCandidate - Returns true if the instruction may be a suitable
894 /// candidate for LICM. e.g. If the instruction is a call, then it's obviously
895 /// not safe to hoist it.
896 bool MachineLICM::IsLICMCandidate(MachineInstr &I) {
897 // Check if it's safe to move the instruction.
898 bool DontMoveAcrossStore = true;
899 if (!I.isSafeToMove(TII, AA, DontMoveAcrossStore))
902 // If it is load then check if it is guaranteed to execute by making sure that
903 // it dominates all exiting blocks. If it doesn't, then there is a path out of
904 // the loop which does not execute this load, so we can't hoist it. Loads
905 // from constant memory are not safe to speculate all the time, for example
906 // indexed load from a jump table.
907 // Stores and side effects are already checked by isSafeToMove.
908 if (I.mayLoad() && !isLoadFromGOTOrConstantPool(I) &&
909 !IsGuaranteedToExecute(I.getParent()))
915 /// IsLoopInvariantInst - Returns true if the instruction is loop
916 /// invariant. I.e., all virtual register operands are defined outside of the
917 /// loop, physical registers aren't accessed explicitly, and there are no side
918 /// effects that aren't captured by the operands or other flags.
920 bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
921 if (!IsLICMCandidate(I))
924 // The instruction is loop invariant if all of its operands are.
925 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
926 const MachineOperand &MO = I.getOperand(i);
931 unsigned Reg = MO.getReg();
932 if (Reg == 0) continue;
934 // Don't hoist an instruction that uses or defines a physical register.
935 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
937 // If the physreg has no defs anywhere, it's just an ambient register
938 // and we can freely move its uses. Alternatively, if it's allocatable,
939 // it could get allocated to something with a def during allocation.
940 if (!MRI->isConstantPhysReg(Reg, *I.getParent()->getParent()))
942 // Otherwise it's safe to move.
944 } else if (!MO.isDead()) {
945 // A def that isn't dead. We can't move it.
947 } else if (CurLoop->getHeader()->isLiveIn(Reg)) {
948 // If the reg is live into the loop, we can't hoist an instruction
949 // which would clobber it.
957 assert(MRI->getVRegDef(Reg) &&
958 "Machine instr not mapped for this vreg?!");
960 // If the loop contains the definition of an operand, then the instruction
961 // isn't loop invariant.
962 if (CurLoop->contains(MRI->getVRegDef(Reg)))
966 // If we got this far, the instruction is loop invariant!
971 /// HasLoopPHIUse - Return true if the specified instruction is used by a
972 /// phi node and hoisting it could cause a copy to be inserted.
973 bool MachineLICM::HasLoopPHIUse(const MachineInstr *MI) const {
974 SmallVector<const MachineInstr*, 8> Work(1, MI);
976 MI = Work.pop_back_val();
977 for (ConstMIOperands MO(MI); MO.isValid(); ++MO) {
978 if (!MO->isReg() || !MO->isDef())
980 unsigned Reg = MO->getReg();
981 if (!TargetRegisterInfo::isVirtualRegister(Reg))
983 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
984 // A PHI may cause a copy to be inserted.
986 // A PHI inside the loop causes a copy because the live range of Reg is
987 // extended across the PHI.
988 if (CurLoop->contains(&UseMI))
990 // A PHI in an exit block can cause a copy to be inserted if the PHI
991 // has multiple predecessors in the loop with different values.
992 // For now, approximate by rejecting all exit blocks.
993 if (isExitBlock(UseMI.getParent()))
997 // Look past copies as well.
998 if (UseMI.isCopy() && CurLoop->contains(&UseMI))
999 Work.push_back(&UseMI);
1002 } while (!Work.empty());
1006 /// HasHighOperandLatency - Compute operand latency between a def of 'Reg'
1007 /// and an use in the current loop, return true if the target considered
1009 bool MachineLICM::HasHighOperandLatency(MachineInstr &MI,
1010 unsigned DefIdx, unsigned Reg) const {
1011 if (!InstrItins || InstrItins->isEmpty() || MRI->use_nodbg_empty(Reg))
1014 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) {
1015 if (UseMI.isCopyLike())
1017 if (!CurLoop->contains(UseMI.getParent()))
1019 for (unsigned i = 0, e = UseMI.getNumOperands(); i != e; ++i) {
1020 const MachineOperand &MO = UseMI.getOperand(i);
1021 if (!MO.isReg() || !MO.isUse())
1023 unsigned MOReg = MO.getReg();
1027 if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, &UseMI, i))
1031 // Only look at the first in loop use.
1038 /// IsCheapInstruction - Return true if the instruction is marked "cheap" or
1039 /// the operand latency between its def and a use is one or less.
1040 bool MachineLICM::IsCheapInstruction(MachineInstr &MI) const {
1041 if (MI.isAsCheapAsAMove() || MI.isCopyLike())
1043 if (!InstrItins || InstrItins->isEmpty())
1046 bool isCheap = false;
1047 unsigned NumDefs = MI.getDesc().getNumDefs();
1048 for (unsigned i = 0, e = MI.getNumOperands(); NumDefs && i != e; ++i) {
1049 MachineOperand &DefMO = MI.getOperand(i);
1050 if (!DefMO.isReg() || !DefMO.isDef())
1053 unsigned Reg = DefMO.getReg();
1054 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1057 if (!TII->hasLowDefLatency(InstrItins, &MI, i))
1065 /// CanCauseHighRegPressure - Visit BBs from header to current BB, check
1066 /// if hoisting an instruction of the given cost matrix can cause high
1067 /// register pressure.
1068 bool MachineLICM::CanCauseHighRegPressure(DenseMap<unsigned, int> &Cost,
1070 for (DenseMap<unsigned, int>::iterator CI = Cost.begin(), CE = Cost.end();
1072 if (CI->second <= 0)
1075 unsigned RCId = CI->first;
1076 unsigned Limit = RegLimit[RCId];
1077 int Cost = CI->second;
1079 // Don't hoist cheap instructions if they would increase register pressure,
1080 // even if we're under the limit.
1084 for (unsigned i = BackTrace.size(); i != 0; --i) {
1085 SmallVectorImpl<unsigned> &RP = BackTrace[i-1];
1086 if (RP[RCId] + Cost >= Limit)
1094 /// UpdateBackTraceRegPressure - Traverse the back trace from header to the
1095 /// current block and update their register pressures to reflect the effect
1096 /// of hoisting MI from the current block to the preheader.
1097 void MachineLICM::UpdateBackTraceRegPressure(const MachineInstr *MI) {
1098 if (MI->isImplicitDef())
1101 // First compute the 'cost' of the instruction, i.e. its contribution
1102 // to register pressure.
1103 DenseMap<unsigned, int> Cost;
1104 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
1105 const MachineOperand &MO = MI->getOperand(i);
1106 if (!MO.isReg() || MO.isImplicit())
1108 unsigned Reg = MO.getReg();
1109 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1112 unsigned RCId, RCCost;
1113 getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
1115 DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
1116 if (CI != Cost.end())
1117 CI->second += RCCost;
1119 Cost.insert(std::make_pair(RCId, RCCost));
1120 } else if (isOperandKill(MO, MRI)) {
1121 DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
1122 if (CI != Cost.end())
1123 CI->second -= RCCost;
1125 Cost.insert(std::make_pair(RCId, -RCCost));
1129 // Update register pressure of blocks from loop header to current block.
1130 for (unsigned i = 0, e = BackTrace.size(); i != e; ++i) {
1131 SmallVectorImpl<unsigned> &RP = BackTrace[i];
1132 for (DenseMap<unsigned, int>::iterator CI = Cost.begin(), CE = Cost.end();
1134 unsigned RCId = CI->first;
1135 RP[RCId] += CI->second;
1140 /// IsProfitableToHoist - Return true if it is potentially profitable to hoist
1141 /// the given loop invariant.
1142 bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
1143 if (MI.isImplicitDef())
1146 // Besides removing computation from the loop, hoisting an instruction has
1149 // - The value defined by the instruction becomes live across the entire
1150 // loop. This increases register pressure in the loop.
1152 // - If the value is used by a PHI in the loop, a copy will be required for
1153 // lowering the PHI after extending the live range.
1155 // - When hoisting the last use of a value in the loop, that value no longer
1156 // needs to be live in the loop. This lowers register pressure in the loop.
1158 bool CheapInstr = IsCheapInstruction(MI);
1159 bool CreatesCopy = HasLoopPHIUse(&MI);
1161 // Don't hoist a cheap instruction if it would create a copy in the loop.
1162 if (CheapInstr && CreatesCopy) {
1163 DEBUG(dbgs() << "Won't hoist cheap instr with loop PHI use: " << MI);
1167 // Rematerializable instructions should always be hoisted since the register
1168 // allocator can just pull them down again when needed.
1169 if (TII->isTriviallyReMaterializable(&MI, AA))
1172 // Estimate register pressure to determine whether to LICM the instruction.
1173 // In low register pressure situation, we can be more aggressive about
1174 // hoisting. Also, favors hoisting long latency instructions even in
1175 // moderately high pressure situation.
1176 // Cheap instructions will only be hoisted if they don't increase register
1178 // FIXME: If there are long latency loop-invariant instructions inside the
1179 // loop at this point, why didn't the optimizer's LICM hoist them?
1180 DenseMap<unsigned, int> Cost;
1181 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
1182 const MachineOperand &MO = MI.getOperand(i);
1183 if (!MO.isReg() || MO.isImplicit())
1185 unsigned Reg = MO.getReg();
1186 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1189 unsigned RCId, RCCost;
1190 getRegisterClassIDAndCost(&MI, Reg, i, RCId, RCCost);
1192 if (HasHighOperandLatency(MI, i, Reg)) {
1193 DEBUG(dbgs() << "Hoist High Latency: " << MI);
1197 Cost[RCId] += RCCost;
1198 } else if (isOperandKill(MO, MRI)) {
1199 // Is a virtual register use is a kill, hoisting it out of the loop
1200 // may actually reduce register pressure or be register pressure
1202 Cost[RCId] -= RCCost;
1206 // Visit BBs from header to current BB, if hoisting this doesn't cause
1207 // high register pressure, then it's safe to proceed.
1208 if (!CanCauseHighRegPressure(Cost, CheapInstr)) {
1209 DEBUG(dbgs() << "Hoist non-reg-pressure: " << MI);
1214 // Don't risk increasing register pressure if it would create copies.
1216 DEBUG(dbgs() << "Won't hoist instr with loop PHI use: " << MI);
1220 // Do not "speculate" in high register pressure situation. If an
1221 // instruction is not guaranteed to be executed in the loop, it's best to be
1223 if (AvoidSpeculation &&
1224 (!IsGuaranteedToExecute(MI.getParent()) && !MayCSE(&MI))) {
1225 DEBUG(dbgs() << "Won't speculate: " << MI);
1229 // High register pressure situation, only hoist if the instruction is going
1231 if (!TII->isTriviallyReMaterializable(&MI, AA) &&
1232 !MI.isInvariantLoad(AA)) {
1233 DEBUG(dbgs() << "Can't remat / high reg-pressure: " << MI);
1240 MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
1241 // Don't unfold simple loads.
1242 if (MI->canFoldAsLoad())
1245 // If not, we may be able to unfold a load and hoist that.
1246 // First test whether the instruction is loading from an amenable
1248 if (!MI->isInvariantLoad(AA))
1251 // Next determine the register class for a temporary register.
1252 unsigned LoadRegIndex;
1254 TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(),
1255 /*UnfoldLoad=*/true,
1256 /*UnfoldStore=*/false,
1258 if (NewOpc == 0) return nullptr;
1259 const MCInstrDesc &MID = TII->get(NewOpc);
1260 if (MID.getNumDefs() != 1) return nullptr;
1261 MachineFunction &MF = *MI->getParent()->getParent();
1262 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF);
1263 // Ok, we're unfolding. Create a temporary register and do the unfold.
1264 unsigned Reg = MRI->createVirtualRegister(RC);
1266 SmallVector<MachineInstr *, 2> NewMIs;
1268 TII->unfoldMemoryOperand(MF, MI, Reg,
1269 /*UnfoldLoad=*/true, /*UnfoldStore=*/false,
1273 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
1275 assert(NewMIs.size() == 2 &&
1276 "Unfolded a load into multiple instructions!");
1277 MachineBasicBlock *MBB = MI->getParent();
1278 MachineBasicBlock::iterator Pos = MI;
1279 MBB->insert(Pos, NewMIs[0]);
1280 MBB->insert(Pos, NewMIs[1]);
1281 // If unfolding produced a load that wasn't loop-invariant or profitable to
1282 // hoist, discard the new instructions and bail.
1283 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
1284 NewMIs[0]->eraseFromParent();
1285 NewMIs[1]->eraseFromParent();
1289 // Update register pressure for the unfolded instruction.
1290 UpdateRegPressure(NewMIs[1]);
1292 // Otherwise we successfully unfolded a load that we can hoist.
1293 MI->eraseFromParent();
1297 void MachineLICM::InitCSEMap(MachineBasicBlock *BB) {
1298 for (MachineBasicBlock::iterator I = BB->begin(),E = BB->end(); I != E; ++I) {
1299 const MachineInstr *MI = &*I;
1300 unsigned Opcode = MI->getOpcode();
1301 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
1302 CI = CSEMap.find(Opcode);
1303 if (CI != CSEMap.end())
1304 CI->second.push_back(MI);
1306 std::vector<const MachineInstr*> CSEMIs;
1307 CSEMIs.push_back(MI);
1308 CSEMap.insert(std::make_pair(Opcode, CSEMIs));
1314 MachineLICM::LookForDuplicate(const MachineInstr *MI,
1315 std::vector<const MachineInstr*> &PrevMIs) {
1316 for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) {
1317 const MachineInstr *PrevMI = PrevMIs[i];
1318 if (TII->produceSameValue(MI, PrevMI, (PreRegAlloc ? MRI : nullptr)))
1324 bool MachineLICM::EliminateCSE(MachineInstr *MI,
1325 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI) {
1326 // Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
1327 // the undef property onto uses.
1328 if (CI == CSEMap.end() || MI->isImplicitDef())
1331 if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
1332 DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
1334 // Replace virtual registers defined by MI by their counterparts defined
1336 SmallVector<unsigned, 2> Defs;
1337 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1338 const MachineOperand &MO = MI->getOperand(i);
1340 // Physical registers may not differ here.
1341 assert((!MO.isReg() || MO.getReg() == 0 ||
1342 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
1343 MO.getReg() == Dup->getOperand(i).getReg()) &&
1344 "Instructions with different phys regs are not identical!");
1346 if (MO.isReg() && MO.isDef() &&
1347 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1351 SmallVector<const TargetRegisterClass*, 2> OrigRCs;
1352 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
1353 unsigned Idx = Defs[i];
1354 unsigned Reg = MI->getOperand(Idx).getReg();
1355 unsigned DupReg = Dup->getOperand(Idx).getReg();
1356 OrigRCs.push_back(MRI->getRegClass(DupReg));
1358 if (!MRI->constrainRegClass(DupReg, MRI->getRegClass(Reg))) {
1359 // Restore old RCs if more than one defs.
1360 for (unsigned j = 0; j != i; ++j)
1361 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]);
1366 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
1367 unsigned Idx = Defs[i];
1368 unsigned Reg = MI->getOperand(Idx).getReg();
1369 unsigned DupReg = Dup->getOperand(Idx).getReg();
1370 MRI->replaceRegWith(Reg, DupReg);
1371 MRI->clearKillFlags(DupReg);
1374 MI->eraseFromParent();
1381 /// MayCSE - Return true if the given instruction will be CSE'd if it's
1382 /// hoisted out of the loop.
1383 bool MachineLICM::MayCSE(MachineInstr *MI) {
1384 unsigned Opcode = MI->getOpcode();
1385 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
1386 CI = CSEMap.find(Opcode);
1387 // Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
1388 // the undef property onto uses.
1389 if (CI == CSEMap.end() || MI->isImplicitDef())
1392 return LookForDuplicate(MI, CI->second) != nullptr;
1395 /// Hoist - When an instruction is found to use only loop invariant operands
1396 /// that are safe to hoist, this instruction is called to do the dirty work.
1398 bool MachineLICM::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
1399 // First check whether we should hoist this instruction.
1400 if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
1401 // If not, try unfolding a hoistable load.
1402 MI = ExtractHoistableLoad(MI);
1403 if (!MI) return false;
1406 // Now move the instructions to the predecessor, inserting it before any
1407 // terminator instructions.
1409 dbgs() << "Hoisting " << *MI;
1410 if (Preheader->getBasicBlock())
1411 dbgs() << " to MachineBasicBlock "
1412 << Preheader->getName();
1413 if (MI->getParent()->getBasicBlock())
1414 dbgs() << " from MachineBasicBlock "
1415 << MI->getParent()->getName();
1419 // If this is the first instruction being hoisted to the preheader,
1420 // initialize the CSE map with potential common expressions.
1422 InitCSEMap(Preheader);
1423 FirstInLoop = false;
1426 // Look for opportunity to CSE the hoisted instruction.
1427 unsigned Opcode = MI->getOpcode();
1428 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
1429 CI = CSEMap.find(Opcode);
1430 if (!EliminateCSE(MI, CI)) {
1431 // Otherwise, splice the instruction to the preheader.
1432 Preheader->splice(Preheader->getFirstTerminator(),MI->getParent(),MI);
1434 // Update register pressure for BBs from header to this block.
1435 UpdateBackTraceRegPressure(MI);
1437 // Clear the kill flags of any register this instruction defines,
1438 // since they may need to be live throughout the entire loop
1439 // rather than just live for part of it.
1440 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1441 MachineOperand &MO = MI->getOperand(i);
1442 if (MO.isReg() && MO.isDef() && !MO.isDead())
1443 MRI->clearKillFlags(MO.getReg());
1446 // Add to the CSE map.
1447 if (CI != CSEMap.end())
1448 CI->second.push_back(MI);
1450 std::vector<const MachineInstr*> CSEMIs;
1451 CSEMIs.push_back(MI);
1452 CSEMap.insert(std::make_pair(Opcode, CSEMIs));
1462 MachineBasicBlock *MachineLICM::getCurPreheader() {
1463 // Determine the block to which to hoist instructions. If we can't find a
1464 // suitable loop predecessor, we can't do any hoisting.
1466 // If we've tried to get a preheader and failed, don't try again.
1467 if (CurPreheader == reinterpret_cast<MachineBasicBlock *>(-1))
1470 if (!CurPreheader) {
1471 CurPreheader = CurLoop->getLoopPreheader();
1472 if (!CurPreheader) {
1473 MachineBasicBlock *Pred = CurLoop->getLoopPredecessor();
1475 CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
1479 CurPreheader = Pred->SplitCriticalEdge(CurLoop->getHeader(), this);
1480 if (!CurPreheader) {
1481 CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
1486 return CurPreheader;