1 //===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs loop invariant code motion on machine instructions. We
11 // attempt to remove as much code from the body of a loop as possible.
13 // This pass does not attempt to throttle itself to limit register pressure.
14 // The register allocation phases are expected to perform rematerialization
15 // to recover when register pressure is high.
17 // This pass is not intended to be a replacement or a complete alternative
18 // for the LLVM-IR-level LICM pass. It is only designed to hoist simple
19 // constructs that are not exposed before lowering and instruction selection.
21 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "machine-licm"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/PseudoSourceValue.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Analysis/AliasAnalysis.h"
35 #include "llvm/ADT/DenseMap.h"
36 #include "llvm/ADT/SmallSet.h"
37 #include "llvm/ADT/Statistic.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops");
44 STATISTIC(NumCSEed, "Number of hoisted machine instructions CSEed");
45 STATISTIC(NumPostRAHoisted,
46 "Number of machine instructions hoisted out of loops post regalloc");
49 class MachineLICM : public MachineFunctionPass {
52 const TargetMachine *TM;
53 const TargetInstrInfo *TII;
54 const TargetRegisterInfo *TRI;
55 const MachineFrameInfo *MFI;
56 MachineRegisterInfo *RegInfo;
58 // Various analyses that we use...
59 AliasAnalysis *AA; // Alias analysis info.
60 MachineLoopInfo *MLI; // Current MachineLoopInfo
61 MachineDominatorTree *DT; // Machine dominator tree for the cur loop
63 // State that is updated as we process loops
64 bool Changed; // True if a loop is changed.
65 MachineLoop *CurLoop; // The current loop we are working on.
66 MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
68 BitVector AllocatableSet;
70 // For each opcode, keep a list of potentail CSE instructions.
71 DenseMap<unsigned, std::vector<const MachineInstr*> > CSEMap;
74 static char ID; // Pass identification, replacement for typeid
76 MachineFunctionPass(&ID), PreRegAlloc(true) {}
78 explicit MachineLICM(bool PreRA) :
79 MachineFunctionPass(&ID), PreRegAlloc(PreRA) {}
81 virtual bool runOnMachineFunction(MachineFunction &MF);
83 const char *getPassName() const { return "Machine Instruction LICM"; }
85 // FIXME: Loop preheaders?
86 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
88 AU.addRequired<MachineLoopInfo>();
89 AU.addRequired<MachineDominatorTree>();
90 AU.addRequired<AliasAnalysis>();
91 AU.addPreserved<MachineLoopInfo>();
92 AU.addPreserved<MachineDominatorTree>();
93 MachineFunctionPass::getAnalysisUsage(AU);
96 virtual void releaseMemory() {
101 /// CandidateInfo - Keep track of information about hoisting candidates.
102 struct CandidateInfo {
106 CandidateInfo(MachineInstr *mi, unsigned def, int fi)
107 : MI(mi), Def(def), FI(fi) {}
110 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
111 /// invariants out to the preheader.
112 void HoistRegionPostRA();
114 /// HoistPostRA - When an instruction is found to only use loop invariant
115 /// operands that is safe to hoist, this instruction is called to do the
117 void HoistPostRA(MachineInstr *MI, unsigned Def);
119 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
120 /// gather register def and frame object update information.
121 void ProcessMI(MachineInstr *MI, unsigned *PhysRegDefs,
122 SmallSet<int, 32> &StoredFIs,
123 SmallVector<CandidateInfo, 32> &Candidates);
125 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the
127 void AddToLiveIns(unsigned Reg);
129 /// IsLICMCandidate - Returns true if the instruction may be a suitable
130 /// candidate for LICM. e.g. If the instruction is a call, then it's obviously
131 /// not safe to hoist it.
132 bool IsLICMCandidate(MachineInstr &I);
134 /// IsLoopInvariantInst - Returns true if the instruction is loop
135 /// invariant. I.e., all virtual register operands are defined outside of
136 /// the loop, physical registers aren't accessed (explicitly or implicitly),
137 /// and the instruction is hoistable.
139 bool IsLoopInvariantInst(MachineInstr &I);
141 /// IsProfitableToHoist - Return true if it is potentially profitable to
142 /// hoist the given loop invariant.
143 bool IsProfitableToHoist(MachineInstr &MI);
145 /// HoistRegion - Walk the specified region of the CFG (defined by all
146 /// blocks dominated by the specified block, and that are in the current
147 /// loop) in depth first order w.r.t the DominatorTree. This allows us to
148 /// visit definitions before uses, allowing us to hoist a loop body in one
149 /// pass without iteration.
151 void HoistRegion(MachineDomTreeNode *N);
153 /// isLoadFromConstantMemory - Return true if the given instruction is a
154 /// load from constant memory.
155 bool isLoadFromConstantMemory(MachineInstr *MI);
157 /// ExtractHoistableLoad - Unfold a load from the given machineinstr if
158 /// the load itself could be hoisted. Return the unfolded and hoistable
159 /// load, or null if the load couldn't be unfolded or if it wouldn't
161 MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
163 /// LookForDuplicate - Find an instruction amount PrevMIs that is a
164 /// duplicate of MI. Return this instruction if it's found.
165 const MachineInstr *LookForDuplicate(const MachineInstr *MI,
166 std::vector<const MachineInstr*> &PrevMIs);
168 /// EliminateCSE - Given a LICM'ed instruction, look for an instruction on
169 /// the preheader that compute the same value. If it's found, do a RAU on
170 /// with the definition of the existing instruction rather than hoisting
171 /// the instruction to the preheader.
172 bool EliminateCSE(MachineInstr *MI,
173 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI);
175 /// Hoist - When an instruction is found to only use loop invariant operands
176 /// that is safe to hoist, this instruction is called to do the dirty work.
178 void Hoist(MachineInstr *MI);
180 /// InitCSEMap - Initialize the CSE map with instructions that are in the
181 /// current loop preheader that may become duplicates of instructions that
182 /// are hoisted out of the loop.
183 void InitCSEMap(MachineBasicBlock *BB);
185 } // end anonymous namespace
187 char MachineLICM::ID = 0;
188 static RegisterPass<MachineLICM>
189 X("machinelicm", "Machine Loop Invariant Code Motion");
191 FunctionPass *llvm::createMachineLICMPass(bool PreRegAlloc) {
192 return new MachineLICM(PreRegAlloc);
195 /// LoopIsOuterMostWithPreheader - Test if the given loop is the outer-most
196 /// loop that has a preheader.
197 static bool LoopIsOuterMostWithPreheader(MachineLoop *CurLoop) {
198 for (MachineLoop *L = CurLoop->getParentLoop(); L; L = L->getParentLoop())
199 if (L->getLoopPreheader())
204 bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
206 DEBUG(dbgs() << "******** Pre-regalloc Machine LICM ********\n");
208 DEBUG(dbgs() << "******** Post-regalloc Machine LICM ********\n");
211 TM = &MF.getTarget();
212 TII = TM->getInstrInfo();
213 TRI = TM->getRegisterInfo();
214 MFI = MF.getFrameInfo();
215 RegInfo = &MF.getRegInfo();
216 AllocatableSet = TRI->getAllocatableSet(MF);
218 // Get our Loop information...
219 MLI = &getAnalysis<MachineLoopInfo>();
220 DT = &getAnalysis<MachineDominatorTree>();
221 AA = &getAnalysis<AliasAnalysis>();
223 for (MachineLoopInfo::iterator I = MLI->begin(), E = MLI->end(); I != E; ++I){
226 // If this is done before regalloc, only visit outer-most preheader-sporting
228 if (PreRegAlloc && !LoopIsOuterMostWithPreheader(CurLoop))
231 // Determine the block to which to hoist instructions. If we can't find a
232 // suitable loop preheader, we can't do any hoisting.
234 // FIXME: We are only hoisting if the basic block coming into this loop
235 // has only one successor. This isn't the case in general because we haven't
236 // broken critical edges or added preheaders.
237 CurPreheader = CurLoop->getLoopPreheader();
244 // CSEMap is initialized for loop header when the first instruction is
246 MachineDomTreeNode *N = DT->getNode(CurLoop->getHeader());
255 /// InstructionStoresToFI - Return true if instruction stores to the
257 static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
258 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
259 oe = MI->memoperands_end(); o != oe; ++o) {
260 if (!(*o)->isStore() || !(*o)->getValue())
262 if (const FixedStackPseudoSourceValue *Value =
263 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
264 if (Value->getFrameIndex() == FI)
271 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
272 /// gather register def and frame object update information.
273 void MachineLICM::ProcessMI(MachineInstr *MI,
274 unsigned *PhysRegDefs,
275 SmallSet<int, 32> &StoredFIs,
276 SmallVector<CandidateInfo, 32> &Candidates) {
277 bool RuledOut = false;
278 bool HasNonInvariantUse = false;
280 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
281 const MachineOperand &MO = MI->getOperand(i);
283 // Remember if the instruction stores to the frame index.
284 int FI = MO.getIndex();
285 if (!StoredFIs.count(FI) &&
286 MFI->isSpillSlotObjectIndex(FI) &&
287 InstructionStoresToFI(MI, FI))
288 StoredFIs.insert(FI);
289 HasNonInvariantUse = true;
295 unsigned Reg = MO.getReg();
298 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
299 "Not expecting virtual register!");
302 if (Reg && PhysRegDefs[Reg])
303 // If it's using a non-loop-invariant register, then it's obviously not
305 HasNonInvariantUse = true;
309 if (MO.isImplicit()) {
311 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
314 // Non-dead implicit def? This cannot be hoisted.
316 // No need to check if a dead implicit def is also defined by
317 // another instruction.
321 // FIXME: For now, avoid instructions with multiple defs, unless
322 // it's a dead implicit def.
328 // If we have already seen another instruction that defines the same
329 // register, then this is not safe.
330 if (++PhysRegDefs[Reg] > 1)
331 // MI defined register is seen defined by another instruction in
332 // the loop, it cannot be a LICM candidate.
334 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
335 if (++PhysRegDefs[*AS] > 1)
339 // Only consider reloads for now and remats which do not have register
340 // operands. FIXME: Consider unfold load folding instructions.
341 if (Def && !RuledOut) {
343 if ((!HasNonInvariantUse && IsLICMCandidate(*MI)) ||
344 (TII->isLoadFromStackSlot(MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
345 Candidates.push_back(CandidateInfo(MI, Def, FI));
349 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
350 /// invariants out to the preheader.
351 void MachineLICM::HoistRegionPostRA() {
352 unsigned NumRegs = TRI->getNumRegs();
353 unsigned *PhysRegDefs = new unsigned[NumRegs];
354 std::fill(PhysRegDefs, PhysRegDefs + NumRegs, 0);
356 SmallVector<CandidateInfo, 32> Candidates;
357 SmallSet<int, 32> StoredFIs;
359 // Walk the entire region, count number of defs for each register, and
360 // collect potential LICM candidates.
361 const std::vector<MachineBasicBlock*> Blocks = CurLoop->getBlocks();
362 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
363 MachineBasicBlock *BB = Blocks[i];
364 // Conservatively treat live-in's as an external def.
365 // FIXME: That means a reload that're reused in successor block(s) will not
367 for (MachineBasicBlock::livein_iterator I = BB->livein_begin(),
368 E = BB->livein_end(); I != E; ++I) {
371 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
375 for (MachineBasicBlock::iterator
376 MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
377 MachineInstr *MI = &*MII;
378 ProcessMI(MI, PhysRegDefs, StoredFIs, Candidates);
382 // Now evaluate whether the potential candidates qualify.
383 // 1. Check if the candidate defined register is defined by another
384 // instruction in the loop.
385 // 2. If the candidate is a load from stack slot (always true for now),
386 // check if the slot is stored anywhere in the loop.
387 for (unsigned i = 0, e = Candidates.size(); i != e; ++i) {
388 if (Candidates[i].FI != INT_MIN &&
389 StoredFIs.count(Candidates[i].FI))
392 if (PhysRegDefs[Candidates[i].Def] == 1) {
394 MachineInstr *MI = Candidates[i].MI;
395 for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
396 const MachineOperand &MO = MI->getOperand(j);
397 if (!MO.isReg() || MO.isDef() || !MO.getReg())
399 if (PhysRegDefs[MO.getReg()]) {
400 // If it's using a non-loop-invariant register, then it's obviously
401 // not safe to hoist.
407 HoistPostRA(MI, Candidates[i].Def);
411 delete[] PhysRegDefs;
414 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the current
415 /// loop, and make sure it is not killed by any instructions in the loop.
416 void MachineLICM::AddToLiveIns(unsigned Reg) {
417 const std::vector<MachineBasicBlock*> Blocks = CurLoop->getBlocks();
418 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
419 MachineBasicBlock *BB = Blocks[i];
420 if (!BB->isLiveIn(Reg))
422 for (MachineBasicBlock::iterator
423 MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
424 MachineInstr *MI = &*MII;
425 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
426 MachineOperand &MO = MI->getOperand(i);
427 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
428 if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
435 /// HoistPostRA - When an instruction is found to only use loop invariant
436 /// operands that is safe to hoist, this instruction is called to do the
438 void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
439 // Now move the instructions to the predecessor, inserting it before any
440 // terminator instructions.
442 dbgs() << "Hoisting " << *MI;
443 if (CurPreheader->getBasicBlock())
444 dbgs() << " to MachineBasicBlock "
445 << CurPreheader->getName();
446 if (MI->getParent()->getBasicBlock())
447 dbgs() << " from MachineBasicBlock "
448 << MI->getParent()->getName();
452 // Splice the instruction to the preheader.
453 MachineBasicBlock *MBB = MI->getParent();
454 CurPreheader->splice(CurPreheader->getFirstTerminator(), MBB, MI);
456 // Add register to livein list to all the BBs in the current loop since a
457 // loop invariant must be kept live throughout the whole loop. This is
458 // important to ensure later passes do not scavenge the def register.
465 /// HoistRegion - Walk the specified region of the CFG (defined by all blocks
466 /// dominated by the specified block, and that are in the current loop) in depth
467 /// first order w.r.t the DominatorTree. This allows us to visit definitions
468 /// before uses, allowing us to hoist a loop body in one pass without iteration.
470 void MachineLICM::HoistRegion(MachineDomTreeNode *N) {
471 assert(N != 0 && "Null dominator tree node?");
472 MachineBasicBlock *BB = N->getBlock();
474 // If this subregion is not in the top level loop at all, exit.
475 if (!CurLoop->contains(BB)) return;
477 for (MachineBasicBlock::iterator
478 MII = BB->begin(), E = BB->end(); MII != E; ) {
479 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
484 const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
485 for (unsigned I = 0, E = Children.size(); I != E; ++I)
486 HoistRegion(Children[I]);
489 /// IsLICMCandidate - Returns true if the instruction may be a suitable
490 /// candidate for LICM. e.g. If the instruction is a call, then it's obviously
491 /// not safe to hoist it.
492 bool MachineLICM::IsLICMCandidate(MachineInstr &I) {
493 if (I.isImplicitDef())
496 const TargetInstrDesc &TID = I.getDesc();
498 // Ignore stuff that we obviously can't hoist.
499 if (TID.mayStore() || TID.isCall() || TID.isTerminator() ||
500 TID.hasUnmodeledSideEffects())
504 // Okay, this instruction does a load. As a refinement, we allow the target
505 // to decide whether the loaded value is actually a constant. If so, we can
506 // actually use it as a load.
507 if (!I.isInvariantLoad(AA))
508 // FIXME: we should be able to hoist loads with no other side effects if
509 // there are no other instructions which can change memory in this loop.
510 // This is a trivial form of alias analysis.
516 /// IsLoopInvariantInst - Returns true if the instruction is loop
517 /// invariant. I.e., all virtual register operands are defined outside of the
518 /// loop, physical registers aren't accessed explicitly, and there are no side
519 /// effects that aren't captured by the operands or other flags.
521 bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
522 if (!IsLICMCandidate(I))
525 // The instruction is loop invariant if all of its operands are.
526 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
527 const MachineOperand &MO = I.getOperand(i);
532 unsigned Reg = MO.getReg();
533 if (Reg == 0) continue;
535 // Don't hoist an instruction that uses or defines a physical register.
536 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
538 // If the physreg has no defs anywhere, it's just an ambient register
539 // and we can freely move its uses. Alternatively, if it's allocatable,
540 // it could get allocated to something with a def during allocation.
541 if (!RegInfo->def_empty(Reg))
543 if (AllocatableSet.test(Reg))
545 // Check for a def among the register's aliases too.
546 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
547 unsigned AliasReg = *Alias;
548 if (!RegInfo->def_empty(AliasReg))
550 if (AllocatableSet.test(AliasReg))
553 // Otherwise it's safe to move.
555 } else if (!MO.isDead()) {
556 // A def that isn't dead. We can't move it.
558 } else if (CurLoop->getHeader()->isLiveIn(Reg)) {
559 // If the reg is live into the loop, we can't hoist an instruction
560 // which would clobber it.
568 assert(RegInfo->getVRegDef(Reg) &&
569 "Machine instr not mapped for this vreg?!");
571 // If the loop contains the definition of an operand, then the instruction
572 // isn't loop invariant.
573 if (CurLoop->contains(RegInfo->getVRegDef(Reg)))
577 // If we got this far, the instruction is loop invariant!
582 /// HasPHIUses - Return true if the specified register has any PHI use.
583 static bool HasPHIUses(unsigned Reg, MachineRegisterInfo *RegInfo) {
584 for (MachineRegisterInfo::use_iterator UI = RegInfo->use_begin(Reg),
585 UE = RegInfo->use_end(); UI != UE; ++UI) {
586 MachineInstr *UseMI = &*UI;
593 /// isLoadFromConstantMemory - Return true if the given instruction is a
594 /// load from constant memory. Machine LICM will hoist these even if they are
595 /// not re-materializable.
596 bool MachineLICM::isLoadFromConstantMemory(MachineInstr *MI) {
597 if (!MI->getDesc().mayLoad()) return false;
598 if (!MI->hasOneMemOperand()) return false;
599 MachineMemOperand *MMO = *MI->memoperands_begin();
600 if (MMO->isVolatile()) return false;
601 if (!MMO->getValue()) return false;
602 const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(MMO->getValue());
604 MachineFunction &MF = *MI->getParent()->getParent();
605 return PSV->isConstant(MF.getFrameInfo());
607 return AA->pointsToConstantMemory(MMO->getValue());
611 /// IsProfitableToHoist - Return true if it is potentially profitable to hoist
612 /// the given loop invariant.
613 bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
614 // FIXME: For now, only hoist re-materilizable instructions. LICM will
615 // increase register pressure. We want to make sure it doesn't increase
617 // Also hoist loads from constant memory, e.g. load from stubs, GOT. Hoisting
618 // these tend to help performance in low register pressure situation. The
619 // trade off is it may cause spill in high pressure situation. It will end up
620 // adding a store in the loop preheader. But the reload is no more expensive.
621 // The side benefit is these loads are frequently CSE'ed.
622 if (!TII->isTriviallyReMaterializable(&MI, AA)) {
623 if (!isLoadFromConstantMemory(&MI))
627 // If result(s) of this instruction is used by PHIs, then don't hoist it.
628 // The presence of joins makes it difficult for current register allocator
629 // implementation to perform remat.
630 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
631 const MachineOperand &MO = MI.getOperand(i);
632 if (!MO.isReg() || !MO.isDef())
634 if (HasPHIUses(MO.getReg(), RegInfo))
641 MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
642 // If not, we may be able to unfold a load and hoist that.
643 // First test whether the instruction is loading from an amenable
645 if (!isLoadFromConstantMemory(MI))
648 // Next determine the register class for a temporary register.
649 unsigned LoadRegIndex;
651 TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(),
653 /*UnfoldStore=*/false,
655 if (NewOpc == 0) return 0;
656 const TargetInstrDesc &TID = TII->get(NewOpc);
657 if (TID.getNumDefs() != 1) return 0;
658 const TargetRegisterClass *RC = TID.OpInfo[LoadRegIndex].getRegClass(TRI);
659 // Ok, we're unfolding. Create a temporary register and do the unfold.
660 unsigned Reg = RegInfo->createVirtualRegister(RC);
662 MachineFunction &MF = *MI->getParent()->getParent();
663 SmallVector<MachineInstr *, 2> NewMIs;
665 TII->unfoldMemoryOperand(MF, MI, Reg,
666 /*UnfoldLoad=*/true, /*UnfoldStore=*/false,
670 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
672 assert(NewMIs.size() == 2 &&
673 "Unfolded a load into multiple instructions!");
674 MachineBasicBlock *MBB = MI->getParent();
675 MBB->insert(MI, NewMIs[0]);
676 MBB->insert(MI, NewMIs[1]);
677 // If unfolding produced a load that wasn't loop-invariant or profitable to
678 // hoist, discard the new instructions and bail.
679 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
680 NewMIs[0]->eraseFromParent();
681 NewMIs[1]->eraseFromParent();
684 // Otherwise we successfully unfolded a load that we can hoist.
685 MI->eraseFromParent();
689 void MachineLICM::InitCSEMap(MachineBasicBlock *BB) {
690 for (MachineBasicBlock::iterator I = BB->begin(),E = BB->end(); I != E; ++I) {
691 const MachineInstr *MI = &*I;
692 // FIXME: For now, only hoist re-materilizable instructions. LICM will
693 // increase register pressure. We want to make sure it doesn't increase
695 if (TII->isTriviallyReMaterializable(MI, AA)) {
696 unsigned Opcode = MI->getOpcode();
697 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
698 CI = CSEMap.find(Opcode);
699 if (CI != CSEMap.end())
700 CI->second.push_back(MI);
702 std::vector<const MachineInstr*> CSEMIs;
703 CSEMIs.push_back(MI);
704 CSEMap.insert(std::make_pair(Opcode, CSEMIs));
711 MachineLICM::LookForDuplicate(const MachineInstr *MI,
712 std::vector<const MachineInstr*> &PrevMIs) {
713 for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) {
714 const MachineInstr *PrevMI = PrevMIs[i];
715 if (TII->produceSameValue(MI, PrevMI))
721 bool MachineLICM::EliminateCSE(MachineInstr *MI,
722 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI) {
723 if (CI == CSEMap.end())
726 if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
727 DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
729 // Replace virtual registers defined by MI by their counterparts defined
731 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
732 const MachineOperand &MO = MI->getOperand(i);
734 // Physical registers may not differ here.
735 assert((!MO.isReg() || MO.getReg() == 0 ||
736 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
737 MO.getReg() == Dup->getOperand(i).getReg()) &&
738 "Instructions with different phys regs are not identical!");
740 if (MO.isReg() && MO.isDef() &&
741 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
742 RegInfo->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg());
744 MI->eraseFromParent();
751 /// Hoist - When an instruction is found to use only loop invariant operands
752 /// that are safe to hoist, this instruction is called to do the dirty work.
754 void MachineLICM::Hoist(MachineInstr *MI) {
755 // First check whether we should hoist this instruction.
756 if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
757 // If not, try unfolding a hoistable load.
758 MI = ExtractHoistableLoad(MI);
762 // Now move the instructions to the predecessor, inserting it before any
763 // terminator instructions.
765 dbgs() << "Hoisting " << *MI;
766 if (CurPreheader->getBasicBlock())
767 dbgs() << " to MachineBasicBlock "
768 << CurPreheader->getName();
769 if (MI->getParent()->getBasicBlock())
770 dbgs() << " from MachineBasicBlock "
771 << MI->getParent()->getName();
775 // If this is the first instruction being hoisted to the preheader,
776 // initialize the CSE map with potential common expressions.
777 InitCSEMap(CurPreheader);
779 // Look for opportunity to CSE the hoisted instruction.
780 unsigned Opcode = MI->getOpcode();
781 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
782 CI = CSEMap.find(Opcode);
783 if (!EliminateCSE(MI, CI)) {
784 // Otherwise, splice the instruction to the preheader.
785 CurPreheader->splice(CurPreheader->getFirstTerminator(),MI->getParent(),MI);
787 // Add to the CSE map.
788 if (CI != CSEMap.end())
789 CI->second.push_back(MI);
791 std::vector<const MachineInstr*> CSEMIs;
792 CSEMIs.push_back(MI);
793 CSEMap.insert(std::make_pair(Opcode, CSEMIs));