1 //===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs loop invariant code motion on machine instructions. We
11 // attempt to remove as much code from the body of a loop as possible.
13 // This pass does not attempt to throttle itself to limit register pressure.
14 // The register allocation phases are expected to perform rematerialization
15 // to recover when register pressure is high.
17 // This pass is not intended to be a replacement or a complete alternative
18 // for the LLVM-IR-level LICM pass. It is only designed to hoist simple
19 // constructs that are not exposed before lowering and instruction selection.
21 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "machine-licm"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/PseudoSourceValue.h"
31 #include "llvm/Target/TargetLowering.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetInstrItineraries.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Analysis/AliasAnalysis.h"
37 #include "llvm/ADT/DenseMap.h"
38 #include "llvm/ADT/SmallSet.h"
39 #include "llvm/ADT/Statistic.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/raw_ostream.h"
47 TrackRegPressure("rp-aware-machine-licm",
48 cl::desc("Register pressure aware machine LICM"),
49 cl::init(false), cl::Hidden);
52 "Number of machine instructions hoisted out of loops");
54 "Number of instructions hoisted in low reg pressure situation");
55 STATISTIC(NumHighLatency,
56 "Number of high latency instructions hoisted");
58 "Number of hoisted machine instructions CSEed");
59 STATISTIC(NumPostRAHoisted,
60 "Number of machine instructions hoisted out of loops post regalloc");
63 class MachineLICM : public MachineFunctionPass {
66 const TargetMachine *TM;
67 const TargetInstrInfo *TII;
68 const TargetLowering *TLI;
69 const TargetRegisterInfo *TRI;
70 const MachineFrameInfo *MFI;
71 MachineRegisterInfo *MRI;
72 const InstrItineraryData *InstrItins;
74 // Various analyses that we use...
75 AliasAnalysis *AA; // Alias analysis info.
76 MachineLoopInfo *MLI; // Current MachineLoopInfo
77 MachineDominatorTree *DT; // Machine dominator tree for the cur loop
79 // State that is updated as we process loops
80 bool Changed; // True if a loop is changed.
81 bool FirstInLoop; // True if it's the first LICM in the loop.
82 MachineLoop *CurLoop; // The current loop we are working on.
83 MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
85 BitVector AllocatableSet;
87 // Track 'estimated' register pressure.
88 SmallSet<unsigned, 32> RegSeen;
89 SmallVector<unsigned, 8> RegPressure;
91 // Register pressure "limit" per register class. If the pressure
92 // is higher than the limit, then it's considered high.
93 SmallVector<unsigned, 8> RegLimit;
95 // Register pressure on path leading from loop preheader to current BB.
96 SmallVector<SmallVector<unsigned, 8>, 16> BackTrace;
98 // For each opcode, keep a list of potential CSE instructions.
99 DenseMap<unsigned, std::vector<const MachineInstr*> > CSEMap;
102 static char ID; // Pass identification, replacement for typeid
104 MachineFunctionPass(ID), PreRegAlloc(true) {}
106 explicit MachineLICM(bool PreRA) :
107 MachineFunctionPass(ID), PreRegAlloc(PreRA) {}
109 virtual bool runOnMachineFunction(MachineFunction &MF);
111 const char *getPassName() const { return "Machine Instruction LICM"; }
113 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
114 AU.setPreservesCFG();
115 AU.addRequired<MachineLoopInfo>();
116 AU.addRequired<MachineDominatorTree>();
117 AU.addRequired<AliasAnalysis>();
118 AU.addPreserved<MachineLoopInfo>();
119 AU.addPreserved<MachineDominatorTree>();
120 MachineFunctionPass::getAnalysisUsage(AU);
123 virtual void releaseMemory() {
127 for (DenseMap<unsigned,std::vector<const MachineInstr*> >::iterator
128 CI = CSEMap.begin(), CE = CSEMap.end(); CI != CE; ++CI)
134 /// CandidateInfo - Keep track of information about hoisting candidates.
135 struct CandidateInfo {
139 CandidateInfo(MachineInstr *mi, unsigned def, int fi)
140 : MI(mi), Def(def), FI(fi) {}
143 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
144 /// invariants out to the preheader.
145 void HoistRegionPostRA();
147 /// HoistPostRA - When an instruction is found to only use loop invariant
148 /// operands that is safe to hoist, this instruction is called to do the
150 void HoistPostRA(MachineInstr *MI, unsigned Def);
152 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
153 /// gather register def and frame object update information.
154 void ProcessMI(MachineInstr *MI, unsigned *PhysRegDefs,
155 SmallSet<int, 32> &StoredFIs,
156 SmallVector<CandidateInfo, 32> &Candidates);
158 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the
160 void AddToLiveIns(unsigned Reg);
162 /// IsLICMCandidate - Returns true if the instruction may be a suitable
163 /// candidate for LICM. e.g. If the instruction is a call, then it's
164 /// obviously not safe to hoist it.
165 bool IsLICMCandidate(MachineInstr &I);
167 /// IsLoopInvariantInst - Returns true if the instruction is loop
168 /// invariant. I.e., all virtual register operands are defined outside of
169 /// the loop, physical registers aren't accessed (explicitly or implicitly),
170 /// and the instruction is hoistable.
172 bool IsLoopInvariantInst(MachineInstr &I);
174 /// ComputeOperandLatency - Compute operand latency between a def of 'Reg'
175 /// and an use in the current loop.
176 int ComputeOperandLatency(MachineInstr &MI, unsigned DefIdx, unsigned Reg);
178 /// IncreaseHighRegPressure - Visit BBs from preheader to current BB, check
179 /// if hoisting an instruction of the given cost matrix can cause high
180 /// register pressure.
181 bool IncreaseHighRegPressure(DenseMap<unsigned, int> &Cost);
183 /// IsProfitableToHoist - Return true if it is potentially profitable to
184 /// hoist the given loop invariant.
185 bool IsProfitableToHoist(MachineInstr &MI);
187 /// HoistRegion - Walk the specified region of the CFG (defined by all
188 /// blocks dominated by the specified block, and that are in the current
189 /// loop) in depth first order w.r.t the DominatorTree. This allows us to
190 /// visit definitions before uses, allowing us to hoist a loop body in one
191 /// pass without iteration.
193 void HoistRegion(MachineDomTreeNode *N, bool IsHeader = false);
195 /// InitRegPressure - Find all virtual register references that are liveout
196 /// of the preheader to initialize the starting "register pressure". Note
197 /// this does not count live through (livein but not used) registers.
198 void InitRegPressure(MachineBasicBlock *BB);
200 /// UpdateRegPressureBefore / UpdateRegPressureAfter - Update estimate of
201 /// register pressure before and after executing a specifi instruction.
202 void UpdateRegPressureBefore(const MachineInstr *MI);
203 void UpdateRegPressureAfter(const MachineInstr *MI);
205 /// isLoadFromConstantMemory - Return true if the given instruction is a
206 /// load from constant memory.
207 bool isLoadFromConstantMemory(MachineInstr *MI);
209 /// ExtractHoistableLoad - Unfold a load from the given machineinstr if
210 /// the load itself could be hoisted. Return the unfolded and hoistable
211 /// load, or null if the load couldn't be unfolded or if it wouldn't
213 MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
215 /// LookForDuplicate - Find an instruction amount PrevMIs that is a
216 /// duplicate of MI. Return this instruction if it's found.
217 const MachineInstr *LookForDuplicate(const MachineInstr *MI,
218 std::vector<const MachineInstr*> &PrevMIs);
220 /// EliminateCSE - Given a LICM'ed instruction, look for an instruction on
221 /// the preheader that compute the same value. If it's found, do a RAU on
222 /// with the definition of the existing instruction rather than hoisting
223 /// the instruction to the preheader.
224 bool EliminateCSE(MachineInstr *MI,
225 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI);
227 /// Hoist - When an instruction is found to only use loop invariant operands
228 /// that is safe to hoist, this instruction is called to do the dirty work.
230 void Hoist(MachineInstr *MI, MachineBasicBlock *Preheader);
232 /// InitCSEMap - Initialize the CSE map with instructions that are in the
233 /// current loop preheader that may become duplicates of instructions that
234 /// are hoisted out of the loop.
235 void InitCSEMap(MachineBasicBlock *BB);
237 /// getCurPreheader - Get the preheader for the current loop, splitting
238 /// a critical edge if needed.
239 MachineBasicBlock *getCurPreheader();
241 } // end anonymous namespace
243 char MachineLICM::ID = 0;
244 INITIALIZE_PASS_BEGIN(MachineLICM, "machinelicm",
245 "Machine Loop Invariant Code Motion", false, false)
246 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
247 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
248 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
249 INITIALIZE_PASS_END(MachineLICM, "machinelicm",
250 "Machine Loop Invariant Code Motion", false, false)
252 FunctionPass *llvm::createMachineLICMPass(bool PreRegAlloc) {
253 return new MachineLICM(PreRegAlloc);
256 /// LoopIsOuterMostWithPredecessor - Test if the given loop is the outer-most
257 /// loop that has a unique predecessor.
258 static bool LoopIsOuterMostWithPredecessor(MachineLoop *CurLoop) {
259 // Check whether this loop even has a unique predecessor.
260 if (!CurLoop->getLoopPredecessor())
262 // Ok, now check to see if any of its outer loops do.
263 for (MachineLoop *L = CurLoop->getParentLoop(); L; L = L->getParentLoop())
264 if (L->getLoopPredecessor())
266 // None of them did, so this is the outermost with a unique predecessor.
270 bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
272 DEBUG(dbgs() << "******** Pre-regalloc Machine LICM: ");
274 DEBUG(dbgs() << "******** Post-regalloc Machine LICM: ");
275 DEBUG(dbgs() << MF.getFunction()->getName() << " ********\n");
277 Changed = FirstInLoop = false;
278 TM = &MF.getTarget();
279 TII = TM->getInstrInfo();
280 TLI = TM->getTargetLowering();
281 TRI = TM->getRegisterInfo();
282 MFI = MF.getFrameInfo();
283 MRI = &MF.getRegInfo();
284 InstrItins = TM->getInstrItineraryData();
285 AllocatableSet = TRI->getAllocatableSet(MF);
288 // Estimate register pressure during pre-regalloc pass.
289 unsigned NumRC = TRI->getNumRegClasses();
290 RegPressure.resize(NumRC);
291 std::fill(RegPressure.begin(), RegPressure.end(), 0);
292 RegLimit.resize(NumRC);
293 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
294 E = TRI->regclass_end(); I != E; ++I)
295 RegLimit[(*I)->getID()] = TLI->getRegPressureLimit(*I, MF);
298 // Get our Loop information...
299 MLI = &getAnalysis<MachineLoopInfo>();
300 DT = &getAnalysis<MachineDominatorTree>();
301 AA = &getAnalysis<AliasAnalysis>();
303 SmallVector<MachineLoop *, 8> Worklist(MLI->begin(), MLI->end());
304 while (!Worklist.empty()) {
305 CurLoop = Worklist.pop_back_val();
308 // If this is done before regalloc, only visit outer-most preheader-sporting
310 if (PreRegAlloc && !LoopIsOuterMostWithPredecessor(CurLoop)) {
311 Worklist.append(CurLoop->begin(), CurLoop->end());
318 // CSEMap is initialized for loop header when the first instruction is
320 MachineDomTreeNode *N = DT->getNode(CurLoop->getHeader());
322 HoistRegion(N, true);
330 /// InstructionStoresToFI - Return true if instruction stores to the
332 static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
333 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
334 oe = MI->memoperands_end(); o != oe; ++o) {
335 if (!(*o)->isStore() || !(*o)->getValue())
337 if (const FixedStackPseudoSourceValue *Value =
338 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
339 if (Value->getFrameIndex() == FI)
346 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
347 /// gather register def and frame object update information.
348 void MachineLICM::ProcessMI(MachineInstr *MI,
349 unsigned *PhysRegDefs,
350 SmallSet<int, 32> &StoredFIs,
351 SmallVector<CandidateInfo, 32> &Candidates) {
352 bool RuledOut = false;
353 bool HasNonInvariantUse = false;
355 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
356 const MachineOperand &MO = MI->getOperand(i);
358 // Remember if the instruction stores to the frame index.
359 int FI = MO.getIndex();
360 if (!StoredFIs.count(FI) &&
361 MFI->isSpillSlotObjectIndex(FI) &&
362 InstructionStoresToFI(MI, FI))
363 StoredFIs.insert(FI);
364 HasNonInvariantUse = true;
370 unsigned Reg = MO.getReg();
373 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
374 "Not expecting virtual register!");
377 if (Reg && PhysRegDefs[Reg])
378 // If it's using a non-loop-invariant register, then it's obviously not
380 HasNonInvariantUse = true;
384 if (MO.isImplicit()) {
386 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
389 // Non-dead implicit def? This cannot be hoisted.
391 // No need to check if a dead implicit def is also defined by
392 // another instruction.
396 // FIXME: For now, avoid instructions with multiple defs, unless
397 // it's a dead implicit def.
403 // If we have already seen another instruction that defines the same
404 // register, then this is not safe.
405 if (++PhysRegDefs[Reg] > 1)
406 // MI defined register is seen defined by another instruction in
407 // the loop, it cannot be a LICM candidate.
409 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
410 if (++PhysRegDefs[*AS] > 1)
414 // Only consider reloads for now and remats which do not have register
415 // operands. FIXME: Consider unfold load folding instructions.
416 if (Def && !RuledOut) {
418 if ((!HasNonInvariantUse && IsLICMCandidate(*MI)) ||
419 (TII->isLoadFromStackSlot(MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
420 Candidates.push_back(CandidateInfo(MI, Def, FI));
424 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
425 /// invariants out to the preheader.
426 void MachineLICM::HoistRegionPostRA() {
427 unsigned NumRegs = TRI->getNumRegs();
428 unsigned *PhysRegDefs = new unsigned[NumRegs];
429 std::fill(PhysRegDefs, PhysRegDefs + NumRegs, 0);
431 SmallVector<CandidateInfo, 32> Candidates;
432 SmallSet<int, 32> StoredFIs;
434 // Walk the entire region, count number of defs for each register, and
435 // collect potential LICM candidates.
436 const std::vector<MachineBasicBlock*> Blocks = CurLoop->getBlocks();
437 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
438 MachineBasicBlock *BB = Blocks[i];
439 // Conservatively treat live-in's as an external def.
440 // FIXME: That means a reload that're reused in successor block(s) will not
442 for (MachineBasicBlock::livein_iterator I = BB->livein_begin(),
443 E = BB->livein_end(); I != E; ++I) {
446 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
450 for (MachineBasicBlock::iterator
451 MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
452 MachineInstr *MI = &*MII;
453 ProcessMI(MI, PhysRegDefs, StoredFIs, Candidates);
457 // Now evaluate whether the potential candidates qualify.
458 // 1. Check if the candidate defined register is defined by another
459 // instruction in the loop.
460 // 2. If the candidate is a load from stack slot (always true for now),
461 // check if the slot is stored anywhere in the loop.
462 for (unsigned i = 0, e = Candidates.size(); i != e; ++i) {
463 if (Candidates[i].FI != INT_MIN &&
464 StoredFIs.count(Candidates[i].FI))
467 if (PhysRegDefs[Candidates[i].Def] == 1) {
469 MachineInstr *MI = Candidates[i].MI;
470 for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
471 const MachineOperand &MO = MI->getOperand(j);
472 if (!MO.isReg() || MO.isDef() || !MO.getReg())
474 if (PhysRegDefs[MO.getReg()]) {
475 // If it's using a non-loop-invariant register, then it's obviously
476 // not safe to hoist.
482 HoistPostRA(MI, Candidates[i].Def);
486 delete[] PhysRegDefs;
489 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the current
490 /// loop, and make sure it is not killed by any instructions in the loop.
491 void MachineLICM::AddToLiveIns(unsigned Reg) {
492 const std::vector<MachineBasicBlock*> Blocks = CurLoop->getBlocks();
493 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
494 MachineBasicBlock *BB = Blocks[i];
495 if (!BB->isLiveIn(Reg))
497 for (MachineBasicBlock::iterator
498 MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
499 MachineInstr *MI = &*MII;
500 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
501 MachineOperand &MO = MI->getOperand(i);
502 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
503 if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
510 /// HoistPostRA - When an instruction is found to only use loop invariant
511 /// operands that is safe to hoist, this instruction is called to do the
513 void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
514 MachineBasicBlock *Preheader = getCurPreheader();
515 if (!Preheader) return;
517 // Now move the instructions to the predecessor, inserting it before any
518 // terminator instructions.
520 dbgs() << "Hoisting " << *MI;
521 if (Preheader->getBasicBlock())
522 dbgs() << " to MachineBasicBlock "
523 << Preheader->getName();
524 if (MI->getParent()->getBasicBlock())
525 dbgs() << " from MachineBasicBlock "
526 << MI->getParent()->getName();
530 // Splice the instruction to the preheader.
531 MachineBasicBlock *MBB = MI->getParent();
532 Preheader->splice(Preheader->getFirstTerminator(), MBB, MI);
534 // Add register to livein list to all the BBs in the current loop since a
535 // loop invariant must be kept live throughout the whole loop. This is
536 // important to ensure later passes do not scavenge the def register.
543 /// HoistRegion - Walk the specified region of the CFG (defined by all blocks
544 /// dominated by the specified block, and that are in the current loop) in depth
545 /// first order w.r.t the DominatorTree. This allows us to visit definitions
546 /// before uses, allowing us to hoist a loop body in one pass without iteration.
548 void MachineLICM::HoistRegion(MachineDomTreeNode *N, bool IsHeader) {
549 assert(N != 0 && "Null dominator tree node?");
550 MachineBasicBlock *BB = N->getBlock();
552 // If this subregion is not in the top level loop at all, exit.
553 if (!CurLoop->contains(BB)) return;
555 MachineBasicBlock *Preheader = getCurPreheader();
559 if (TrackRegPressure) {
561 // Compute registers which are liveout of preheader.
564 InitRegPressure(Preheader);
567 // Remember livein register pressure.
568 BackTrace.push_back(RegPressure);
571 for (MachineBasicBlock::iterator
572 MII = BB->begin(), E = BB->end(); MII != E; ) {
573 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
574 MachineInstr *MI = &*MII;
576 if (TrackRegPressure)
577 UpdateRegPressureBefore(MI);
578 Hoist(MI, Preheader);
579 if (TrackRegPressure)
580 UpdateRegPressureAfter(MI);
585 // Don't hoist things out of a large switch statement. This often causes
586 // code to be hoisted that wasn't going to be executed, and increases
587 // register pressure in a situation where it's likely to matter.
588 if (BB->succ_size() < 25) {
589 const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
590 for (unsigned I = 0, E = Children.size(); I != E; ++I)
591 HoistRegion(Children[I]);
594 if (TrackRegPressure)
595 BackTrace.pop_back();
598 /// InitRegPressure - Find all virtual register references that are liveout of
599 /// the preheader to initialize the starting "register pressure". Note this
600 /// does not count live through (livein but not used) registers.
601 void MachineLICM::InitRegPressure(MachineBasicBlock *BB) {
602 std::fill(RegPressure.begin(), RegPressure.end(), 0);
604 for (MachineBasicBlock::iterator MII = BB->begin(), E = BB->end();
606 MachineInstr *MI = &*MII;
607 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
608 const MachineOperand &MO = MI->getOperand(i);
609 if (!MO.isReg() || MO.isImplicit())
611 unsigned Reg = MO.getReg();
612 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
615 bool isNew = !RegSeen.insert(Reg);
616 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
617 EVT VT = *RC->vt_begin();
618 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
620 RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
622 if (isNew && !MO.isKill())
623 // Haven't seen this, it must be a livein.
624 RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
625 else if (!isNew && MO.isKill())
626 RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT);
632 /// UpdateRegPressureBefore / UpdateRegPressureAfter - Update estimate of
633 /// register pressure before and after executing a specifi instruction.
634 void MachineLICM::UpdateRegPressureBefore(const MachineInstr *MI) {
635 bool NoImpact = MI->isImplicitDef() || MI->isPHI();
637 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
638 const MachineOperand &MO = MI->getOperand(i);
639 if (!MO.isReg() || MO.isImplicit() || !MO.isUse())
641 unsigned Reg = MO.getReg();
642 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
645 bool isNew = !RegSeen.insert(Reg);
649 if (!isNew && MO.isKill()) {
650 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
651 EVT VT = *RC->vt_begin();
652 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
653 unsigned RCCost = TLI->getRepRegClassCostFor(VT);
655 assert(RCCost <= RegPressure[RCId]);
656 RegPressure[RCId] -= RCCost;
661 void MachineLICM::UpdateRegPressureAfter(const MachineInstr *MI) {
662 bool NoImpact = MI->isImplicitDef() || MI->isPHI();
664 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
665 const MachineOperand &MO = MI->getOperand(i);
666 if (!MO.isReg() || MO.isImplicit() || !MO.isDef())
668 unsigned Reg = MO.getReg();
669 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
676 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
677 EVT VT = *RC->vt_begin();
678 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
679 unsigned RCCost = TLI->getRepRegClassCostFor(VT);
680 RegPressure[RCId] += RCCost;
684 /// IsLICMCandidate - Returns true if the instruction may be a suitable
685 /// candidate for LICM. e.g. If the instruction is a call, then it's obviously
686 /// not safe to hoist it.
687 bool MachineLICM::IsLICMCandidate(MachineInstr &I) {
688 // Check if it's safe to move the instruction.
689 bool DontMoveAcrossStore = true;
690 if (!I.isSafeToMove(TII, AA, DontMoveAcrossStore))
696 /// IsLoopInvariantInst - Returns true if the instruction is loop
697 /// invariant. I.e., all virtual register operands are defined outside of the
698 /// loop, physical registers aren't accessed explicitly, and there are no side
699 /// effects that aren't captured by the operands or other flags.
701 bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
702 if (!IsLICMCandidate(I))
705 // The instruction is loop invariant if all of its operands are.
706 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
707 const MachineOperand &MO = I.getOperand(i);
712 unsigned Reg = MO.getReg();
713 if (Reg == 0) continue;
715 // Don't hoist an instruction that uses or defines a physical register.
716 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
718 // If the physreg has no defs anywhere, it's just an ambient register
719 // and we can freely move its uses. Alternatively, if it's allocatable,
720 // it could get allocated to something with a def during allocation.
721 if (!MRI->def_empty(Reg))
723 if (AllocatableSet.test(Reg))
725 // Check for a def among the register's aliases too.
726 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
727 unsigned AliasReg = *Alias;
728 if (!MRI->def_empty(AliasReg))
730 if (AllocatableSet.test(AliasReg))
733 // Otherwise it's safe to move.
735 } else if (!MO.isDead()) {
736 // A def that isn't dead. We can't move it.
738 } else if (CurLoop->getHeader()->isLiveIn(Reg)) {
739 // If the reg is live into the loop, we can't hoist an instruction
740 // which would clobber it.
748 assert(MRI->getVRegDef(Reg) &&
749 "Machine instr not mapped for this vreg?!");
751 // If the loop contains the definition of an operand, then the instruction
752 // isn't loop invariant.
753 if (CurLoop->contains(MRI->getVRegDef(Reg)))
757 // If we got this far, the instruction is loop invariant!
762 /// HasPHIUses - Return true if the specified register has any PHI use.
763 static bool HasPHIUses(unsigned Reg, MachineRegisterInfo *MRI) {
764 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
765 UE = MRI->use_end(); UI != UE; ++UI) {
766 MachineInstr *UseMI = &*UI;
773 /// isLoadFromConstantMemory - Return true if the given instruction is a
774 /// load from constant memory. Machine LICM will hoist these even if they are
775 /// not re-materializable.
776 bool MachineLICM::isLoadFromConstantMemory(MachineInstr *MI) {
777 if (!MI->getDesc().mayLoad()) return false;
778 if (!MI->hasOneMemOperand()) return false;
779 MachineMemOperand *MMO = *MI->memoperands_begin();
780 if (MMO->isVolatile()) return false;
781 if (!MMO->getValue()) return false;
782 const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(MMO->getValue());
784 MachineFunction &MF = *MI->getParent()->getParent();
785 return PSV->isConstant(MF.getFrameInfo());
787 return AA->pointsToConstantMemory(MMO->getValue());
791 /// ComputeOperandLatency - Compute operand latency between a def of 'Reg'
792 /// and an use in the current loop.
793 int MachineLICM::ComputeOperandLatency(MachineInstr &MI,
794 unsigned DefIdx, unsigned Reg) {
795 if (MRI->use_nodbg_empty(Reg))
796 // No use? Return arbitrary large number!
800 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
801 E = MRI->use_nodbg_end(); I != E; ++I) {
802 MachineInstr *UseMI = &*I;
803 if (!CurLoop->contains(UseMI->getParent()))
805 for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
806 const MachineOperand &MO = UseMI->getOperand(i);
807 if (!MO.isReg() || !MO.isUse())
809 unsigned MOReg = MO.getReg();
813 int UseCycle = TII->getOperandLatency(InstrItins, &MI, DefIdx, UseMI, i);
814 Latency = std::max(Latency, UseCycle);
822 Latency = InstrItins->getOperandCycle(MI.getDesc().getSchedClass(), DefIdx);
827 /// IncreaseHighRegPressure - Visit BBs from preheader to current BB, check
828 /// if hoisting an instruction of the given cost matrix can cause high
829 /// register pressure.
830 bool MachineLICM::IncreaseHighRegPressure(DenseMap<unsigned, int> &Cost) {
831 for (unsigned i = BackTrace.size(); i != 0; --i) {
832 bool AnyIncrease = false;
833 SmallVector<unsigned, 8> &RP = BackTrace[i-1];
834 for (DenseMap<unsigned, int>::iterator CI = Cost.begin(), CE = Cost.end();
839 unsigned RCId = CI->first;
840 if (RP[RCId] + CI->second >= RegLimit[RCId])
845 // Hoisting the instruction doesn't increase register pressure.
852 /// IsProfitableToHoist - Return true if it is potentially profitable to hoist
853 /// the given loop invariant.
854 bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
855 if (MI.isImplicitDef())
858 // FIXME: For now, only hoist re-materilizable instructions. LICM will
859 // increase register pressure. We want to make sure it doesn't increase
861 // Also hoist loads from constant memory, e.g. load from stubs, GOT. Hoisting
862 // these tend to help performance in low register pressure situation. The
863 // trade off is it may cause spill in high pressure situation. It will end up
864 // adding a store in the loop preheader. But the reload is no more expensive.
865 // The side benefit is these loads are frequently CSE'ed.
866 if (!TrackRegPressure || MI.getDesc().isAsCheapAsAMove()) {
867 if (!TII->isTriviallyReMaterializable(&MI, AA) &&
868 !isLoadFromConstantMemory(&MI))
871 // In low register pressure situation, we can be more aggressive about
872 // hoisting. Also, favors hoisting long latency instructions even in
873 // moderately high pressure situation.
874 DenseMap<unsigned, int> Cost;
875 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
876 const MachineOperand &MO = MI.getOperand(i);
877 if (!MO.isReg() || MO.isImplicit())
879 unsigned Reg = MO.getReg();
880 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
883 if (InstrItins && !InstrItins->isEmpty()) {
884 int Cycle = ComputeOperandLatency(MI, i, Reg);
886 // FIXME: Target specific high latency limit?
892 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
893 EVT VT = *RC->vt_begin();
894 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
895 unsigned RCCost = TLI->getRepRegClassCostFor(VT);
896 DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
897 // If the instruction is not register pressure neutrail (or better),
898 // check if hoisting it will cause high register pressure in BB's
899 // leading up to this point.
900 if (CI != Cost.end())
901 CI->second += RCCost;
903 Cost.insert(std::make_pair(RCId, RCCost));
904 } else if (MO.isKill()) {
905 // Is a virtual register use is a kill, hoisting it out of the loop
906 // may actually reduce register pressure or be register pressure
908 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
909 EVT VT = *RC->vt_begin();
910 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
911 unsigned RCCost = TLI->getRepRegClassCostFor(VT);
912 DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
913 if (CI != Cost.end())
914 CI->second -= RCCost;
916 Cost.insert(std::make_pair(RCId, -RCCost));
920 // Visit BBs from preheader to current BB, if hoisting this doesn't cause
921 // high register pressure, then it's safe to proceed.
922 if (!IncreaseHighRegPressure(Cost)) {
927 // High register pressure situation, only hoist if the instruction is going to
929 if (!TII->isTriviallyReMaterializable(&MI, AA) &&
930 !isLoadFromConstantMemory(&MI))
934 // If result(s) of this instruction is used by PHIs, then don't hoist it.
935 // The presence of joins makes it difficult for current register allocator
936 // implementation to perform remat.
937 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
938 const MachineOperand &MO = MI.getOperand(i);
939 if (!MO.isReg() || !MO.isDef())
941 if (HasPHIUses(MO.getReg(), MRI))
948 MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
949 // Don't unfold simple loads.
950 if (MI->getDesc().canFoldAsLoad())
953 // If not, we may be able to unfold a load and hoist that.
954 // First test whether the instruction is loading from an amenable
956 if (!isLoadFromConstantMemory(MI))
959 // Next determine the register class for a temporary register.
960 unsigned LoadRegIndex;
962 TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(),
964 /*UnfoldStore=*/false,
966 if (NewOpc == 0) return 0;
967 const TargetInstrDesc &TID = TII->get(NewOpc);
968 if (TID.getNumDefs() != 1) return 0;
969 const TargetRegisterClass *RC = TID.OpInfo[LoadRegIndex].getRegClass(TRI);
970 // Ok, we're unfolding. Create a temporary register and do the unfold.
971 unsigned Reg = MRI->createVirtualRegister(RC);
973 MachineFunction &MF = *MI->getParent()->getParent();
974 SmallVector<MachineInstr *, 2> NewMIs;
976 TII->unfoldMemoryOperand(MF, MI, Reg,
977 /*UnfoldLoad=*/true, /*UnfoldStore=*/false,
981 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
983 assert(NewMIs.size() == 2 &&
984 "Unfolded a load into multiple instructions!");
985 MachineBasicBlock *MBB = MI->getParent();
986 MBB->insert(MI, NewMIs[0]);
987 MBB->insert(MI, NewMIs[1]);
988 // If unfolding produced a load that wasn't loop-invariant or profitable to
989 // hoist, discard the new instructions and bail.
990 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
991 NewMIs[0]->eraseFromParent();
992 NewMIs[1]->eraseFromParent();
995 // Otherwise we successfully unfolded a load that we can hoist.
996 MI->eraseFromParent();
1000 void MachineLICM::InitCSEMap(MachineBasicBlock *BB) {
1001 for (MachineBasicBlock::iterator I = BB->begin(),E = BB->end(); I != E; ++I) {
1002 const MachineInstr *MI = &*I;
1003 // FIXME: For now, only hoist re-materilizable instructions. LICM will
1004 // increase register pressure. We want to make sure it doesn't increase
1006 if (TII->isTriviallyReMaterializable(MI, AA)) {
1007 unsigned Opcode = MI->getOpcode();
1008 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
1009 CI = CSEMap.find(Opcode);
1010 if (CI != CSEMap.end())
1011 CI->second.push_back(MI);
1013 std::vector<const MachineInstr*> CSEMIs;
1014 CSEMIs.push_back(MI);
1015 CSEMap.insert(std::make_pair(Opcode, CSEMIs));
1022 MachineLICM::LookForDuplicate(const MachineInstr *MI,
1023 std::vector<const MachineInstr*> &PrevMIs) {
1024 for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) {
1025 const MachineInstr *PrevMI = PrevMIs[i];
1026 if (TII->produceSameValue(MI, PrevMI))
1032 bool MachineLICM::EliminateCSE(MachineInstr *MI,
1033 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI) {
1034 // Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
1035 // the undef property onto uses.
1036 if (CI == CSEMap.end() || MI->isImplicitDef())
1039 if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
1040 DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
1042 // Replace virtual registers defined by MI by their counterparts defined
1044 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1045 const MachineOperand &MO = MI->getOperand(i);
1047 // Physical registers may not differ here.
1048 assert((!MO.isReg() || MO.getReg() == 0 ||
1049 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
1050 MO.getReg() == Dup->getOperand(i).getReg()) &&
1051 "Instructions with different phys regs are not identical!");
1053 if (MO.isReg() && MO.isDef() &&
1054 !TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
1055 MRI->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg());
1056 MRI->clearKillFlags(Dup->getOperand(i).getReg());
1059 MI->eraseFromParent();
1066 /// Hoist - When an instruction is found to use only loop invariant operands
1067 /// that are safe to hoist, this instruction is called to do the dirty work.
1069 void MachineLICM::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
1070 // First check whether we should hoist this instruction.
1071 if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
1072 // If not, try unfolding a hoistable load.
1073 MI = ExtractHoistableLoad(MI);
1077 // Now move the instructions to the predecessor, inserting it before any
1078 // terminator instructions.
1080 dbgs() << "Hoisting " << *MI;
1081 if (Preheader->getBasicBlock())
1082 dbgs() << " to MachineBasicBlock "
1083 << Preheader->getName();
1084 if (MI->getParent()->getBasicBlock())
1085 dbgs() << " from MachineBasicBlock "
1086 << MI->getParent()->getName();
1090 // If this is the first instruction being hoisted to the preheader,
1091 // initialize the CSE map with potential common expressions.
1093 InitCSEMap(Preheader);
1094 FirstInLoop = false;
1097 // Look for opportunity to CSE the hoisted instruction.
1098 unsigned Opcode = MI->getOpcode();
1099 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
1100 CI = CSEMap.find(Opcode);
1101 if (!EliminateCSE(MI, CI)) {
1102 // Otherwise, splice the instruction to the preheader.
1103 Preheader->splice(Preheader->getFirstTerminator(),MI->getParent(),MI);
1105 // Clear the kill flags of any register this instruction defines,
1106 // since they may need to be live throughout the entire loop
1107 // rather than just live for part of it.
1108 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1109 MachineOperand &MO = MI->getOperand(i);
1110 if (MO.isReg() && MO.isDef() && !MO.isDead())
1111 MRI->clearKillFlags(MO.getReg());
1114 // Add to the CSE map.
1115 if (CI != CSEMap.end())
1116 CI->second.push_back(MI);
1118 std::vector<const MachineInstr*> CSEMIs;
1119 CSEMIs.push_back(MI);
1120 CSEMap.insert(std::make_pair(Opcode, CSEMIs));
1128 MachineBasicBlock *MachineLICM::getCurPreheader() {
1129 // Determine the block to which to hoist instructions. If we can't find a
1130 // suitable loop predecessor, we can't do any hoisting.
1132 // If we've tried to get a preheader and failed, don't try again.
1133 if (CurPreheader == reinterpret_cast<MachineBasicBlock *>(-1))
1136 if (!CurPreheader) {
1137 CurPreheader = CurLoop->getLoopPreheader();
1138 if (!CurPreheader) {
1139 MachineBasicBlock *Pred = CurLoop->getLoopPredecessor();
1141 CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
1145 CurPreheader = Pred->SplitCriticalEdge(CurLoop->getHeader(), this);
1146 if (!CurPreheader) {
1147 CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
1152 return CurPreheader;