1 //===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs loop invariant code motion on machine instructions. We
11 // attempt to remove as much code from the body of a loop as possible.
13 // This pass does not attempt to throttle itself to limit register pressure.
14 // The register allocation phases are expected to perform rematerialization
15 // to recover when register pressure is high.
17 // This pass is not intended to be a replacement or a complete alternative
18 // for the LLVM-IR-level LICM pass. It is only designed to hoist simple
19 // constructs that are not exposed before lowering and instruction selection.
21 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "machine-licm"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/PseudoSourceValue.h"
31 #include "llvm/MC/MCInstrItineraries.h"
32 #include "llvm/Target/TargetLowering.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Analysis/AliasAnalysis.h"
37 #include "llvm/ADT/DenseMap.h"
38 #include "llvm/ADT/SmallSet.h"
39 #include "llvm/ADT/Statistic.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/raw_ostream.h"
45 "Number of machine instructions hoisted out of loops");
47 "Number of instructions hoisted in low reg pressure situation");
48 STATISTIC(NumHighLatency,
49 "Number of high latency instructions hoisted");
51 "Number of hoisted machine instructions CSEed");
52 STATISTIC(NumPostRAHoisted,
53 "Number of machine instructions hoisted out of loops post regalloc");
56 class MachineLICM : public MachineFunctionPass {
59 const TargetMachine *TM;
60 const TargetInstrInfo *TII;
61 const TargetLowering *TLI;
62 const TargetRegisterInfo *TRI;
63 const MachineFrameInfo *MFI;
64 MachineRegisterInfo *MRI;
65 const InstrItineraryData *InstrItins;
67 // Various analyses that we use...
68 AliasAnalysis *AA; // Alias analysis info.
69 MachineLoopInfo *MLI; // Current MachineLoopInfo
70 MachineDominatorTree *DT; // Machine dominator tree for the cur loop
72 // State that is updated as we process loops
73 bool Changed; // True if a loop is changed.
74 bool FirstInLoop; // True if it's the first LICM in the loop.
75 MachineLoop *CurLoop; // The current loop we are working on.
76 MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
78 BitVector AllocatableSet;
80 // Track 'estimated' register pressure.
81 SmallSet<unsigned, 32> RegSeen;
82 SmallVector<unsigned, 8> RegPressure;
84 // Register pressure "limit" per register class. If the pressure
85 // is higher than the limit, then it's considered high.
86 SmallVector<unsigned, 8> RegLimit;
88 // Register pressure on path leading from loop preheader to current BB.
89 SmallVector<SmallVector<unsigned, 8>, 16> BackTrace;
91 // For each opcode, keep a list of potential CSE instructions.
92 DenseMap<unsigned, std::vector<const MachineInstr*> > CSEMap;
94 // If a MBB does not dominate loop exiting blocks then it may not safe
95 // to hoist loads from this block.
96 bool CurrentMBBDominatesLoopExitingBlocks;
97 bool NeedToCheckMBBDominance;
100 static char ID; // Pass identification, replacement for typeid
102 MachineFunctionPass(ID), PreRegAlloc(true) {
103 initializeMachineLICMPass(*PassRegistry::getPassRegistry());
106 explicit MachineLICM(bool PreRA) :
107 MachineFunctionPass(ID), PreRegAlloc(PreRA) {
108 initializeMachineLICMPass(*PassRegistry::getPassRegistry());
111 virtual bool runOnMachineFunction(MachineFunction &MF);
113 const char *getPassName() const { return "Machine Instruction LICM"; }
115 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
116 AU.addRequired<MachineLoopInfo>();
117 AU.addRequired<MachineDominatorTree>();
118 AU.addRequired<AliasAnalysis>();
119 AU.addPreserved<MachineLoopInfo>();
120 AU.addPreserved<MachineDominatorTree>();
121 MachineFunctionPass::getAnalysisUsage(AU);
124 virtual void releaseMemory() {
129 for (DenseMap<unsigned,std::vector<const MachineInstr*> >::iterator
130 CI = CSEMap.begin(), CE = CSEMap.end(); CI != CE; ++CI)
136 /// CandidateInfo - Keep track of information about hoisting candidates.
137 struct CandidateInfo {
141 CandidateInfo(MachineInstr *mi, unsigned def, int fi)
142 : MI(mi), Def(def), FI(fi) {}
145 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
146 /// invariants out to the preheader.
147 void HoistRegionPostRA();
149 /// HoistPostRA - When an instruction is found to only use loop invariant
150 /// operands that is safe to hoist, this instruction is called to do the
152 void HoistPostRA(MachineInstr *MI, unsigned Def);
154 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
155 /// gather register def and frame object update information.
156 void ProcessMI(MachineInstr *MI, unsigned *PhysRegDefs,
157 SmallSet<int, 32> &StoredFIs,
158 SmallVector<CandidateInfo, 32> &Candidates);
160 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the
162 void AddToLiveIns(unsigned Reg);
164 /// IsLICMCandidate - Returns true if the instruction may be a suitable
165 /// candidate for LICM. e.g. If the instruction is a call, then it's
166 /// obviously not safe to hoist it.
167 bool IsLICMCandidate(MachineInstr &I);
169 /// IsLoopInvariantInst - Returns true if the instruction is loop
170 /// invariant. I.e., all virtual register operands are defined outside of
171 /// the loop, physical registers aren't accessed (explicitly or implicitly),
172 /// and the instruction is hoistable.
174 bool IsLoopInvariantInst(MachineInstr &I);
176 /// HasAnyPHIUse - Return true if the specified register is used by any
178 bool HasAnyPHIUse(unsigned Reg) const;
180 /// HasHighOperandLatency - Compute operand latency between a def of 'Reg'
181 /// and an use in the current loop, return true if the target considered
183 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
186 bool IsCheapInstruction(MachineInstr &MI) const;
188 /// CanCauseHighRegPressure - Visit BBs from header to current BB,
189 /// check if hoisting an instruction of the given cost matrix can cause high
190 /// register pressure.
191 bool CanCauseHighRegPressure(DenseMap<unsigned, int> &Cost);
193 /// UpdateBackTraceRegPressure - Traverse the back trace from header to
194 /// the current block and update their register pressures to reflect the
195 /// effect of hoisting MI from the current block to the preheader.
196 void UpdateBackTraceRegPressure(const MachineInstr *MI);
198 /// IsProfitableToHoist - Return true if it is potentially profitable to
199 /// hoist the given loop invariant.
200 bool IsProfitableToHoist(MachineInstr &MI);
202 /// IsGuaranteedToExecute - Check if this mbb is guaranteed to execute.
203 /// If not then a load from this mbb may not be safe to hoist.
204 bool IsGuaranteedToExecute(MachineBasicBlock *BB);
206 /// HoistRegion - Walk the specified region of the CFG (defined by all
207 /// blocks dominated by the specified block, and that are in the current
208 /// loop) in depth first order w.r.t the DominatorTree. This allows us to
209 /// visit definitions before uses, allowing us to hoist a loop body in one
210 /// pass without iteration.
212 void HoistRegion(MachineDomTreeNode *N, bool IsHeader = false);
214 /// getRegisterClassIDAndCost - For a given MI, register, and the operand
215 /// index, return the ID and cost of its representative register class by
217 void getRegisterClassIDAndCost(const MachineInstr *MI,
218 unsigned Reg, unsigned OpIdx,
219 unsigned &RCId, unsigned &RCCost) const;
221 /// InitRegPressure - Find all virtual register references that are liveout
222 /// of the preheader to initialize the starting "register pressure". Note
223 /// this does not count live through (livein but not used) registers.
224 void InitRegPressure(MachineBasicBlock *BB);
226 /// UpdateRegPressure - Update estimate of register pressure after the
227 /// specified instruction.
228 void UpdateRegPressure(const MachineInstr *MI);
230 /// ExtractHoistableLoad - Unfold a load from the given machineinstr if
231 /// the load itself could be hoisted. Return the unfolded and hoistable
232 /// load, or null if the load couldn't be unfolded or if it wouldn't
234 MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
236 /// LookForDuplicate - Find an instruction amount PrevMIs that is a
237 /// duplicate of MI. Return this instruction if it's found.
238 const MachineInstr *LookForDuplicate(const MachineInstr *MI,
239 std::vector<const MachineInstr*> &PrevMIs);
241 /// EliminateCSE - Given a LICM'ed instruction, look for an instruction on
242 /// the preheader that compute the same value. If it's found, do a RAU on
243 /// with the definition of the existing instruction rather than hoisting
244 /// the instruction to the preheader.
245 bool EliminateCSE(MachineInstr *MI,
246 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI);
248 /// Hoist - When an instruction is found to only use loop invariant operands
249 /// that is safe to hoist, this instruction is called to do the dirty work.
250 /// It returns true if the instruction is hoisted.
251 bool Hoist(MachineInstr *MI, MachineBasicBlock *Preheader);
253 /// InitCSEMap - Initialize the CSE map with instructions that are in the
254 /// current loop preheader that may become duplicates of instructions that
255 /// are hoisted out of the loop.
256 void InitCSEMap(MachineBasicBlock *BB);
258 /// getCurPreheader - Get the preheader for the current loop, splitting
259 /// a critical edge if needed.
260 MachineBasicBlock *getCurPreheader();
262 } // end anonymous namespace
264 char MachineLICM::ID = 0;
265 INITIALIZE_PASS_BEGIN(MachineLICM, "machinelicm",
266 "Machine Loop Invariant Code Motion", false, false)
267 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
268 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
269 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
270 INITIALIZE_PASS_END(MachineLICM, "machinelicm",
271 "Machine Loop Invariant Code Motion", false, false)
273 FunctionPass *llvm::createMachineLICMPass(bool PreRegAlloc) {
274 return new MachineLICM(PreRegAlloc);
277 /// LoopIsOuterMostWithPredecessor - Test if the given loop is the outer-most
278 /// loop that has a unique predecessor.
279 static bool LoopIsOuterMostWithPredecessor(MachineLoop *CurLoop) {
280 // Check whether this loop even has a unique predecessor.
281 if (!CurLoop->getLoopPredecessor())
283 // Ok, now check to see if any of its outer loops do.
284 for (MachineLoop *L = CurLoop->getParentLoop(); L; L = L->getParentLoop())
285 if (L->getLoopPredecessor())
287 // None of them did, so this is the outermost with a unique predecessor.
291 bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
293 DEBUG(dbgs() << "******** Pre-regalloc Machine LICM: ");
295 DEBUG(dbgs() << "******** Post-regalloc Machine LICM: ");
296 DEBUG(dbgs() << MF.getFunction()->getName() << " ********\n");
298 Changed = FirstInLoop = false;
299 TM = &MF.getTarget();
300 TII = TM->getInstrInfo();
301 TLI = TM->getTargetLowering();
302 TRI = TM->getRegisterInfo();
303 MFI = MF.getFrameInfo();
304 MRI = &MF.getRegInfo();
305 InstrItins = TM->getInstrItineraryData();
306 AllocatableSet = TRI->getAllocatableSet(MF);
307 // Stay conservative.
308 CurrentMBBDominatesLoopExitingBlocks = false;
309 NeedToCheckMBBDominance = true;
312 // Estimate register pressure during pre-regalloc pass.
313 unsigned NumRC = TRI->getNumRegClasses();
314 RegPressure.resize(NumRC);
315 std::fill(RegPressure.begin(), RegPressure.end(), 0);
316 RegLimit.resize(NumRC);
317 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
318 E = TRI->regclass_end(); I != E; ++I)
319 RegLimit[(*I)->getID()] = TRI->getRegPressureLimit(*I, MF);
322 // Get our Loop information...
323 MLI = &getAnalysis<MachineLoopInfo>();
324 DT = &getAnalysis<MachineDominatorTree>();
325 AA = &getAnalysis<AliasAnalysis>();
327 SmallVector<MachineLoop *, 8> Worklist(MLI->begin(), MLI->end());
328 while (!Worklist.empty()) {
329 CurLoop = Worklist.pop_back_val();
332 // If this is done before regalloc, only visit outer-most preheader-sporting
334 if (PreRegAlloc && !LoopIsOuterMostWithPredecessor(CurLoop)) {
335 Worklist.append(CurLoop->begin(), CurLoop->end());
342 // CSEMap is initialized for loop header when the first instruction is
344 MachineDomTreeNode *N = DT->getNode(CurLoop->getHeader());
346 HoistRegion(N, true);
354 /// InstructionStoresToFI - Return true if instruction stores to the
356 static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
357 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
358 oe = MI->memoperands_end(); o != oe; ++o) {
359 if (!(*o)->isStore() || !(*o)->getValue())
361 if (const FixedStackPseudoSourceValue *Value =
362 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
363 if (Value->getFrameIndex() == FI)
370 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
371 /// gather register def and frame object update information.
372 void MachineLICM::ProcessMI(MachineInstr *MI,
373 unsigned *PhysRegDefs,
374 SmallSet<int, 32> &StoredFIs,
375 SmallVector<CandidateInfo, 32> &Candidates) {
376 bool RuledOut = false;
377 bool HasNonInvariantUse = false;
379 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
380 const MachineOperand &MO = MI->getOperand(i);
382 // Remember if the instruction stores to the frame index.
383 int FI = MO.getIndex();
384 if (!StoredFIs.count(FI) &&
385 MFI->isSpillSlotObjectIndex(FI) &&
386 InstructionStoresToFI(MI, FI))
387 StoredFIs.insert(FI);
388 HasNonInvariantUse = true;
394 unsigned Reg = MO.getReg();
397 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
398 "Not expecting virtual register!");
401 if (Reg && PhysRegDefs[Reg])
402 // If it's using a non-loop-invariant register, then it's obviously not
404 HasNonInvariantUse = true;
408 if (MO.isImplicit()) {
410 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
413 // Non-dead implicit def? This cannot be hoisted.
415 // No need to check if a dead implicit def is also defined by
416 // another instruction.
420 // FIXME: For now, avoid instructions with multiple defs, unless
421 // it's a dead implicit def.
427 // If we have already seen another instruction that defines the same
428 // register, then this is not safe.
429 if (++PhysRegDefs[Reg] > 1)
430 // MI defined register is seen defined by another instruction in
431 // the loop, it cannot be a LICM candidate.
433 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
434 if (++PhysRegDefs[*AS] > 1)
438 // Only consider reloads for now and remats which do not have register
439 // operands. FIXME: Consider unfold load folding instructions.
440 if (Def && !RuledOut) {
442 if ((!HasNonInvariantUse && IsLICMCandidate(*MI)) ||
443 (TII->isLoadFromStackSlot(MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
444 Candidates.push_back(CandidateInfo(MI, Def, FI));
448 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
449 /// invariants out to the preheader.
450 void MachineLICM::HoistRegionPostRA() {
451 unsigned NumRegs = TRI->getNumRegs();
452 unsigned *PhysRegDefs = new unsigned[NumRegs];
453 std::fill(PhysRegDefs, PhysRegDefs + NumRegs, 0);
455 SmallVector<CandidateInfo, 32> Candidates;
456 SmallSet<int, 32> StoredFIs;
458 // Walk the entire region, count number of defs for each register, and
459 // collect potential LICM candidates.
460 const std::vector<MachineBasicBlock*> Blocks = CurLoop->getBlocks();
461 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
462 MachineBasicBlock *BB = Blocks[i];
463 // Conservatively treat live-in's as an external def.
464 // FIXME: That means a reload that're reused in successor block(s) will not
466 for (MachineBasicBlock::livein_iterator I = BB->livein_begin(),
467 E = BB->livein_end(); I != E; ++I) {
470 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
474 NeedToCheckMBBDominance = true;
475 for (MachineBasicBlock::iterator
476 MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
477 MachineInstr *MI = &*MII;
478 ProcessMI(MI, PhysRegDefs, StoredFIs, Candidates);
482 // Now evaluate whether the potential candidates qualify.
483 // 1. Check if the candidate defined register is defined by another
484 // instruction in the loop.
485 // 2. If the candidate is a load from stack slot (always true for now),
486 // check if the slot is stored anywhere in the loop.
487 for (unsigned i = 0, e = Candidates.size(); i != e; ++i) {
488 if (Candidates[i].FI != INT_MIN &&
489 StoredFIs.count(Candidates[i].FI))
492 if (PhysRegDefs[Candidates[i].Def] == 1) {
494 MachineInstr *MI = Candidates[i].MI;
495 for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
496 const MachineOperand &MO = MI->getOperand(j);
497 if (!MO.isReg() || MO.isDef() || !MO.getReg())
499 if (PhysRegDefs[MO.getReg()]) {
500 // If it's using a non-loop-invariant register, then it's obviously
501 // not safe to hoist.
507 HoistPostRA(MI, Candidates[i].Def);
511 delete[] PhysRegDefs;
514 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the current
515 /// loop, and make sure it is not killed by any instructions in the loop.
516 void MachineLICM::AddToLiveIns(unsigned Reg) {
517 const std::vector<MachineBasicBlock*> Blocks = CurLoop->getBlocks();
518 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
519 MachineBasicBlock *BB = Blocks[i];
520 if (!BB->isLiveIn(Reg))
522 for (MachineBasicBlock::iterator
523 MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
524 MachineInstr *MI = &*MII;
525 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
526 MachineOperand &MO = MI->getOperand(i);
527 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
528 if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
535 /// HoistPostRA - When an instruction is found to only use loop invariant
536 /// operands that is safe to hoist, this instruction is called to do the
538 void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
539 MachineBasicBlock *Preheader = getCurPreheader();
540 if (!Preheader) return;
542 // Now move the instructions to the predecessor, inserting it before any
543 // terminator instructions.
545 dbgs() << "Hoisting " << *MI;
546 if (Preheader->getBasicBlock())
547 dbgs() << " to MachineBasicBlock "
548 << Preheader->getName();
549 if (MI->getParent()->getBasicBlock())
550 dbgs() << " from MachineBasicBlock "
551 << MI->getParent()->getName();
555 // Splice the instruction to the preheader.
556 MachineBasicBlock *MBB = MI->getParent();
557 Preheader->splice(Preheader->getFirstTerminator(), MBB, MI);
559 // Add register to livein list to all the BBs in the current loop since a
560 // loop invariant must be kept live throughout the whole loop. This is
561 // important to ensure later passes do not scavenge the def register.
568 // IsGuaranteedToExecute - Check if this mbb is guaranteed to execute.
569 // If not then a load from this mbb may not be safe to hoist.
570 bool MachineLICM::IsGuaranteedToExecute(MachineBasicBlock *BB) {
571 // Do not check if we already have checked it once.
572 if (NeedToCheckMBBDominance == false)
573 return CurrentMBBDominatesLoopExitingBlocks;
575 NeedToCheckMBBDominance = false;
577 if (BB != CurLoop->getHeader()) {
578 // Check loop exiting blocks.
579 SmallVector<MachineBasicBlock*, 8> CurrentLoopExitingBlocks;
580 CurLoop->getExitingBlocks(CurrentLoopExitingBlocks);
581 for (unsigned i = 0, e = CurrentLoopExitingBlocks.size(); i != e; ++i)
582 if (!DT->dominates(BB, CurrentLoopExitingBlocks[i])) {
583 CurrentMBBDominatesLoopExitingBlocks = false;
584 return CurrentMBBDominatesLoopExitingBlocks;
588 CurrentMBBDominatesLoopExitingBlocks = true;
589 return CurrentMBBDominatesLoopExitingBlocks;
592 /// HoistRegion - Walk the specified region of the CFG (defined by all blocks
593 /// dominated by the specified block, and that are in the current loop) in depth
594 /// first order w.r.t the DominatorTree. This allows us to visit definitions
595 /// before uses, allowing us to hoist a loop body in one pass without iteration.
597 void MachineLICM::HoistRegion(MachineDomTreeNode *N, bool IsHeader) {
598 assert(N != 0 && "Null dominator tree node?");
599 MachineBasicBlock *BB = N->getBlock();
601 // If this subregion is not in the top level loop at all, exit.
602 if (!CurLoop->contains(BB)) return;
604 MachineBasicBlock *Preheader = getCurPreheader();
609 // Compute registers which are livein into the loop headers.
612 InitRegPressure(Preheader);
615 // Remember livein register pressure.
616 BackTrace.push_back(RegPressure);
618 NeedToCheckMBBDominance = true;
619 for (MachineBasicBlock::iterator
620 MII = BB->begin(), E = BB->end(); MII != E; ) {
621 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
622 MachineInstr *MI = &*MII;
623 if (!Hoist(MI, Preheader))
624 UpdateRegPressure(MI);
628 // Don't hoist things out of a large switch statement. This often causes
629 // code to be hoisted that wasn't going to be executed, and increases
630 // register pressure in a situation where it's likely to matter.
631 if (BB->succ_size() < 25) {
632 const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
633 for (unsigned I = 0, E = Children.size(); I != E; ++I)
634 HoistRegion(Children[I]);
637 BackTrace.pop_back();
640 static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI) {
641 return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg());
644 /// getRegisterClassIDAndCost - For a given MI, register, and the operand
645 /// index, return the ID and cost of its representative register class.
647 MachineLICM::getRegisterClassIDAndCost(const MachineInstr *MI,
648 unsigned Reg, unsigned OpIdx,
649 unsigned &RCId, unsigned &RCCost) const {
650 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
651 EVT VT = *RC->vt_begin();
652 if (VT == MVT::untyped) {
656 RCId = TLI->getRepRegClassFor(VT)->getID();
657 RCCost = TLI->getRepRegClassCostFor(VT);
661 /// InitRegPressure - Find all virtual register references that are liveout of
662 /// the preheader to initialize the starting "register pressure". Note this
663 /// does not count live through (livein but not used) registers.
664 void MachineLICM::InitRegPressure(MachineBasicBlock *BB) {
665 std::fill(RegPressure.begin(), RegPressure.end(), 0);
667 // If the preheader has only a single predecessor and it ends with a
668 // fallthrough or an unconditional branch, then scan its predecessor for live
669 // defs as well. This happens whenever the preheader is created by splitting
670 // the critical edge from the loop predecessor to the loop header.
671 if (BB->pred_size() == 1) {
672 MachineBasicBlock *TBB = 0, *FBB = 0;
673 SmallVector<MachineOperand, 4> Cond;
674 if (!TII->AnalyzeBranch(*BB, TBB, FBB, Cond, false) && Cond.empty())
675 InitRegPressure(*BB->pred_begin());
678 for (MachineBasicBlock::iterator MII = BB->begin(), E = BB->end();
680 MachineInstr *MI = &*MII;
681 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
682 const MachineOperand &MO = MI->getOperand(i);
683 if (!MO.isReg() || MO.isImplicit())
685 unsigned Reg = MO.getReg();
686 if (!TargetRegisterInfo::isVirtualRegister(Reg))
689 bool isNew = RegSeen.insert(Reg);
690 unsigned RCId, RCCost;
691 getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
693 RegPressure[RCId] += RCCost;
695 bool isKill = isOperandKill(MO, MRI);
696 if (isNew && !isKill)
697 // Haven't seen this, it must be a livein.
698 RegPressure[RCId] += RCCost;
699 else if (!isNew && isKill)
700 RegPressure[RCId] -= RCCost;
706 /// UpdateRegPressure - Update estimate of register pressure after the
707 /// specified instruction.
708 void MachineLICM::UpdateRegPressure(const MachineInstr *MI) {
709 if (MI->isImplicitDef())
712 SmallVector<unsigned, 4> Defs;
713 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
714 const MachineOperand &MO = MI->getOperand(i);
715 if (!MO.isReg() || MO.isImplicit())
717 unsigned Reg = MO.getReg();
718 if (!TargetRegisterInfo::isVirtualRegister(Reg))
721 bool isNew = RegSeen.insert(Reg);
724 else if (!isNew && isOperandKill(MO, MRI)) {
725 unsigned RCId, RCCost;
726 getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
727 if (RCCost > RegPressure[RCId])
728 RegPressure[RCId] = 0;
730 RegPressure[RCId] -= RCCost;
735 while (!Defs.empty()) {
736 unsigned Reg = Defs.pop_back_val();
737 unsigned RCId, RCCost;
738 getRegisterClassIDAndCost(MI, Reg, Idx, RCId, RCCost);
739 RegPressure[RCId] += RCCost;
744 /// IsLICMCandidate - Returns true if the instruction may be a suitable
745 /// candidate for LICM. e.g. If the instruction is a call, then it's obviously
746 /// not safe to hoist it.
747 bool MachineLICM::IsLICMCandidate(MachineInstr &I) {
748 // Check if it's safe to move the instruction.
749 bool DontMoveAcrossStore = true;
750 if (!I.isSafeToMove(TII, AA, DontMoveAcrossStore))
753 // If it is load then check if it is guaranteed to execute by making sure that
754 // it dominates all exiting blocks. If it doesn't, then there is a path out of
755 // the loop which does not execute this load, so we can't hoist it.
756 // Stores and side effects are already checked by isSafeToMove.
757 if (I.getDesc().mayLoad() && !IsGuaranteedToExecute(I.getParent()))
763 /// IsLoopInvariantInst - Returns true if the instruction is loop
764 /// invariant. I.e., all virtual register operands are defined outside of the
765 /// loop, physical registers aren't accessed explicitly, and there are no side
766 /// effects that aren't captured by the operands or other flags.
768 bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
769 if (!IsLICMCandidate(I))
772 // The instruction is loop invariant if all of its operands are.
773 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
774 const MachineOperand &MO = I.getOperand(i);
779 unsigned Reg = MO.getReg();
780 if (Reg == 0) continue;
782 // Don't hoist an instruction that uses or defines a physical register.
783 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
785 // If the physreg has no defs anywhere, it's just an ambient register
786 // and we can freely move its uses. Alternatively, if it's allocatable,
787 // it could get allocated to something with a def during allocation.
788 if (!MRI->def_empty(Reg))
790 if (AllocatableSet.test(Reg))
792 // Check for a def among the register's aliases too.
793 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
794 unsigned AliasReg = *Alias;
795 if (!MRI->def_empty(AliasReg))
797 if (AllocatableSet.test(AliasReg))
800 // Otherwise it's safe to move.
802 } else if (!MO.isDead()) {
803 // A def that isn't dead. We can't move it.
805 } else if (CurLoop->getHeader()->isLiveIn(Reg)) {
806 // If the reg is live into the loop, we can't hoist an instruction
807 // which would clobber it.
815 assert(MRI->getVRegDef(Reg) &&
816 "Machine instr not mapped for this vreg?!");
818 // If the loop contains the definition of an operand, then the instruction
819 // isn't loop invariant.
820 if (CurLoop->contains(MRI->getVRegDef(Reg)))
824 // If we got this far, the instruction is loop invariant!
829 /// HasAnyPHIUse - Return true if the specified register is used by any
831 bool MachineLICM::HasAnyPHIUse(unsigned Reg) const {
832 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
833 UE = MRI->use_end(); UI != UE; ++UI) {
834 MachineInstr *UseMI = &*UI;
837 // Look pass copies as well.
838 if (UseMI->isCopy()) {
839 unsigned Def = UseMI->getOperand(0).getReg();
840 if (TargetRegisterInfo::isVirtualRegister(Def) &&
848 /// HasHighOperandLatency - Compute operand latency between a def of 'Reg'
849 /// and an use in the current loop, return true if the target considered
851 bool MachineLICM::HasHighOperandLatency(MachineInstr &MI,
852 unsigned DefIdx, unsigned Reg) const {
853 if (!InstrItins || InstrItins->isEmpty() || MRI->use_nodbg_empty(Reg))
856 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
857 E = MRI->use_nodbg_end(); I != E; ++I) {
858 MachineInstr *UseMI = &*I;
859 if (UseMI->isCopyLike())
861 if (!CurLoop->contains(UseMI->getParent()))
863 for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
864 const MachineOperand &MO = UseMI->getOperand(i);
865 if (!MO.isReg() || !MO.isUse())
867 unsigned MOReg = MO.getReg();
871 if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, UseMI, i))
875 // Only look at the first in loop use.
882 /// IsCheapInstruction - Return true if the instruction is marked "cheap" or
883 /// the operand latency between its def and a use is one or less.
884 bool MachineLICM::IsCheapInstruction(MachineInstr &MI) const {
885 if (MI.getDesc().isAsCheapAsAMove() || MI.isCopyLike())
887 if (!InstrItins || InstrItins->isEmpty())
890 bool isCheap = false;
891 unsigned NumDefs = MI.getDesc().getNumDefs();
892 for (unsigned i = 0, e = MI.getNumOperands(); NumDefs && i != e; ++i) {
893 MachineOperand &DefMO = MI.getOperand(i);
894 if (!DefMO.isReg() || !DefMO.isDef())
897 unsigned Reg = DefMO.getReg();
898 if (TargetRegisterInfo::isPhysicalRegister(Reg))
901 if (!TII->hasLowDefLatency(InstrItins, &MI, i))
909 /// CanCauseHighRegPressure - Visit BBs from header to current BB, check
910 /// if hoisting an instruction of the given cost matrix can cause high
911 /// register pressure.
912 bool MachineLICM::CanCauseHighRegPressure(DenseMap<unsigned, int> &Cost) {
913 for (DenseMap<unsigned, int>::iterator CI = Cost.begin(), CE = Cost.end();
918 unsigned RCId = CI->first;
919 for (unsigned i = BackTrace.size(); i != 0; --i) {
920 SmallVector<unsigned, 8> &RP = BackTrace[i-1];
921 if (RP[RCId] + CI->second >= RegLimit[RCId])
929 /// UpdateBackTraceRegPressure - Traverse the back trace from header to the
930 /// current block and update their register pressures to reflect the effect
931 /// of hoisting MI from the current block to the preheader.
932 void MachineLICM::UpdateBackTraceRegPressure(const MachineInstr *MI) {
933 if (MI->isImplicitDef())
936 // First compute the 'cost' of the instruction, i.e. its contribution
937 // to register pressure.
938 DenseMap<unsigned, int> Cost;
939 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
940 const MachineOperand &MO = MI->getOperand(i);
941 if (!MO.isReg() || MO.isImplicit())
943 unsigned Reg = MO.getReg();
944 if (!TargetRegisterInfo::isVirtualRegister(Reg))
947 unsigned RCId, RCCost;
948 getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
950 DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
951 if (CI != Cost.end())
952 CI->second += RCCost;
954 Cost.insert(std::make_pair(RCId, RCCost));
955 } else if (isOperandKill(MO, MRI)) {
956 DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
957 if (CI != Cost.end())
958 CI->second -= RCCost;
960 Cost.insert(std::make_pair(RCId, -RCCost));
964 // Update register pressure of blocks from loop header to current block.
965 for (unsigned i = 0, e = BackTrace.size(); i != e; ++i) {
966 SmallVector<unsigned, 8> &RP = BackTrace[i];
967 for (DenseMap<unsigned, int>::iterator CI = Cost.begin(), CE = Cost.end();
969 unsigned RCId = CI->first;
970 RP[RCId] += CI->second;
975 /// IsProfitableToHoist - Return true if it is potentially profitable to hoist
976 /// the given loop invariant.
977 bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
978 if (MI.isImplicitDef())
981 // If the instruction is cheap, only hoist if it is re-materilizable. LICM
982 // will increase register pressure. It's probably not worth it if the
983 // instruction is cheap.
984 // Also hoist loads from constant memory, e.g. load from stubs, GOT. Hoisting
985 // these tend to help performance in low register pressure situation. The
986 // trade off is it may cause spill in high pressure situation. It will end up
987 // adding a store in the loop preheader. But the reload is no more expensive.
988 // The side benefit is these loads are frequently CSE'ed.
989 if (IsCheapInstruction(MI)) {
990 if (!TII->isTriviallyReMaterializable(&MI, AA))
993 // Estimate register pressure to determine whether to LICM the instruction.
994 // In low register pressure situation, we can be more aggressive about
995 // hoisting. Also, favors hoisting long latency instructions even in
996 // moderately high pressure situation.
997 // FIXME: If there are long latency loop-invariant instructions inside the
998 // loop at this point, why didn't the optimizer's LICM hoist them?
999 DenseMap<unsigned, int> Cost;
1000 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
1001 const MachineOperand &MO = MI.getOperand(i);
1002 if (!MO.isReg() || MO.isImplicit())
1004 unsigned Reg = MO.getReg();
1005 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1008 unsigned RCId, RCCost;
1009 getRegisterClassIDAndCost(&MI, Reg, i, RCId, RCCost);
1011 if (HasHighOperandLatency(MI, i, Reg)) {
1016 DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
1017 if (CI != Cost.end())
1018 CI->second += RCCost;
1020 Cost.insert(std::make_pair(RCId, RCCost));
1021 } else if (isOperandKill(MO, MRI)) {
1022 // Is a virtual register use is a kill, hoisting it out of the loop
1023 // may actually reduce register pressure or be register pressure
1025 DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
1026 if (CI != Cost.end())
1027 CI->second -= RCCost;
1029 Cost.insert(std::make_pair(RCId, -RCCost));
1033 // Visit BBs from header to current BB, if hoisting this doesn't cause
1034 // high register pressure, then it's safe to proceed.
1035 if (!CanCauseHighRegPressure(Cost)) {
1040 // High register pressure situation, only hoist if the instruction is going to
1042 if (!TII->isTriviallyReMaterializable(&MI, AA) &&
1043 !MI.isInvariantLoad(AA))
1047 // If result(s) of this instruction is used by PHIs outside of the loop, then
1048 // don't hoist it if the instruction because it will introduce an extra copy.
1049 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1050 const MachineOperand &MO = MI.getOperand(i);
1051 if (!MO.isReg() || !MO.isDef())
1053 if (HasAnyPHIUse(MO.getReg()))
1060 MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
1061 // Don't unfold simple loads.
1062 if (MI->getDesc().canFoldAsLoad())
1065 // If not, we may be able to unfold a load and hoist that.
1066 // First test whether the instruction is loading from an amenable
1068 if (!MI->isInvariantLoad(AA))
1071 // Next determine the register class for a temporary register.
1072 unsigned LoadRegIndex;
1074 TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(),
1075 /*UnfoldLoad=*/true,
1076 /*UnfoldStore=*/false,
1078 if (NewOpc == 0) return 0;
1079 const MCInstrDesc &MID = TII->get(NewOpc);
1080 if (MID.getNumDefs() != 1) return 0;
1081 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI);
1082 // Ok, we're unfolding. Create a temporary register and do the unfold.
1083 unsigned Reg = MRI->createVirtualRegister(RC);
1085 MachineFunction &MF = *MI->getParent()->getParent();
1086 SmallVector<MachineInstr *, 2> NewMIs;
1088 TII->unfoldMemoryOperand(MF, MI, Reg,
1089 /*UnfoldLoad=*/true, /*UnfoldStore=*/false,
1093 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
1095 assert(NewMIs.size() == 2 &&
1096 "Unfolded a load into multiple instructions!");
1097 MachineBasicBlock *MBB = MI->getParent();
1098 MBB->insert(MI, NewMIs[0]);
1099 MBB->insert(MI, NewMIs[1]);
1100 // If unfolding produced a load that wasn't loop-invariant or profitable to
1101 // hoist, discard the new instructions and bail.
1102 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
1103 NewMIs[0]->eraseFromParent();
1104 NewMIs[1]->eraseFromParent();
1108 // Update register pressure for the unfolded instruction.
1109 UpdateRegPressure(NewMIs[1]);
1111 // Otherwise we successfully unfolded a load that we can hoist.
1112 MI->eraseFromParent();
1116 void MachineLICM::InitCSEMap(MachineBasicBlock *BB) {
1117 for (MachineBasicBlock::iterator I = BB->begin(),E = BB->end(); I != E; ++I) {
1118 const MachineInstr *MI = &*I;
1119 unsigned Opcode = MI->getOpcode();
1120 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
1121 CI = CSEMap.find(Opcode);
1122 if (CI != CSEMap.end())
1123 CI->second.push_back(MI);
1125 std::vector<const MachineInstr*> CSEMIs;
1126 CSEMIs.push_back(MI);
1127 CSEMap.insert(std::make_pair(Opcode, CSEMIs));
1133 MachineLICM::LookForDuplicate(const MachineInstr *MI,
1134 std::vector<const MachineInstr*> &PrevMIs) {
1135 for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) {
1136 const MachineInstr *PrevMI = PrevMIs[i];
1137 if (TII->produceSameValue(MI, PrevMI, (PreRegAlloc ? MRI : 0)))
1143 bool MachineLICM::EliminateCSE(MachineInstr *MI,
1144 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI) {
1145 // Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
1146 // the undef property onto uses.
1147 if (CI == CSEMap.end() || MI->isImplicitDef())
1150 if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
1151 DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
1153 // Replace virtual registers defined by MI by their counterparts defined
1155 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1156 const MachineOperand &MO = MI->getOperand(i);
1158 // Physical registers may not differ here.
1159 assert((!MO.isReg() || MO.getReg() == 0 ||
1160 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
1161 MO.getReg() == Dup->getOperand(i).getReg()) &&
1162 "Instructions with different phys regs are not identical!");
1164 if (MO.isReg() && MO.isDef() &&
1165 !TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
1166 MRI->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg());
1167 MRI->clearKillFlags(Dup->getOperand(i).getReg());
1170 MI->eraseFromParent();
1177 /// Hoist - When an instruction is found to use only loop invariant operands
1178 /// that are safe to hoist, this instruction is called to do the dirty work.
1180 bool MachineLICM::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
1181 // First check whether we should hoist this instruction.
1182 if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
1183 // If not, try unfolding a hoistable load.
1184 MI = ExtractHoistableLoad(MI);
1185 if (!MI) return false;
1188 // Now move the instructions to the predecessor, inserting it before any
1189 // terminator instructions.
1191 dbgs() << "Hoisting " << *MI;
1192 if (Preheader->getBasicBlock())
1193 dbgs() << " to MachineBasicBlock "
1194 << Preheader->getName();
1195 if (MI->getParent()->getBasicBlock())
1196 dbgs() << " from MachineBasicBlock "
1197 << MI->getParent()->getName();
1201 // If this is the first instruction being hoisted to the preheader,
1202 // initialize the CSE map with potential common expressions.
1204 InitCSEMap(Preheader);
1205 FirstInLoop = false;
1208 // Look for opportunity to CSE the hoisted instruction.
1209 unsigned Opcode = MI->getOpcode();
1210 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
1211 CI = CSEMap.find(Opcode);
1212 if (!EliminateCSE(MI, CI)) {
1213 // Otherwise, splice the instruction to the preheader.
1214 Preheader->splice(Preheader->getFirstTerminator(),MI->getParent(),MI);
1216 // Update register pressure for BBs from header to this block.
1217 UpdateBackTraceRegPressure(MI);
1219 // Clear the kill flags of any register this instruction defines,
1220 // since they may need to be live throughout the entire loop
1221 // rather than just live for part of it.
1222 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1223 MachineOperand &MO = MI->getOperand(i);
1224 if (MO.isReg() && MO.isDef() && !MO.isDead())
1225 MRI->clearKillFlags(MO.getReg());
1228 // Add to the CSE map.
1229 if (CI != CSEMap.end())
1230 CI->second.push_back(MI);
1232 std::vector<const MachineInstr*> CSEMIs;
1233 CSEMIs.push_back(MI);
1234 CSEMap.insert(std::make_pair(Opcode, CSEMIs));
1244 MachineBasicBlock *MachineLICM::getCurPreheader() {
1245 // Determine the block to which to hoist instructions. If we can't find a
1246 // suitable loop predecessor, we can't do any hoisting.
1248 // If we've tried to get a preheader and failed, don't try again.
1249 if (CurPreheader == reinterpret_cast<MachineBasicBlock *>(-1))
1252 if (!CurPreheader) {
1253 CurPreheader = CurLoop->getLoopPreheader();
1254 if (!CurPreheader) {
1255 MachineBasicBlock *Pred = CurLoop->getLoopPredecessor();
1257 CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
1261 CurPreheader = Pred->SplitCriticalEdge(CurLoop->getHeader(), this);
1262 if (!CurPreheader) {
1263 CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
1268 return CurPreheader;