1 //===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs loop invariant code motion on machine instructions. We
11 // attempt to remove as much code from the body of a loop as possible.
13 // This pass does not attempt to throttle itself to limit register pressure.
14 // The register allocation phases are expected to perform rematerialization
15 // to recover when register pressure is high.
17 // This pass is not intended to be a replacement or a complete alternative
18 // for the LLVM-IR-level LICM pass. It is only designed to hoist simple
19 // constructs that are not exposed before lowering and instruction selection.
21 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "machine-licm"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/PseudoSourceValue.h"
31 #include "llvm/MC/MCInstrItineraries.h"
32 #include "llvm/Target/TargetLowering.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Analysis/AliasAnalysis.h"
37 #include "llvm/ADT/DenseMap.h"
38 #include "llvm/ADT/SmallSet.h"
39 #include "llvm/ADT/Statistic.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/raw_ostream.h"
45 "Number of machine instructions hoisted out of loops");
47 "Number of instructions hoisted in low reg pressure situation");
48 STATISTIC(NumHighLatency,
49 "Number of high latency instructions hoisted");
51 "Number of hoisted machine instructions CSEed");
52 STATISTIC(NumPostRAHoisted,
53 "Number of machine instructions hoisted out of loops post regalloc");
56 class MachineLICM : public MachineFunctionPass {
59 const TargetMachine *TM;
60 const TargetInstrInfo *TII;
61 const TargetLowering *TLI;
62 const TargetRegisterInfo *TRI;
63 const MachineFrameInfo *MFI;
64 MachineRegisterInfo *MRI;
65 const InstrItineraryData *InstrItins;
67 // Various analyses that we use...
68 AliasAnalysis *AA; // Alias analysis info.
69 MachineLoopInfo *MLI; // Current MachineLoopInfo
70 MachineDominatorTree *DT; // Machine dominator tree for the cur loop
72 // State that is updated as we process loops
73 bool Changed; // True if a loop is changed.
74 bool FirstInLoop; // True if it's the first LICM in the loop.
75 MachineLoop *CurLoop; // The current loop we are working on.
76 MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
78 BitVector AllocatableSet;
80 // Track 'estimated' register pressure.
81 SmallSet<unsigned, 32> RegSeen;
82 SmallVector<unsigned, 8> RegPressure;
84 // Register pressure "limit" per register class. If the pressure
85 // is higher than the limit, then it's considered high.
86 SmallVector<unsigned, 8> RegLimit;
88 // Register pressure on path leading from loop preheader to current BB.
89 SmallVector<SmallVector<unsigned, 8>, 16> BackTrace;
91 // For each opcode, keep a list of potential CSE instructions.
92 DenseMap<unsigned, std::vector<const MachineInstr*> > CSEMap;
95 static char ID; // Pass identification, replacement for typeid
97 MachineFunctionPass(ID), PreRegAlloc(true) {
98 initializeMachineLICMPass(*PassRegistry::getPassRegistry());
101 explicit MachineLICM(bool PreRA) :
102 MachineFunctionPass(ID), PreRegAlloc(PreRA) {
103 initializeMachineLICMPass(*PassRegistry::getPassRegistry());
106 virtual bool runOnMachineFunction(MachineFunction &MF);
108 const char *getPassName() const { return "Machine Instruction LICM"; }
110 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
111 AU.addRequired<MachineLoopInfo>();
112 AU.addRequired<MachineDominatorTree>();
113 AU.addRequired<AliasAnalysis>();
114 AU.addPreserved<MachineLoopInfo>();
115 AU.addPreserved<MachineDominatorTree>();
116 MachineFunctionPass::getAnalysisUsage(AU);
119 virtual void releaseMemory() {
124 for (DenseMap<unsigned,std::vector<const MachineInstr*> >::iterator
125 CI = CSEMap.begin(), CE = CSEMap.end(); CI != CE; ++CI)
131 /// CandidateInfo - Keep track of information about hoisting candidates.
132 struct CandidateInfo {
136 CandidateInfo(MachineInstr *mi, unsigned def, int fi)
137 : MI(mi), Def(def), FI(fi) {}
140 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
141 /// invariants out to the preheader.
142 void HoistRegionPostRA();
144 /// HoistPostRA - When an instruction is found to only use loop invariant
145 /// operands that is safe to hoist, this instruction is called to do the
147 void HoistPostRA(MachineInstr *MI, unsigned Def);
149 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
150 /// gather register def and frame object update information.
151 void ProcessMI(MachineInstr *MI, unsigned *PhysRegDefs,
152 SmallSet<int, 32> &StoredFIs,
153 SmallVector<CandidateInfo, 32> &Candidates);
155 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the
157 void AddToLiveIns(unsigned Reg);
159 /// IsLICMCandidate - Returns true if the instruction may be a suitable
160 /// candidate for LICM. e.g. If the instruction is a call, then it's
161 /// obviously not safe to hoist it.
162 bool IsLICMCandidate(MachineInstr &I);
164 /// IsLoopInvariantInst - Returns true if the instruction is loop
165 /// invariant. I.e., all virtual register operands are defined outside of
166 /// the loop, physical registers aren't accessed (explicitly or implicitly),
167 /// and the instruction is hoistable.
169 bool IsLoopInvariantInst(MachineInstr &I);
171 /// HasAnyPHIUse - Return true if the specified register is used by any
173 bool HasAnyPHIUse(unsigned Reg) const;
175 /// HasHighOperandLatency - Compute operand latency between a def of 'Reg'
176 /// and an use in the current loop, return true if the target considered
178 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
181 bool IsCheapInstruction(MachineInstr &MI) const;
183 /// CanCauseHighRegPressure - Visit BBs from header to current BB,
184 /// check if hoisting an instruction of the given cost matrix can cause high
185 /// register pressure.
186 bool CanCauseHighRegPressure(DenseMap<unsigned, int> &Cost);
188 /// UpdateBackTraceRegPressure - Traverse the back trace from header to
189 /// the current block and update their register pressures to reflect the
190 /// effect of hoisting MI from the current block to the preheader.
191 void UpdateBackTraceRegPressure(const MachineInstr *MI);
193 /// IsProfitableToHoist - Return true if it is potentially profitable to
194 /// hoist the given loop invariant.
195 bool IsProfitableToHoist(MachineInstr &MI);
197 /// HoistRegion - Walk the specified region of the CFG (defined by all
198 /// blocks dominated by the specified block, and that are in the current
199 /// loop) in depth first order w.r.t the DominatorTree. This allows us to
200 /// visit definitions before uses, allowing us to hoist a loop body in one
201 /// pass without iteration.
203 void HoistRegion(MachineDomTreeNode *N, bool IsHeader = false);
205 /// getRegisterClassIDAndCost - For a given MI, register, and the operand
206 /// index, return the ID and cost of its representative register class by
208 void getRegisterClassIDAndCost(const MachineInstr *MI,
209 unsigned Reg, unsigned OpIdx,
210 unsigned &RCId, unsigned &RCCost) const;
212 /// InitRegPressure - Find all virtual register references that are liveout
213 /// of the preheader to initialize the starting "register pressure". Note
214 /// this does not count live through (livein but not used) registers.
215 void InitRegPressure(MachineBasicBlock *BB);
217 /// UpdateRegPressure - Update estimate of register pressure after the
218 /// specified instruction.
219 void UpdateRegPressure(const MachineInstr *MI);
221 /// ExtractHoistableLoad - Unfold a load from the given machineinstr if
222 /// the load itself could be hoisted. Return the unfolded and hoistable
223 /// load, or null if the load couldn't be unfolded or if it wouldn't
225 MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
227 /// LookForDuplicate - Find an instruction amount PrevMIs that is a
228 /// duplicate of MI. Return this instruction if it's found.
229 const MachineInstr *LookForDuplicate(const MachineInstr *MI,
230 std::vector<const MachineInstr*> &PrevMIs);
232 /// EliminateCSE - Given a LICM'ed instruction, look for an instruction on
233 /// the preheader that compute the same value. If it's found, do a RAU on
234 /// with the definition of the existing instruction rather than hoisting
235 /// the instruction to the preheader.
236 bool EliminateCSE(MachineInstr *MI,
237 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI);
239 /// Hoist - When an instruction is found to only use loop invariant operands
240 /// that is safe to hoist, this instruction is called to do the dirty work.
241 /// It returns true if the instruction is hoisted.
242 bool Hoist(MachineInstr *MI, MachineBasicBlock *Preheader);
244 /// InitCSEMap - Initialize the CSE map with instructions that are in the
245 /// current loop preheader that may become duplicates of instructions that
246 /// are hoisted out of the loop.
247 void InitCSEMap(MachineBasicBlock *BB);
249 /// getCurPreheader - Get the preheader for the current loop, splitting
250 /// a critical edge if needed.
251 MachineBasicBlock *getCurPreheader();
253 } // end anonymous namespace
255 char MachineLICM::ID = 0;
256 INITIALIZE_PASS_BEGIN(MachineLICM, "machinelicm",
257 "Machine Loop Invariant Code Motion", false, false)
258 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
259 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
260 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
261 INITIALIZE_PASS_END(MachineLICM, "machinelicm",
262 "Machine Loop Invariant Code Motion", false, false)
264 FunctionPass *llvm::createMachineLICMPass(bool PreRegAlloc) {
265 return new MachineLICM(PreRegAlloc);
268 /// LoopIsOuterMostWithPredecessor - Test if the given loop is the outer-most
269 /// loop that has a unique predecessor.
270 static bool LoopIsOuterMostWithPredecessor(MachineLoop *CurLoop) {
271 // Check whether this loop even has a unique predecessor.
272 if (!CurLoop->getLoopPredecessor())
274 // Ok, now check to see if any of its outer loops do.
275 for (MachineLoop *L = CurLoop->getParentLoop(); L; L = L->getParentLoop())
276 if (L->getLoopPredecessor())
278 // None of them did, so this is the outermost with a unique predecessor.
282 bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
284 DEBUG(dbgs() << "******** Pre-regalloc Machine LICM: ");
286 DEBUG(dbgs() << "******** Post-regalloc Machine LICM: ");
287 DEBUG(dbgs() << MF.getFunction()->getName() << " ********\n");
289 Changed = FirstInLoop = false;
290 TM = &MF.getTarget();
291 TII = TM->getInstrInfo();
292 TLI = TM->getTargetLowering();
293 TRI = TM->getRegisterInfo();
294 MFI = MF.getFrameInfo();
295 MRI = &MF.getRegInfo();
296 InstrItins = TM->getInstrItineraryData();
297 AllocatableSet = TRI->getAllocatableSet(MF);
300 // Estimate register pressure during pre-regalloc pass.
301 unsigned NumRC = TRI->getNumRegClasses();
302 RegPressure.resize(NumRC);
303 std::fill(RegPressure.begin(), RegPressure.end(), 0);
304 RegLimit.resize(NumRC);
305 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
306 E = TRI->regclass_end(); I != E; ++I)
307 RegLimit[(*I)->getID()] = TRI->getRegPressureLimit(*I, MF);
310 // Get our Loop information...
311 MLI = &getAnalysis<MachineLoopInfo>();
312 DT = &getAnalysis<MachineDominatorTree>();
313 AA = &getAnalysis<AliasAnalysis>();
315 SmallVector<MachineLoop *, 8> Worklist(MLI->begin(), MLI->end());
316 while (!Worklist.empty()) {
317 CurLoop = Worklist.pop_back_val();
320 // If this is done before regalloc, only visit outer-most preheader-sporting
322 if (PreRegAlloc && !LoopIsOuterMostWithPredecessor(CurLoop)) {
323 Worklist.append(CurLoop->begin(), CurLoop->end());
330 // CSEMap is initialized for loop header when the first instruction is
332 MachineDomTreeNode *N = DT->getNode(CurLoop->getHeader());
334 HoistRegion(N, true);
342 /// InstructionStoresToFI - Return true if instruction stores to the
344 static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
345 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
346 oe = MI->memoperands_end(); o != oe; ++o) {
347 if (!(*o)->isStore() || !(*o)->getValue())
349 if (const FixedStackPseudoSourceValue *Value =
350 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
351 if (Value->getFrameIndex() == FI)
358 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
359 /// gather register def and frame object update information.
360 void MachineLICM::ProcessMI(MachineInstr *MI,
361 unsigned *PhysRegDefs,
362 SmallSet<int, 32> &StoredFIs,
363 SmallVector<CandidateInfo, 32> &Candidates) {
364 bool RuledOut = false;
365 bool HasNonInvariantUse = false;
367 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
368 const MachineOperand &MO = MI->getOperand(i);
370 // Remember if the instruction stores to the frame index.
371 int FI = MO.getIndex();
372 if (!StoredFIs.count(FI) &&
373 MFI->isSpillSlotObjectIndex(FI) &&
374 InstructionStoresToFI(MI, FI))
375 StoredFIs.insert(FI);
376 HasNonInvariantUse = true;
382 unsigned Reg = MO.getReg();
385 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
386 "Not expecting virtual register!");
389 if (Reg && PhysRegDefs[Reg])
390 // If it's using a non-loop-invariant register, then it's obviously not
392 HasNonInvariantUse = true;
396 if (MO.isImplicit()) {
398 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
401 // Non-dead implicit def? This cannot be hoisted.
403 // No need to check if a dead implicit def is also defined by
404 // another instruction.
408 // FIXME: For now, avoid instructions with multiple defs, unless
409 // it's a dead implicit def.
415 // If we have already seen another instruction that defines the same
416 // register, then this is not safe.
417 if (++PhysRegDefs[Reg] > 1)
418 // MI defined register is seen defined by another instruction in
419 // the loop, it cannot be a LICM candidate.
421 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
422 if (++PhysRegDefs[*AS] > 1)
426 // Only consider reloads for now and remats which do not have register
427 // operands. FIXME: Consider unfold load folding instructions.
428 if (Def && !RuledOut) {
430 if ((!HasNonInvariantUse && IsLICMCandidate(*MI)) ||
431 (TII->isLoadFromStackSlot(MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
432 Candidates.push_back(CandidateInfo(MI, Def, FI));
436 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
437 /// invariants out to the preheader.
438 void MachineLICM::HoistRegionPostRA() {
439 unsigned NumRegs = TRI->getNumRegs();
440 unsigned *PhysRegDefs = new unsigned[NumRegs];
441 std::fill(PhysRegDefs, PhysRegDefs + NumRegs, 0);
443 SmallVector<CandidateInfo, 32> Candidates;
444 SmallSet<int, 32> StoredFIs;
446 // Walk the entire region, count number of defs for each register, and
447 // collect potential LICM candidates.
448 const std::vector<MachineBasicBlock*> Blocks = CurLoop->getBlocks();
449 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
450 MachineBasicBlock *BB = Blocks[i];
451 // Conservatively treat live-in's as an external def.
452 // FIXME: That means a reload that're reused in successor block(s) will not
454 for (MachineBasicBlock::livein_iterator I = BB->livein_begin(),
455 E = BB->livein_end(); I != E; ++I) {
458 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
462 for (MachineBasicBlock::iterator
463 MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
464 MachineInstr *MI = &*MII;
465 ProcessMI(MI, PhysRegDefs, StoredFIs, Candidates);
469 // Now evaluate whether the potential candidates qualify.
470 // 1. Check if the candidate defined register is defined by another
471 // instruction in the loop.
472 // 2. If the candidate is a load from stack slot (always true for now),
473 // check if the slot is stored anywhere in the loop.
474 for (unsigned i = 0, e = Candidates.size(); i != e; ++i) {
475 if (Candidates[i].FI != INT_MIN &&
476 StoredFIs.count(Candidates[i].FI))
479 if (PhysRegDefs[Candidates[i].Def] == 1) {
481 MachineInstr *MI = Candidates[i].MI;
482 for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
483 const MachineOperand &MO = MI->getOperand(j);
484 if (!MO.isReg() || MO.isDef() || !MO.getReg())
486 if (PhysRegDefs[MO.getReg()]) {
487 // If it's using a non-loop-invariant register, then it's obviously
488 // not safe to hoist.
494 HoistPostRA(MI, Candidates[i].Def);
498 delete[] PhysRegDefs;
501 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the current
502 /// loop, and make sure it is not killed by any instructions in the loop.
503 void MachineLICM::AddToLiveIns(unsigned Reg) {
504 const std::vector<MachineBasicBlock*> Blocks = CurLoop->getBlocks();
505 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
506 MachineBasicBlock *BB = Blocks[i];
507 if (!BB->isLiveIn(Reg))
509 for (MachineBasicBlock::iterator
510 MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
511 MachineInstr *MI = &*MII;
512 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
513 MachineOperand &MO = MI->getOperand(i);
514 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
515 if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
522 /// HoistPostRA - When an instruction is found to only use loop invariant
523 /// operands that is safe to hoist, this instruction is called to do the
525 void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
526 MachineBasicBlock *Preheader = getCurPreheader();
527 if (!Preheader) return;
529 // Now move the instructions to the predecessor, inserting it before any
530 // terminator instructions.
532 dbgs() << "Hoisting " << *MI;
533 if (Preheader->getBasicBlock())
534 dbgs() << " to MachineBasicBlock "
535 << Preheader->getName();
536 if (MI->getParent()->getBasicBlock())
537 dbgs() << " from MachineBasicBlock "
538 << MI->getParent()->getName();
542 // Splice the instruction to the preheader.
543 MachineBasicBlock *MBB = MI->getParent();
544 Preheader->splice(Preheader->getFirstTerminator(), MBB, MI);
546 // Add register to livein list to all the BBs in the current loop since a
547 // loop invariant must be kept live throughout the whole loop. This is
548 // important to ensure later passes do not scavenge the def register.
555 /// HoistRegion - Walk the specified region of the CFG (defined by all blocks
556 /// dominated by the specified block, and that are in the current loop) in depth
557 /// first order w.r.t the DominatorTree. This allows us to visit definitions
558 /// before uses, allowing us to hoist a loop body in one pass without iteration.
560 void MachineLICM::HoistRegion(MachineDomTreeNode *N, bool IsHeader) {
561 assert(N != 0 && "Null dominator tree node?");
562 MachineBasicBlock *BB = N->getBlock();
564 // If this subregion is not in the top level loop at all, exit.
565 if (!CurLoop->contains(BB)) return;
567 MachineBasicBlock *Preheader = getCurPreheader();
572 // Compute registers which are livein into the loop headers.
575 InitRegPressure(Preheader);
578 // Remember livein register pressure.
579 BackTrace.push_back(RegPressure);
581 for (MachineBasicBlock::iterator
582 MII = BB->begin(), E = BB->end(); MII != E; ) {
583 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
584 MachineInstr *MI = &*MII;
585 if (!Hoist(MI, Preheader))
586 UpdateRegPressure(MI);
590 // Don't hoist things out of a large switch statement. This often causes
591 // code to be hoisted that wasn't going to be executed, and increases
592 // register pressure in a situation where it's likely to matter.
593 if (BB->succ_size() < 25) {
594 const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
595 for (unsigned I = 0, E = Children.size(); I != E; ++I)
596 HoistRegion(Children[I]);
599 BackTrace.pop_back();
602 static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI) {
603 return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg());
606 /// getRegisterClassIDAndCost - For a given MI, register, and the operand
607 /// index, return the ID and cost of its representative register class.
609 MachineLICM::getRegisterClassIDAndCost(const MachineInstr *MI,
610 unsigned Reg, unsigned OpIdx,
611 unsigned &RCId, unsigned &RCCost) const {
612 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
613 EVT VT = *RC->vt_begin();
614 if (VT == MVT::untyped) {
618 RCId = TLI->getRepRegClassFor(VT)->getID();
619 RCCost = TLI->getRepRegClassCostFor(VT);
623 /// InitRegPressure - Find all virtual register references that are liveout of
624 /// the preheader to initialize the starting "register pressure". Note this
625 /// does not count live through (livein but not used) registers.
626 void MachineLICM::InitRegPressure(MachineBasicBlock *BB) {
627 std::fill(RegPressure.begin(), RegPressure.end(), 0);
629 // If the preheader has only a single predecessor and it ends with a
630 // fallthrough or an unconditional branch, then scan its predecessor for live
631 // defs as well. This happens whenever the preheader is created by splitting
632 // the critical edge from the loop predecessor to the loop header.
633 if (BB->pred_size() == 1) {
634 MachineBasicBlock *TBB = 0, *FBB = 0;
635 SmallVector<MachineOperand, 4> Cond;
636 if (!TII->AnalyzeBranch(*BB, TBB, FBB, Cond, false) && Cond.empty())
637 InitRegPressure(*BB->pred_begin());
640 for (MachineBasicBlock::iterator MII = BB->begin(), E = BB->end();
642 MachineInstr *MI = &*MII;
643 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
644 const MachineOperand &MO = MI->getOperand(i);
645 if (!MO.isReg() || MO.isImplicit())
647 unsigned Reg = MO.getReg();
648 if (!TargetRegisterInfo::isVirtualRegister(Reg))
651 bool isNew = RegSeen.insert(Reg);
652 unsigned RCId, RCCost;
653 getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
655 RegPressure[RCId] += RCCost;
657 bool isKill = isOperandKill(MO, MRI);
658 if (isNew && !isKill)
659 // Haven't seen this, it must be a livein.
660 RegPressure[RCId] += RCCost;
661 else if (!isNew && isKill)
662 RegPressure[RCId] -= RCCost;
668 /// UpdateRegPressure - Update estimate of register pressure after the
669 /// specified instruction.
670 void MachineLICM::UpdateRegPressure(const MachineInstr *MI) {
671 if (MI->isImplicitDef())
674 SmallVector<unsigned, 4> Defs;
675 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
676 const MachineOperand &MO = MI->getOperand(i);
677 if (!MO.isReg() || MO.isImplicit())
679 unsigned Reg = MO.getReg();
680 if (!TargetRegisterInfo::isVirtualRegister(Reg))
683 bool isNew = RegSeen.insert(Reg);
686 else if (!isNew && isOperandKill(MO, MRI)) {
687 unsigned RCId, RCCost;
688 getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
689 if (RCCost > RegPressure[RCId])
690 RegPressure[RCId] = 0;
692 RegPressure[RCId] -= RCCost;
697 while (!Defs.empty()) {
698 unsigned Reg = Defs.pop_back_val();
699 unsigned RCId, RCCost;
700 getRegisterClassIDAndCost(MI, Reg, Idx, RCId, RCCost);
701 RegPressure[RCId] += RCCost;
706 /// IsLICMCandidate - Returns true if the instruction may be a suitable
707 /// candidate for LICM. e.g. If the instruction is a call, then it's obviously
708 /// not safe to hoist it.
709 bool MachineLICM::IsLICMCandidate(MachineInstr &I) {
710 // Check if it's safe to move the instruction.
711 bool DontMoveAcrossStore = true;
712 if (!I.isSafeToMove(TII, AA, DontMoveAcrossStore))
718 /// IsLoopInvariantInst - Returns true if the instruction is loop
719 /// invariant. I.e., all virtual register operands are defined outside of the
720 /// loop, physical registers aren't accessed explicitly, and there are no side
721 /// effects that aren't captured by the operands or other flags.
723 bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
724 if (!IsLICMCandidate(I))
727 // The instruction is loop invariant if all of its operands are.
728 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
729 const MachineOperand &MO = I.getOperand(i);
734 unsigned Reg = MO.getReg();
735 if (Reg == 0) continue;
737 // Don't hoist an instruction that uses or defines a physical register.
738 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
740 // If the physreg has no defs anywhere, it's just an ambient register
741 // and we can freely move its uses. Alternatively, if it's allocatable,
742 // it could get allocated to something with a def during allocation.
743 if (!MRI->def_empty(Reg))
745 if (AllocatableSet.test(Reg))
747 // Check for a def among the register's aliases too.
748 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
749 unsigned AliasReg = *Alias;
750 if (!MRI->def_empty(AliasReg))
752 if (AllocatableSet.test(AliasReg))
755 // Otherwise it's safe to move.
757 } else if (!MO.isDead()) {
758 // A def that isn't dead. We can't move it.
760 } else if (CurLoop->getHeader()->isLiveIn(Reg)) {
761 // If the reg is live into the loop, we can't hoist an instruction
762 // which would clobber it.
770 assert(MRI->getVRegDef(Reg) &&
771 "Machine instr not mapped for this vreg?!");
773 // If the loop contains the definition of an operand, then the instruction
774 // isn't loop invariant.
775 if (CurLoop->contains(MRI->getVRegDef(Reg)))
779 // If we got this far, the instruction is loop invariant!
784 /// HasAnyPHIUse - Return true if the specified register is used by any
786 bool MachineLICM::HasAnyPHIUse(unsigned Reg) const {
787 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
788 UE = MRI->use_end(); UI != UE; ++UI) {
789 MachineInstr *UseMI = &*UI;
792 // Look pass copies as well.
793 if (UseMI->isCopy()) {
794 unsigned Def = UseMI->getOperand(0).getReg();
795 if (TargetRegisterInfo::isVirtualRegister(Def) &&
803 /// HasHighOperandLatency - Compute operand latency between a def of 'Reg'
804 /// and an use in the current loop, return true if the target considered
806 bool MachineLICM::HasHighOperandLatency(MachineInstr &MI,
807 unsigned DefIdx, unsigned Reg) const {
808 if (!InstrItins || InstrItins->isEmpty() || MRI->use_nodbg_empty(Reg))
811 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
812 E = MRI->use_nodbg_end(); I != E; ++I) {
813 MachineInstr *UseMI = &*I;
814 if (UseMI->isCopyLike())
816 if (!CurLoop->contains(UseMI->getParent()))
818 for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
819 const MachineOperand &MO = UseMI->getOperand(i);
820 if (!MO.isReg() || !MO.isUse())
822 unsigned MOReg = MO.getReg();
826 if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, UseMI, i))
830 // Only look at the first in loop use.
837 /// IsCheapInstruction - Return true if the instruction is marked "cheap" or
838 /// the operand latency between its def and a use is one or less.
839 bool MachineLICM::IsCheapInstruction(MachineInstr &MI) const {
840 if (MI.getDesc().isAsCheapAsAMove() || MI.isCopyLike())
842 if (!InstrItins || InstrItins->isEmpty())
845 bool isCheap = false;
846 unsigned NumDefs = MI.getDesc().getNumDefs();
847 for (unsigned i = 0, e = MI.getNumOperands(); NumDefs && i != e; ++i) {
848 MachineOperand &DefMO = MI.getOperand(i);
849 if (!DefMO.isReg() || !DefMO.isDef())
852 unsigned Reg = DefMO.getReg();
853 if (TargetRegisterInfo::isPhysicalRegister(Reg))
856 if (!TII->hasLowDefLatency(InstrItins, &MI, i))
864 /// CanCauseHighRegPressure - Visit BBs from header to current BB, check
865 /// if hoisting an instruction of the given cost matrix can cause high
866 /// register pressure.
867 bool MachineLICM::CanCauseHighRegPressure(DenseMap<unsigned, int> &Cost) {
868 for (DenseMap<unsigned, int>::iterator CI = Cost.begin(), CE = Cost.end();
873 unsigned RCId = CI->first;
874 for (unsigned i = BackTrace.size(); i != 0; --i) {
875 SmallVector<unsigned, 8> &RP = BackTrace[i-1];
876 if (RP[RCId] + CI->second >= RegLimit[RCId])
884 /// UpdateBackTraceRegPressure - Traverse the back trace from header to the
885 /// current block and update their register pressures to reflect the effect
886 /// of hoisting MI from the current block to the preheader.
887 void MachineLICM::UpdateBackTraceRegPressure(const MachineInstr *MI) {
888 if (MI->isImplicitDef())
891 // First compute the 'cost' of the instruction, i.e. its contribution
892 // to register pressure.
893 DenseMap<unsigned, int> Cost;
894 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
895 const MachineOperand &MO = MI->getOperand(i);
896 if (!MO.isReg() || MO.isImplicit())
898 unsigned Reg = MO.getReg();
899 if (!TargetRegisterInfo::isVirtualRegister(Reg))
902 unsigned RCId, RCCost;
903 getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
905 DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
906 if (CI != Cost.end())
907 CI->second += RCCost;
909 Cost.insert(std::make_pair(RCId, RCCost));
910 } else if (isOperandKill(MO, MRI)) {
911 DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
912 if (CI != Cost.end())
913 CI->second -= RCCost;
915 Cost.insert(std::make_pair(RCId, -RCCost));
919 // Update register pressure of blocks from loop header to current block.
920 for (unsigned i = 0, e = BackTrace.size(); i != e; ++i) {
921 SmallVector<unsigned, 8> &RP = BackTrace[i];
922 for (DenseMap<unsigned, int>::iterator CI = Cost.begin(), CE = Cost.end();
924 unsigned RCId = CI->first;
925 RP[RCId] += CI->second;
930 /// IsProfitableToHoist - Return true if it is potentially profitable to hoist
931 /// the given loop invariant.
932 bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
933 if (MI.isImplicitDef())
936 // If the instruction is cheap, only hoist if it is re-materilizable. LICM
937 // will increase register pressure. It's probably not worth it if the
938 // instruction is cheap.
939 // Also hoist loads from constant memory, e.g. load from stubs, GOT. Hoisting
940 // these tend to help performance in low register pressure situation. The
941 // trade off is it may cause spill in high pressure situation. It will end up
942 // adding a store in the loop preheader. But the reload is no more expensive.
943 // The side benefit is these loads are frequently CSE'ed.
944 if (IsCheapInstruction(MI)) {
945 if (!TII->isTriviallyReMaterializable(&MI, AA))
948 // Estimate register pressure to determine whether to LICM the instruction.
949 // In low register pressure situation, we can be more aggressive about
950 // hoisting. Also, favors hoisting long latency instructions even in
951 // moderately high pressure situation.
952 // FIXME: If there are long latency loop-invariant instructions inside the
953 // loop at this point, why didn't the optimizer's LICM hoist them?
954 DenseMap<unsigned, int> Cost;
955 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
956 const MachineOperand &MO = MI.getOperand(i);
957 if (!MO.isReg() || MO.isImplicit())
959 unsigned Reg = MO.getReg();
960 if (!TargetRegisterInfo::isVirtualRegister(Reg))
963 unsigned RCId, RCCost;
964 getRegisterClassIDAndCost(&MI, Reg, i, RCId, RCCost);
966 if (HasHighOperandLatency(MI, i, Reg)) {
971 DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
972 if (CI != Cost.end())
973 CI->second += RCCost;
975 Cost.insert(std::make_pair(RCId, RCCost));
976 } else if (isOperandKill(MO, MRI)) {
977 // Is a virtual register use is a kill, hoisting it out of the loop
978 // may actually reduce register pressure or be register pressure
980 DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
981 if (CI != Cost.end())
982 CI->second -= RCCost;
984 Cost.insert(std::make_pair(RCId, -RCCost));
988 // Visit BBs from header to current BB, if hoisting this doesn't cause
989 // high register pressure, then it's safe to proceed.
990 if (!CanCauseHighRegPressure(Cost)) {
995 // High register pressure situation, only hoist if the instruction is going to
997 if (!TII->isTriviallyReMaterializable(&MI, AA) &&
998 !MI.isInvariantLoad(AA))
1002 // If result(s) of this instruction is used by PHIs outside of the loop, then
1003 // don't hoist it if the instruction because it will introduce an extra copy.
1004 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1005 const MachineOperand &MO = MI.getOperand(i);
1006 if (!MO.isReg() || !MO.isDef())
1008 if (HasAnyPHIUse(MO.getReg()))
1015 MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
1016 // Don't unfold simple loads.
1017 if (MI->getDesc().canFoldAsLoad())
1020 // If not, we may be able to unfold a load and hoist that.
1021 // First test whether the instruction is loading from an amenable
1023 if (!MI->isInvariantLoad(AA))
1026 // Next determine the register class for a temporary register.
1027 unsigned LoadRegIndex;
1029 TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(),
1030 /*UnfoldLoad=*/true,
1031 /*UnfoldStore=*/false,
1033 if (NewOpc == 0) return 0;
1034 const MCInstrDesc &MID = TII->get(NewOpc);
1035 if (MID.getNumDefs() != 1) return 0;
1036 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI);
1037 // Ok, we're unfolding. Create a temporary register and do the unfold.
1038 unsigned Reg = MRI->createVirtualRegister(RC);
1040 MachineFunction &MF = *MI->getParent()->getParent();
1041 SmallVector<MachineInstr *, 2> NewMIs;
1043 TII->unfoldMemoryOperand(MF, MI, Reg,
1044 /*UnfoldLoad=*/true, /*UnfoldStore=*/false,
1048 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
1050 assert(NewMIs.size() == 2 &&
1051 "Unfolded a load into multiple instructions!");
1052 MachineBasicBlock *MBB = MI->getParent();
1053 MBB->insert(MI, NewMIs[0]);
1054 MBB->insert(MI, NewMIs[1]);
1055 // If unfolding produced a load that wasn't loop-invariant or profitable to
1056 // hoist, discard the new instructions and bail.
1057 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
1058 NewMIs[0]->eraseFromParent();
1059 NewMIs[1]->eraseFromParent();
1063 // Update register pressure for the unfolded instruction.
1064 UpdateRegPressure(NewMIs[1]);
1066 // Otherwise we successfully unfolded a load that we can hoist.
1067 MI->eraseFromParent();
1071 void MachineLICM::InitCSEMap(MachineBasicBlock *BB) {
1072 for (MachineBasicBlock::iterator I = BB->begin(),E = BB->end(); I != E; ++I) {
1073 const MachineInstr *MI = &*I;
1074 unsigned Opcode = MI->getOpcode();
1075 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
1076 CI = CSEMap.find(Opcode);
1077 if (CI != CSEMap.end())
1078 CI->second.push_back(MI);
1080 std::vector<const MachineInstr*> CSEMIs;
1081 CSEMIs.push_back(MI);
1082 CSEMap.insert(std::make_pair(Opcode, CSEMIs));
1088 MachineLICM::LookForDuplicate(const MachineInstr *MI,
1089 std::vector<const MachineInstr*> &PrevMIs) {
1090 for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) {
1091 const MachineInstr *PrevMI = PrevMIs[i];
1092 if (TII->produceSameValue(MI, PrevMI, (PreRegAlloc ? MRI : 0)))
1098 bool MachineLICM::EliminateCSE(MachineInstr *MI,
1099 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI) {
1100 // Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
1101 // the undef property onto uses.
1102 if (CI == CSEMap.end() || MI->isImplicitDef())
1105 if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
1106 DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
1108 // Replace virtual registers defined by MI by their counterparts defined
1110 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1111 const MachineOperand &MO = MI->getOperand(i);
1113 // Physical registers may not differ here.
1114 assert((!MO.isReg() || MO.getReg() == 0 ||
1115 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
1116 MO.getReg() == Dup->getOperand(i).getReg()) &&
1117 "Instructions with different phys regs are not identical!");
1119 if (MO.isReg() && MO.isDef() &&
1120 !TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
1121 MRI->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg());
1122 MRI->clearKillFlags(Dup->getOperand(i).getReg());
1125 MI->eraseFromParent();
1132 /// Hoist - When an instruction is found to use only loop invariant operands
1133 /// that are safe to hoist, this instruction is called to do the dirty work.
1135 bool MachineLICM::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
1136 // First check whether we should hoist this instruction.
1137 if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
1138 // If not, try unfolding a hoistable load.
1139 MI = ExtractHoistableLoad(MI);
1140 if (!MI) return false;
1143 // Now move the instructions to the predecessor, inserting it before any
1144 // terminator instructions.
1146 dbgs() << "Hoisting " << *MI;
1147 if (Preheader->getBasicBlock())
1148 dbgs() << " to MachineBasicBlock "
1149 << Preheader->getName();
1150 if (MI->getParent()->getBasicBlock())
1151 dbgs() << " from MachineBasicBlock "
1152 << MI->getParent()->getName();
1156 // If this is the first instruction being hoisted to the preheader,
1157 // initialize the CSE map with potential common expressions.
1159 InitCSEMap(Preheader);
1160 FirstInLoop = false;
1163 // Look for opportunity to CSE the hoisted instruction.
1164 unsigned Opcode = MI->getOpcode();
1165 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
1166 CI = CSEMap.find(Opcode);
1167 if (!EliminateCSE(MI, CI)) {
1168 // Otherwise, splice the instruction to the preheader.
1169 Preheader->splice(Preheader->getFirstTerminator(),MI->getParent(),MI);
1171 // Update register pressure for BBs from header to this block.
1172 UpdateBackTraceRegPressure(MI);
1174 // Clear the kill flags of any register this instruction defines,
1175 // since they may need to be live throughout the entire loop
1176 // rather than just live for part of it.
1177 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1178 MachineOperand &MO = MI->getOperand(i);
1179 if (MO.isReg() && MO.isDef() && !MO.isDead())
1180 MRI->clearKillFlags(MO.getReg());
1183 // Add to the CSE map.
1184 if (CI != CSEMap.end())
1185 CI->second.push_back(MI);
1187 std::vector<const MachineInstr*> CSEMIs;
1188 CSEMIs.push_back(MI);
1189 CSEMap.insert(std::make_pair(Opcode, CSEMIs));
1199 MachineBasicBlock *MachineLICM::getCurPreheader() {
1200 // Determine the block to which to hoist instructions. If we can't find a
1201 // suitable loop predecessor, we can't do any hoisting.
1203 // If we've tried to get a preheader and failed, don't try again.
1204 if (CurPreheader == reinterpret_cast<MachineBasicBlock *>(-1))
1207 if (!CurPreheader) {
1208 CurPreheader = CurLoop->getLoopPreheader();
1209 if (!CurPreheader) {
1210 MachineBasicBlock *Pred = CurLoop->getLoopPredecessor();
1212 CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
1216 CurPreheader = Pred->SplitCriticalEdge(CurLoop->getHeader(), this);
1217 if (!CurPreheader) {
1218 CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
1223 return CurPreheader;