1 //===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs loop invariant code motion on machine instructions. We
11 // attempt to remove as much code from the body of a loop as possible.
13 // This pass does not attempt to throttle itself to limit register pressure.
14 // The register allocation phases are expected to perform rematerialization
15 // to recover when register pressure is high.
17 // This pass is not intended to be a replacement or a complete alternative
18 // for the LLVM-IR-level LICM pass. It is only designed to hoist simple
19 // constructs that are not exposed before lowering and instruction selection.
21 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "machine-licm"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/PseudoSourceValue.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Analysis/AliasAnalysis.h"
35 #include "llvm/ADT/DenseMap.h"
36 #include "llvm/ADT/SmallSet.h"
37 #include "llvm/ADT/Statistic.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops");
44 STATISTIC(NumCSEed, "Number of hoisted machine instructions CSEed");
45 STATISTIC(NumPostRAHoisted,
46 "Number of machine instructions hoisted out of loops post regalloc");
49 class MachineLICM : public MachineFunctionPass {
52 const TargetMachine *TM;
53 const TargetInstrInfo *TII;
54 const TargetRegisterInfo *TRI;
55 const MachineFrameInfo *MFI;
56 MachineRegisterInfo *RegInfo;
58 // Various analyses that we use...
59 AliasAnalysis *AA; // Alias analysis info.
60 MachineLoopInfo *MLI; // Current MachineLoopInfo
61 MachineDominatorTree *DT; // Machine dominator tree for the cur loop
63 // State that is updated as we process loops
64 bool Changed; // True if a loop is changed.
65 MachineLoop *CurLoop; // The current loop we are working on.
66 MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
68 BitVector AllocatableSet;
70 // For each opcode, keep a list of potentail CSE instructions.
71 DenseMap<unsigned, std::vector<const MachineInstr*> > CSEMap;
74 static char ID; // Pass identification, replacement for typeid
76 MachineFunctionPass(&ID), PreRegAlloc(true) {}
78 explicit MachineLICM(bool PreRA) :
79 MachineFunctionPass(&ID), PreRegAlloc(PreRA) {}
81 virtual bool runOnMachineFunction(MachineFunction &MF);
83 const char *getPassName() const { return "Machine Instruction LICM"; }
85 // FIXME: Loop preheaders?
86 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
88 AU.addRequired<MachineLoopInfo>();
89 AU.addRequired<MachineDominatorTree>();
90 AU.addRequired<AliasAnalysis>();
91 AU.addPreserved<MachineLoopInfo>();
92 AU.addPreserved<MachineDominatorTree>();
93 MachineFunctionPass::getAnalysisUsage(AU);
96 virtual void releaseMemory() {
101 /// CandidateInfo - Keep track of information about hoisting candidates.
102 struct CandidateInfo {
106 CandidateInfo(MachineInstr *mi, int fi, unsigned def)
107 : MI(mi), FI(fi), Def(def) {}
110 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
111 /// invariants out to the preheader.
112 void HoistRegionPostRA(MachineDomTreeNode *N);
114 /// HoistPostRA - When an instruction is found to only use loop invariant
115 /// operands that is safe to hoist, this instruction is called to do the
117 void HoistPostRA(MachineInstr *MI, unsigned Def);
119 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
120 /// gather register def and frame object update information.
121 void ProcessMI(MachineInstr *MI, unsigned *PhysRegDefs,
122 SmallSet<int, 32> &StoredFIs,
123 SmallVector<CandidateInfo, 32> &Candidates);
125 /// AddToLiveIns - Add 'Reg' to the livein sets of BBs in the backedge path
126 /// from MBB to LoopHeader (inclusive).
127 void AddToLiveIns(unsigned Reg,
128 MachineBasicBlock *MBB, MachineBasicBlock *LoopHeader);
130 /// IsLoopInvariantInst - Returns true if the instruction is loop
131 /// invariant. I.e., all virtual register operands are defined outside of
132 /// the loop, physical registers aren't accessed (explicitly or implicitly),
133 /// and the instruction is hoistable.
135 bool IsLoopInvariantInst(MachineInstr &I);
137 /// IsProfitableToHoist - Return true if it is potentially profitable to
138 /// hoist the given loop invariant.
139 bool IsProfitableToHoist(MachineInstr &MI);
141 /// HoistRegion - Walk the specified region of the CFG (defined by all
142 /// blocks dominated by the specified block, and that are in the current
143 /// loop) in depth first order w.r.t the DominatorTree. This allows us to
144 /// visit definitions before uses, allowing us to hoist a loop body in one
145 /// pass without iteration.
147 void HoistRegion(MachineDomTreeNode *N);
149 /// isLoadFromConstantMemory - Return true if the given instruction is a
150 /// load from constant memory.
151 bool isLoadFromConstantMemory(MachineInstr *MI);
153 /// ExtractHoistableLoad - Unfold a load from the given machineinstr if
154 /// the load itself could be hoisted. Return the unfolded and hoistable
155 /// load, or null if the load couldn't be unfolded or if it wouldn't
157 MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
159 /// LookForDuplicate - Find an instruction amount PrevMIs that is a
160 /// duplicate of MI. Return this instruction if it's found.
161 const MachineInstr *LookForDuplicate(const MachineInstr *MI,
162 std::vector<const MachineInstr*> &PrevMIs);
164 /// EliminateCSE - Given a LICM'ed instruction, look for an instruction on
165 /// the preheader that compute the same value. If it's found, do a RAU on
166 /// with the definition of the existing instruction rather than hoisting
167 /// the instruction to the preheader.
168 bool EliminateCSE(MachineInstr *MI,
169 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI);
171 /// Hoist - When an instruction is found to only use loop invariant operands
172 /// that is safe to hoist, this instruction is called to do the dirty work.
174 void Hoist(MachineInstr *MI);
176 /// InitCSEMap - Initialize the CSE map with instructions that are in the
177 /// current loop preheader that may become duplicates of instructions that
178 /// are hoisted out of the loop.
179 void InitCSEMap(MachineBasicBlock *BB);
181 } // end anonymous namespace
183 char MachineLICM::ID = 0;
184 static RegisterPass<MachineLICM>
185 X("machinelicm", "Machine Loop Invariant Code Motion");
187 FunctionPass *llvm::createMachineLICMPass(bool PreRegAlloc) {
188 return new MachineLICM(PreRegAlloc);
191 /// LoopIsOuterMostWithPreheader - Test if the given loop is the outer-most
192 /// loop that has a preheader.
193 static bool LoopIsOuterMostWithPreheader(MachineLoop *CurLoop) {
194 for (MachineLoop *L = CurLoop->getParentLoop(); L; L = L->getParentLoop())
195 if (L->getLoopPreheader())
200 bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
202 DEBUG(dbgs() << "******** Pre-regalloc Machine LICM ********\n");
204 DEBUG(dbgs() << "******** Post-regalloc Machine LICM ********\n");
207 TM = &MF.getTarget();
208 TII = TM->getInstrInfo();
209 TRI = TM->getRegisterInfo();
210 MFI = MF.getFrameInfo();
211 RegInfo = &MF.getRegInfo();
212 AllocatableSet = TRI->getAllocatableSet(MF);
214 // Get our Loop information...
215 MLI = &getAnalysis<MachineLoopInfo>();
216 DT = &getAnalysis<MachineDominatorTree>();
217 AA = &getAnalysis<AliasAnalysis>();
219 for (MachineLoopInfo::iterator I = MLI->begin(), E = MLI->end(); I != E; ++I){
222 // If this is done before regalloc, only visit outer-most preheader-sporting
224 if (PreRegAlloc && !LoopIsOuterMostWithPreheader(CurLoop))
227 // Determine the block to which to hoist instructions. If we can't find a
228 // suitable loop preheader, we can't do any hoisting.
230 // FIXME: We are only hoisting if the basic block coming into this loop
231 // has only one successor. This isn't the case in general because we haven't
232 // broken critical edges or added preheaders.
233 CurPreheader = CurLoop->getLoopPreheader();
237 // CSEMap is initialized for loop header when the first instruction is
239 MachineDomTreeNode *N = DT->getNode(CurLoop->getHeader());
241 HoistRegionPostRA(N);
251 /// InstructionStoresToFI - Return true if instruction stores to the
253 static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
254 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
255 oe = MI->memoperands_end(); o != oe; ++o) {
256 if (!(*o)->isStore() || !(*o)->getValue())
258 if (const FixedStackPseudoSourceValue *Value =
259 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
260 if (Value->getFrameIndex() == FI)
267 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
268 /// gather register def and frame object update information.
269 void MachineLICM::ProcessMI(MachineInstr *MI,
270 unsigned *PhysRegDefs,
271 SmallSet<int, 32> &StoredFIs,
272 SmallVector<CandidateInfo, 32> &Candidates) {
273 bool RuledOut = false;
275 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
276 const MachineOperand &MO = MI->getOperand(i);
278 // Remember if the instruction stores to the frame index.
279 int FI = MO.getIndex();
280 if (!StoredFIs.count(FI) &&
281 MFI->isSpillSlotObjectIndex(FI) &&
282 InstructionStoresToFI(MI, FI))
283 StoredFIs.insert(FI);
289 unsigned Reg = MO.getReg();
292 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
293 "Not expecting virtual register!");
298 if (MO.isImplicit()) {
300 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
303 // Non-dead implicit def? This cannot be hoisted.
305 // No need to check if a dead implicit def is also defined by
306 // another instruction.
310 // FIXME: For now, avoid instructions with multiple defs, unless
311 // it's a dead implicit def.
317 // If we have already seen another instruction that defines the same
318 // register, then this is not safe.
319 if (++PhysRegDefs[Reg] > 1)
320 // MI defined register is seen defined by another instruction in
321 // the loop, it cannot be a LICM candidate.
323 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
324 if (++PhysRegDefs[*AS] > 1)
328 // FIXME: Only consider reloads for now. We should be able to handle
329 // remats which does not have register operands.
330 if (Def && !RuledOut) {
332 if (TII->isLoadFromStackSlot(MI, FI) &&
333 MFI->isSpillSlotObjectIndex(FI))
334 Candidates.push_back(CandidateInfo(MI, FI, Def));
338 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
339 /// invariants out to the preheader.
340 void MachineLICM::HoistRegionPostRA(MachineDomTreeNode *N) {
341 assert(N != 0 && "Null dominator tree node?");
343 unsigned NumRegs = TRI->getNumRegs();
344 unsigned *PhysRegDefs = new unsigned[NumRegs];
345 std::fill(PhysRegDefs, PhysRegDefs + NumRegs, 0);
347 SmallVector<CandidateInfo, 32> Candidates;
348 SmallSet<int, 32> StoredFIs;
350 // Walk the entire region, count number of defs for each register, and
351 // return potential LICM candidates.
352 SmallVector<MachineDomTreeNode*, 8> WorkList;
353 WorkList.push_back(N);
355 N = WorkList.pop_back_val();
356 MachineBasicBlock *BB = N->getBlock();
358 if (!CurLoop->contains(MLI->getLoopFor(BB)))
360 // Conservatively treat live-in's as an external def.
361 // FIXME: That means a reload that're reused in successor block(s) will not
363 for (MachineBasicBlock::livein_iterator I = BB->livein_begin(),
364 E = BB->livein_end(); I != E; ++I) {
367 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
371 for (MachineBasicBlock::iterator
372 MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
373 MachineInstr *MI = &*MII;
374 ProcessMI(MI, PhysRegDefs, StoredFIs, Candidates);
377 const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
378 for (unsigned I = 0, E = Children.size(); I != E; ++I)
379 WorkList.push_back(Children[I]);
380 } while (!WorkList.empty());
382 // Now evaluate whether the potential candidates qualify.
383 // 1. Check if the candidate defined register is defined by another
384 // instruction in the loop.
385 // 2. If the candidate is a load from stack slot (always true for now),
386 // check if the slot is stored anywhere in the loop.
387 for (unsigned i = 0, e = Candidates.size(); i != e; ++i) {
388 if (StoredFIs.count(Candidates[i].FI))
391 if (PhysRegDefs[Candidates[i].Def] == 1)
392 HoistPostRA(Candidates[i].MI, Candidates[i].Def);
395 delete[] PhysRegDefs;
398 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the
399 /// backedge path from MBB to LoopHeader.
400 void MachineLICM::AddToLiveIns(unsigned Reg, MachineBasicBlock *MBB,
401 MachineBasicBlock *LoopHeader) {
402 SmallPtrSet<MachineBasicBlock*, 4> Visited;
403 SmallVector<MachineBasicBlock*, 4> WorkList;
404 WorkList.push_back(MBB);
406 MBB = WorkList.pop_back_val();
407 if (!Visited.insert(MBB))
410 if (MBB == LoopHeader)
412 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
413 E = MBB->pred_end(); PI != E; ++PI)
414 WorkList.push_back(*PI);
415 } while (!WorkList.empty());
418 /// HoistPostRA - When an instruction is found to only use loop invariant
419 /// operands that is safe to hoist, this instruction is called to do the
421 void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
422 // Now move the instructions to the predecessor, inserting it before any
423 // terminator instructions.
425 dbgs() << "Hoisting " << *MI;
426 if (CurPreheader->getBasicBlock())
427 dbgs() << " to MachineBasicBlock "
428 << CurPreheader->getName();
429 if (MI->getParent()->getBasicBlock())
430 dbgs() << " from MachineBasicBlock "
431 << MI->getParent()->getName();
435 // Splice the instruction to the preheader.
436 MachineBasicBlock *MBB = MI->getParent();
437 CurPreheader->splice(CurPreheader->getFirstTerminator(), MBB, MI);
439 // Add register to livein list to BBs in the path from loop header to original
440 // BB. Note, currently it's not necessary to worry about adding it to all BB's
441 // with uses. Reload that're reused in successor block(s) are not being
443 AddToLiveIns(Def, MBB, CurLoop->getHeader());
449 /// HoistRegion - Walk the specified region of the CFG (defined by all blocks
450 /// dominated by the specified block, and that are in the current loop) in depth
451 /// first order w.r.t the DominatorTree. This allows us to visit definitions
452 /// before uses, allowing us to hoist a loop body in one pass without iteration.
454 void MachineLICM::HoistRegion(MachineDomTreeNode *N) {
455 assert(N != 0 && "Null dominator tree node?");
456 MachineBasicBlock *BB = N->getBlock();
458 // If this subregion is not in the top level loop at all, exit.
459 if (!CurLoop->contains(BB)) return;
461 for (MachineBasicBlock::iterator
462 MII = BB->begin(), E = BB->end(); MII != E; ) {
463 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
468 const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
469 for (unsigned I = 0, E = Children.size(); I != E; ++I)
470 HoistRegion(Children[I]);
473 /// IsLoopInvariantInst - Returns true if the instruction is loop
474 /// invariant. I.e., all virtual register operands are defined outside of the
475 /// loop, physical registers aren't accessed explicitly, and there are no side
476 /// effects that aren't captured by the operands or other flags.
478 bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
479 const TargetInstrDesc &TID = I.getDesc();
481 // Ignore stuff that we obviously can't hoist.
482 if (TID.mayStore() || TID.isCall() || TID.isTerminator() ||
483 TID.hasUnmodeledSideEffects())
487 // Okay, this instruction does a load. As a refinement, we allow the target
488 // to decide whether the loaded value is actually a constant. If so, we can
489 // actually use it as a load.
490 if (!I.isInvariantLoad(AA))
491 // FIXME: we should be able to hoist loads with no other side effects if
492 // there are no other instructions which can change memory in this loop.
493 // This is a trivial form of alias analysis.
497 // The instruction is loop invariant if all of its operands are.
498 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
499 const MachineOperand &MO = I.getOperand(i);
504 unsigned Reg = MO.getReg();
505 if (Reg == 0) continue;
507 // Don't hoist an instruction that uses or defines a physical register.
508 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
510 // If the physreg has no defs anywhere, it's just an ambient register
511 // and we can freely move its uses. Alternatively, if it's allocatable,
512 // it could get allocated to something with a def during allocation.
513 if (!RegInfo->def_empty(Reg))
515 if (AllocatableSet.test(Reg))
517 // Check for a def among the register's aliases too.
518 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
519 unsigned AliasReg = *Alias;
520 if (!RegInfo->def_empty(AliasReg))
522 if (AllocatableSet.test(AliasReg))
525 // Otherwise it's safe to move.
527 } else if (!MO.isDead()) {
528 // A def that isn't dead. We can't move it.
530 } else if (CurLoop->getHeader()->isLiveIn(Reg)) {
531 // If the reg is live into the loop, we can't hoist an instruction
532 // which would clobber it.
540 assert(RegInfo->getVRegDef(Reg) &&
541 "Machine instr not mapped for this vreg?!");
543 // If the loop contains the definition of an operand, then the instruction
544 // isn't loop invariant.
545 if (CurLoop->contains(RegInfo->getVRegDef(Reg)))
549 // If we got this far, the instruction is loop invariant!
554 /// HasPHIUses - Return true if the specified register has any PHI use.
555 static bool HasPHIUses(unsigned Reg, MachineRegisterInfo *RegInfo) {
556 for (MachineRegisterInfo::use_iterator UI = RegInfo->use_begin(Reg),
557 UE = RegInfo->use_end(); UI != UE; ++UI) {
558 MachineInstr *UseMI = &*UI;
565 /// isLoadFromConstantMemory - Return true if the given instruction is a
566 /// load from constant memory. Machine LICM will hoist these even if they are
567 /// not re-materializable.
568 bool MachineLICM::isLoadFromConstantMemory(MachineInstr *MI) {
569 if (!MI->getDesc().mayLoad()) return false;
570 if (!MI->hasOneMemOperand()) return false;
571 MachineMemOperand *MMO = *MI->memoperands_begin();
572 if (MMO->isVolatile()) return false;
573 if (!MMO->getValue()) return false;
574 const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(MMO->getValue());
576 MachineFunction &MF = *MI->getParent()->getParent();
577 return PSV->isConstant(MF.getFrameInfo());
579 return AA->pointsToConstantMemory(MMO->getValue());
583 /// IsProfitableToHoist - Return true if it is potentially profitable to hoist
584 /// the given loop invariant.
585 bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
586 if (MI.isImplicitDef())
589 // FIXME: For now, only hoist re-materilizable instructions. LICM will
590 // increase register pressure. We want to make sure it doesn't increase
592 // Also hoist loads from constant memory, e.g. load from stubs, GOT. Hoisting
593 // these tend to help performance in low register pressure situation. The
594 // trade off is it may cause spill in high pressure situation. It will end up
595 // adding a store in the loop preheader. But the reload is no more expensive.
596 // The side benefit is these loads are frequently CSE'ed.
597 if (!TII->isTriviallyReMaterializable(&MI, AA)) {
598 if (!isLoadFromConstantMemory(&MI))
602 // If result(s) of this instruction is used by PHIs, then don't hoist it.
603 // The presence of joins makes it difficult for current register allocator
604 // implementation to perform remat.
605 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
606 const MachineOperand &MO = MI.getOperand(i);
607 if (!MO.isReg() || !MO.isDef())
609 if (HasPHIUses(MO.getReg(), RegInfo))
616 MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
617 // If not, we may be able to unfold a load and hoist that.
618 // First test whether the instruction is loading from an amenable
620 if (!isLoadFromConstantMemory(MI))
623 // Next determine the register class for a temporary register.
624 unsigned LoadRegIndex;
626 TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(),
628 /*UnfoldStore=*/false,
630 if (NewOpc == 0) return 0;
631 const TargetInstrDesc &TID = TII->get(NewOpc);
632 if (TID.getNumDefs() != 1) return 0;
633 const TargetRegisterClass *RC = TID.OpInfo[LoadRegIndex].getRegClass(TRI);
634 // Ok, we're unfolding. Create a temporary register and do the unfold.
635 unsigned Reg = RegInfo->createVirtualRegister(RC);
637 MachineFunction &MF = *MI->getParent()->getParent();
638 SmallVector<MachineInstr *, 2> NewMIs;
640 TII->unfoldMemoryOperand(MF, MI, Reg,
641 /*UnfoldLoad=*/true, /*UnfoldStore=*/false,
645 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
647 assert(NewMIs.size() == 2 &&
648 "Unfolded a load into multiple instructions!");
649 MachineBasicBlock *MBB = MI->getParent();
650 MBB->insert(MI, NewMIs[0]);
651 MBB->insert(MI, NewMIs[1]);
652 // If unfolding produced a load that wasn't loop-invariant or profitable to
653 // hoist, discard the new instructions and bail.
654 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
655 NewMIs[0]->eraseFromParent();
656 NewMIs[1]->eraseFromParent();
659 // Otherwise we successfully unfolded a load that we can hoist.
660 MI->eraseFromParent();
664 void MachineLICM::InitCSEMap(MachineBasicBlock *BB) {
665 for (MachineBasicBlock::iterator I = BB->begin(),E = BB->end(); I != E; ++I) {
666 const MachineInstr *MI = &*I;
667 // FIXME: For now, only hoist re-materilizable instructions. LICM will
668 // increase register pressure. We want to make sure it doesn't increase
670 if (TII->isTriviallyReMaterializable(MI, AA)) {
671 unsigned Opcode = MI->getOpcode();
672 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
673 CI = CSEMap.find(Opcode);
674 if (CI != CSEMap.end())
675 CI->second.push_back(MI);
677 std::vector<const MachineInstr*> CSEMIs;
678 CSEMIs.push_back(MI);
679 CSEMap.insert(std::make_pair(Opcode, CSEMIs));
686 MachineLICM::LookForDuplicate(const MachineInstr *MI,
687 std::vector<const MachineInstr*> &PrevMIs) {
688 for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) {
689 const MachineInstr *PrevMI = PrevMIs[i];
690 if (TII->produceSameValue(MI, PrevMI))
696 bool MachineLICM::EliminateCSE(MachineInstr *MI,
697 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI) {
698 if (CI == CSEMap.end())
701 if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
702 DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
704 // Replace virtual registers defined by MI by their counterparts defined
706 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
707 const MachineOperand &MO = MI->getOperand(i);
709 // Physical registers may not differ here.
710 assert((!MO.isReg() || MO.getReg() == 0 ||
711 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
712 MO.getReg() == Dup->getOperand(i).getReg()) &&
713 "Instructions with different phys regs are not identical!");
715 if (MO.isReg() && MO.isDef() &&
716 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
717 RegInfo->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg());
719 MI->eraseFromParent();
726 /// Hoist - When an instruction is found to use only loop invariant operands
727 /// that are safe to hoist, this instruction is called to do the dirty work.
729 void MachineLICM::Hoist(MachineInstr *MI) {
730 // First check whether we should hoist this instruction.
731 if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
732 // If not, try unfolding a hoistable load.
733 MI = ExtractHoistableLoad(MI);
737 // Now move the instructions to the predecessor, inserting it before any
738 // terminator instructions.
740 dbgs() << "Hoisting " << *MI;
741 if (CurPreheader->getBasicBlock())
742 dbgs() << " to MachineBasicBlock "
743 << CurPreheader->getName();
744 if (MI->getParent()->getBasicBlock())
745 dbgs() << " from MachineBasicBlock "
746 << MI->getParent()->getName();
750 // If this is the first instruction being hoisted to the preheader,
751 // initialize the CSE map with potential common expressions.
752 InitCSEMap(CurPreheader);
754 // Look for opportunity to CSE the hoisted instruction.
755 unsigned Opcode = MI->getOpcode();
756 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
757 CI = CSEMap.find(Opcode);
758 if (!EliminateCSE(MI, CI)) {
759 // Otherwise, splice the instruction to the preheader.
760 CurPreheader->splice(CurPreheader->getFirstTerminator(),MI->getParent(),MI);
762 // Add to the CSE map.
763 if (CI != CSEMap.end())
764 CI->second.push_back(MI);
766 std::vector<const MachineInstr*> CSEMIs;
767 CSEMIs.push_back(MI);
768 CSEMap.insert(std::make_pair(Opcode, CSEMIs));