1 //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implementation of the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineRegisterInfo.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Support/CommandLine.h"
20 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
21 VRegInfo.reserve(256);
22 RegAllocHints.reserve(256);
23 RegClass2VRegMap = new std::vector<unsigned>[TRI.getNumRegClasses()];
24 UsedPhysRegs.resize(TRI.getNumRegs());
26 // Create the physreg use/def lists.
27 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
28 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
31 MachineRegisterInfo::~MachineRegisterInfo() {
33 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
34 assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 &&
35 "Vreg use list non-empty still?");
36 for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
37 assert(!PhysRegUseDefLists[i] &&
38 "PhysRegUseDefLists has entries after all instructions are deleted");
40 delete [] PhysRegUseDefLists;
41 delete [] RegClass2VRegMap;
44 /// setRegClass - Set the register class of the specified virtual register.
47 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
48 const TargetRegisterClass *OldRC = VRegInfo[Reg].first;
49 VRegInfo[Reg].first = RC;
51 // Remove from old register class's vregs list. This may be slow but
52 // fortunately this operation is rarely needed.
53 std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()];
54 std::vector<unsigned>::iterator I =
55 std::find(VRegs.begin(), VRegs.end(), Reg);
58 // Add to new register class's vregs list.
59 RegClass2VRegMap[RC->getID()].push_back(Reg);
62 const TargetRegisterClass *
63 MachineRegisterInfo::constrainRegClass(unsigned Reg,
64 const TargetRegisterClass *RC) {
65 const TargetRegisterClass *OldRC = getRegClass(Reg);
68 const TargetRegisterClass *NewRC = getCommonSubClass(OldRC, RC);
72 setRegClass(Reg, NewRC);
76 /// createVirtualRegister - Create and return a new virtual register in the
77 /// function with the specified register class.
80 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
81 assert(RegClass && "Cannot create register without RegClass!");
82 assert(RegClass->isAllocatable() &&
83 "Virtual register RegClass must be allocatable.");
85 // New virtual register number.
86 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
88 // Add a reg, but keep track of whether the vector reallocated or not.
89 const unsigned FirstVirtReg = TargetRegisterInfo::index2VirtReg(0);
90 void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg];
92 VRegInfo[Reg].first = RegClass;
93 RegAllocHints.grow(Reg);
95 if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase)
96 // The vector reallocated, handle this now.
97 HandleVRegListReallocation();
98 RegClass2VRegMap[RegClass->getID()].push_back(Reg);
102 /// HandleVRegListReallocation - We just added a virtual register to the
103 /// VRegInfo info list and it reallocated. Update the use/def lists info
105 void MachineRegisterInfo::HandleVRegListReallocation() {
106 // The back pointers for the vreg lists point into the previous vector.
107 // Update them to point to their correct slots.
108 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
109 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
110 MachineOperand *List = VRegInfo[Reg].second;
112 // Update the back-pointer to be accurate once more.
113 List->Contents.Reg.Prev = &VRegInfo[Reg].second;
117 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
118 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
119 /// except that it also changes any definitions of the register as well.
120 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
121 assert(FromReg != ToReg && "Cannot replace a reg with itself");
123 // TODO: This could be more efficient by bulk changing the operands.
124 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
125 MachineOperand &O = I.getOperand();
132 /// getVRegDef - Return the machine instr that defines the specified virtual
133 /// register or null if none is found. This assumes that the code is in SSA
134 /// form, so there should only be one definition.
135 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
136 // Since we are in SSA form, we can use the first definition.
138 return &*def_begin(Reg);
142 bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const {
143 use_iterator UI = use_begin(RegNo);
146 return ++UI == use_end();
149 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
150 use_nodbg_iterator UI = use_nodbg_begin(RegNo);
151 if (UI == use_nodbg_end())
153 return ++UI == use_nodbg_end();
156 /// clearKillFlags - Iterate over all the uses of the given register and
157 /// clear the kill flag from the MachineOperand. This function is used by
158 /// optimization passes which extend register lifetimes and need only
159 /// preserve conservative kill flag information.
160 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
161 for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
162 UI.getOperand().setIsKill(false);
165 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
166 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
167 if (I->first == Reg || I->second == Reg)
172 bool MachineRegisterInfo::isLiveOut(unsigned Reg) const {
173 for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
179 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
180 /// corresponding live-in physical register.
181 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
182 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
183 if (I->second == VReg)
188 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
189 /// corresponding live-in physical register.
190 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
191 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
192 if (I->first == PReg)
197 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
198 /// into the given entry block.
200 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
201 const TargetRegisterInfo &TRI,
202 const TargetInstrInfo &TII) {
203 // Emit the copies into the top of the block.
204 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
205 if (LiveIns[i].second) {
206 if (use_empty(LiveIns[i].second)) {
207 // The livein has no uses. Drop it.
209 // It would be preferable to have isel avoid creating live-in
210 // records for unused arguments in the first place, but it's
211 // complicated by the debug info code for arguments.
212 LiveIns.erase(LiveIns.begin() + i);
216 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
217 TII.get(TargetOpcode::COPY), LiveIns[i].second)
218 .addReg(LiveIns[i].first);
220 // Add the register to the entry block live-in set.
221 EntryMBB->addLiveIn(LiveIns[i].first);
224 // Add the register to the entry block live-in set.
225 EntryMBB->addLiveIn(LiveIns[i].first);
229 void MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) {
230 for (int i = UsedPhysRegs.find_first(); i >= 0;
231 i = UsedPhysRegs.find_next(i))
232 for (const unsigned *SS = TRI.getSubRegisters(i);
233 unsigned SubReg = *SS; ++SS)
234 if (SubReg > unsigned(i))
235 UsedPhysRegs.set(SubReg);
239 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
240 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
241 I.getOperand().getParent()->dump();