1 //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implementation of the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineRegisterInfo.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Target/TargetMachine.h"
20 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI)
21 : TRI(&TRI), IsSSA(true), TracksLiveness(true) {
22 VRegInfo.reserve(256);
23 RegAllocHints.reserve(256);
24 UsedRegUnits.resize(TRI.getNumRegUnits());
25 UsedPhysRegMask.resize(TRI.getNumRegs());
27 // Create the physreg use/def lists.
28 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
29 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
32 MachineRegisterInfo::~MachineRegisterInfo() {
33 delete [] PhysRegUseDefLists;
36 /// setRegClass - Set the register class of the specified virtual register.
39 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
40 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
41 VRegInfo[Reg].first = RC;
44 const TargetRegisterClass *
45 MachineRegisterInfo::constrainRegClass(unsigned Reg,
46 const TargetRegisterClass *RC,
47 unsigned MinNumRegs) {
48 const TargetRegisterClass *OldRC = getRegClass(Reg);
51 const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC);
52 if (!NewRC || NewRC == OldRC)
54 if (NewRC->getNumRegs() < MinNumRegs)
56 setRegClass(Reg, NewRC);
61 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
62 const TargetInstrInfo *TII = TM.getInstrInfo();
63 const TargetRegisterClass *OldRC = getRegClass(Reg);
64 const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
66 // Stop early if there is no room to grow.
70 // Accumulate constraints from all uses.
71 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
73 const TargetRegisterClass *OpRC =
74 I->getRegClassConstraint(I.getOperandNo(), TII, TRI);
75 if (unsigned SubIdx = I.getOperand().getSubReg()) {
77 NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx);
79 NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx);
81 NewRC = TRI->getCommonSubClass(NewRC, OpRC);
82 if (!NewRC || NewRC == OldRC)
85 setRegClass(Reg, NewRC);
89 /// createVirtualRegister - Create and return a new virtual register in the
90 /// function with the specified register class.
93 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
94 assert(RegClass && "Cannot create register without RegClass!");
95 assert(RegClass->isAllocatable() &&
96 "Virtual register RegClass must be allocatable.");
98 // New virtual register number.
99 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
101 VRegInfo[Reg].first = RegClass;
102 RegAllocHints.grow(Reg);
106 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
107 void MachineRegisterInfo::clearVirtRegs() {
109 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
110 assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 &&
111 "Vreg use list non-empty still?");
116 /// Add MO to the linked list of operands for its register.
117 void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
118 assert(!MO->isOnRegUseList() && "Already on list");
119 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
120 MachineOperand *const Head = HeadRef;
122 // Head points to the first list element.
123 // Next is NULL on the last list element.
124 // Prev pointers are circular, so Head->Prev == Last.
126 // Head is NULL for an empty list.
128 MO->Contents.Reg.Prev = MO;
129 MO->Contents.Reg.Next = 0;
133 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
135 // Insert MO between Last and Head in the circular Prev chain.
136 MachineOperand *Last = Head->Contents.Reg.Prev;
137 assert(Last && "Inconsistent use list");
138 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
139 Head->Contents.Reg.Prev = MO;
140 MO->Contents.Reg.Prev = Last;
142 // Def operands always precede uses. This allows def_iterator to stop early.
143 // Insert def operands at the front, and use operands at the back.
145 // Insert def at the front.
146 MO->Contents.Reg.Next = Head;
149 // Insert use at the end.
150 MO->Contents.Reg.Next = 0;
151 Last->Contents.Reg.Next = MO;
155 /// Remove MO from its use-def list.
156 void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
157 assert(MO->isOnRegUseList() && "Operand not on use list");
158 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
159 MachineOperand *const Head = HeadRef;
160 assert(Head && "List already empty");
162 // Unlink this from the doubly linked list of operands.
163 MachineOperand *Next = MO->Contents.Reg.Next;
164 MachineOperand *Prev = MO->Contents.Reg.Prev;
166 // Prev links are circular, next link is NULL instead of looping back to Head.
170 Prev->Contents.Reg.Next = Next;
172 (Next ? Next : Head)->Contents.Reg.Prev = Prev;
174 MO->Contents.Reg.Prev = 0;
175 MO->Contents.Reg.Next = 0;
178 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
180 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
181 /// operands that won't be destroyed, which is OK because the MO destructor is
184 /// The Src and Dst ranges may overlap.
185 void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
188 assert(Src != Dst && NumOps && "Noop moveOperands");
190 // Copy backwards if Dst is within the Src range.
192 if (Dst >= Src && Dst < Src + NumOps) {
198 // Copy one operand at a time.
200 new (Dst) MachineOperand(*Src);
202 // Dst takes Src's place in the use-def chain.
204 MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
205 MachineOperand *Prev = Src->Contents.Reg.Prev;
206 MachineOperand *Next = Src->Contents.Reg.Next;
207 assert(Head && "List empty, but operand is chained");
208 assert(Prev && "Operand was not on use-def list");
210 // Prev links are circular, next link is NULL instead of looping back to
215 Prev->Contents.Reg.Next = Dst;
217 // Update Prev pointer. This also works when Src was pointing to itself
218 // in a 1-element list. In that case Head == Dst.
219 (Next ? Next : Head)->Contents.Reg.Prev = Dst;
227 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
228 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
229 /// except that it also changes any definitions of the register as well.
230 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
231 assert(FromReg != ToReg && "Cannot replace a reg with itself");
233 // TODO: This could be more efficient by bulk changing the operands.
234 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
235 MachineOperand &O = I.getOperand();
242 /// getVRegDef - Return the machine instr that defines the specified virtual
243 /// register or null if none is found. This assumes that the code is in SSA
244 /// form, so there should only be one definition.
245 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
246 // Since we are in SSA form, we can use the first definition.
247 def_iterator I = def_begin(Reg);
248 assert((I.atEnd() || llvm::next(I) == def_end()) &&
249 "getVRegDef assumes a single definition or no definition");
250 return !I.atEnd() ? &*I : 0;
253 /// getUniqueVRegDef - Return the unique machine instr that defines the
254 /// specified virtual register or null if none is found. If there are
255 /// multiple definitions or no definition, return null.
256 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const {
257 if (def_empty(Reg)) return 0;
258 def_iterator I = def_begin(Reg);
259 if (llvm::next(I) != def_end())
264 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
265 use_nodbg_iterator UI = use_nodbg_begin(RegNo);
266 if (UI == use_nodbg_end())
268 return ++UI == use_nodbg_end();
271 /// clearKillFlags - Iterate over all the uses of the given register and
272 /// clear the kill flag from the MachineOperand. This function is used by
273 /// optimization passes which extend register lifetimes and need only
274 /// preserve conservative kill flag information.
275 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
276 for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
277 UI.getOperand().setIsKill(false);
280 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
281 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
282 if (I->first == Reg || I->second == Reg)
287 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
288 /// corresponding live-in physical register.
289 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
290 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
291 if (I->second == VReg)
296 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
297 /// corresponding live-in physical register.
298 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
299 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
300 if (I->first == PReg)
305 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
306 /// into the given entry block.
308 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
309 const TargetRegisterInfo &TRI,
310 const TargetInstrInfo &TII) {
311 // Emit the copies into the top of the block.
312 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
313 if (LiveIns[i].second) {
314 if (use_empty(LiveIns[i].second)) {
315 // The livein has no uses. Drop it.
317 // It would be preferable to have isel avoid creating live-in
318 // records for unused arguments in the first place, but it's
319 // complicated by the debug info code for arguments.
320 LiveIns.erase(LiveIns.begin() + i);
324 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
325 TII.get(TargetOpcode::COPY), LiveIns[i].second)
326 .addReg(LiveIns[i].first);
328 // Add the register to the entry block live-in set.
329 EntryMBB->addLiveIn(LiveIns[i].first);
332 // Add the register to the entry block live-in set.
333 EntryMBB->addLiveIn(LiveIns[i].first);
338 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
339 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
340 I.getOperand().getParent()->dump();
344 void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
345 ReservedRegs = TRI->getReservedRegs(MF);
346 assert(ReservedRegs.size() == TRI->getNumRegs() &&
347 "Invalid ReservedRegs vector from target");
350 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
351 const MachineFunction &MF) const {
352 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
354 // Check if any overlapping register is modified, or allocatable so it may be
356 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI)
357 if (!def_empty(*AI) || isAllocatable(*AI))