1 //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implementation of the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineRegisterInfo.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Support/CommandLine.h"
20 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
21 VRegInfo.reserve(256);
22 RegAllocHints.reserve(256);
23 UsedPhysRegs.resize(TRI.getNumRegs());
25 // Create the physreg use/def lists.
26 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
27 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
30 MachineRegisterInfo::~MachineRegisterInfo() {
32 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
33 assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 &&
34 "Vreg use list non-empty still?");
35 for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
36 assert(!PhysRegUseDefLists[i] &&
37 "PhysRegUseDefLists has entries after all instructions are deleted");
39 delete [] PhysRegUseDefLists;
42 /// setRegClass - Set the register class of the specified virtual register.
45 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
46 VRegInfo[Reg].first = RC;
49 const TargetRegisterClass *
50 MachineRegisterInfo::constrainRegClass(unsigned Reg,
51 const TargetRegisterClass *RC) {
52 const TargetRegisterClass *OldRC = getRegClass(Reg);
55 const TargetRegisterClass *NewRC = getCommonSubClass(OldRC, RC);
59 setRegClass(Reg, NewRC);
63 /// createVirtualRegister - Create and return a new virtual register in the
64 /// function with the specified register class.
67 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
68 assert(RegClass && "Cannot create register without RegClass!");
69 assert(RegClass->isAllocatable() &&
70 "Virtual register RegClass must be allocatable.");
72 // New virtual register number.
73 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
75 // Add a reg, but keep track of whether the vector reallocated or not.
76 const unsigned FirstVirtReg = TargetRegisterInfo::index2VirtReg(0);
77 void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg];
79 VRegInfo[Reg].first = RegClass;
80 RegAllocHints.grow(Reg);
82 if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase)
83 // The vector reallocated, handle this now.
84 HandleVRegListReallocation();
88 /// HandleVRegListReallocation - We just added a virtual register to the
89 /// VRegInfo info list and it reallocated. Update the use/def lists info
91 void MachineRegisterInfo::HandleVRegListReallocation() {
92 // The back pointers for the vreg lists point into the previous vector.
93 // Update them to point to their correct slots.
94 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
95 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
96 MachineOperand *List = VRegInfo[Reg].second;
98 // Update the back-pointer to be accurate once more.
99 List->Contents.Reg.Prev = &VRegInfo[Reg].second;
103 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
104 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
105 /// except that it also changes any definitions of the register as well.
106 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
107 assert(FromReg != ToReg && "Cannot replace a reg with itself");
109 // TODO: This could be more efficient by bulk changing the operands.
110 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
111 MachineOperand &O = I.getOperand();
118 /// getVRegDef - Return the machine instr that defines the specified virtual
119 /// register or null if none is found. This assumes that the code is in SSA
120 /// form, so there should only be one definition.
121 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
122 // Since we are in SSA form, we can use the first definition.
124 return &*def_begin(Reg);
128 bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const {
129 use_iterator UI = use_begin(RegNo);
132 return ++UI == use_end();
135 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
136 use_nodbg_iterator UI = use_nodbg_begin(RegNo);
137 if (UI == use_nodbg_end())
139 return ++UI == use_nodbg_end();
142 /// clearKillFlags - Iterate over all the uses of the given register and
143 /// clear the kill flag from the MachineOperand. This function is used by
144 /// optimization passes which extend register lifetimes and need only
145 /// preserve conservative kill flag information.
146 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
147 for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
148 UI.getOperand().setIsKill(false);
151 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
152 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
153 if (I->first == Reg || I->second == Reg)
158 bool MachineRegisterInfo::isLiveOut(unsigned Reg) const {
159 for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
165 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
166 /// corresponding live-in physical register.
167 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
168 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
169 if (I->second == VReg)
174 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
175 /// corresponding live-in physical register.
176 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
177 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
178 if (I->first == PReg)
183 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
184 /// into the given entry block.
186 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
187 const TargetRegisterInfo &TRI,
188 const TargetInstrInfo &TII) {
189 // Emit the copies into the top of the block.
190 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
191 if (LiveIns[i].second) {
192 if (use_empty(LiveIns[i].second)) {
193 // The livein has no uses. Drop it.
195 // It would be preferable to have isel avoid creating live-in
196 // records for unused arguments in the first place, but it's
197 // complicated by the debug info code for arguments.
198 LiveIns.erase(LiveIns.begin() + i);
202 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
203 TII.get(TargetOpcode::COPY), LiveIns[i].second)
204 .addReg(LiveIns[i].first);
206 // Add the register to the entry block live-in set.
207 EntryMBB->addLiveIn(LiveIns[i].first);
210 // Add the register to the entry block live-in set.
211 EntryMBB->addLiveIn(LiveIns[i].first);
215 void MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) {
216 for (int i = UsedPhysRegs.find_first(); i >= 0;
217 i = UsedPhysRegs.find_next(i))
218 for (const unsigned *SS = TRI.getSubRegisters(i);
219 unsigned SubReg = *SS; ++SS)
220 if (SubReg > unsigned(i))
221 UsedPhysRegs.set(SubReg);
225 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
226 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
227 I.getOperand().getParent()->dump();