1 //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implementation of the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineRegisterInfo.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Support/CommandLine.h"
20 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
21 VRegInfo.reserve(256);
22 RegAllocHints.reserve(256);
23 RegClass2VRegMap = new std::vector<unsigned>[TRI.getNumRegClasses()];
24 UsedPhysRegs.resize(TRI.getNumRegs());
26 // Create the physreg use/def lists.
27 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
28 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
31 MachineRegisterInfo::~MachineRegisterInfo() {
33 for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i)
34 assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?");
35 for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
36 assert(!PhysRegUseDefLists[i] &&
37 "PhysRegUseDefLists has entries after all instructions are deleted");
39 delete [] PhysRegUseDefLists;
40 delete [] RegClass2VRegMap;
43 /// setRegClass - Set the register class of the specified virtual register.
46 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
48 Reg -= TargetRegisterInfo::FirstVirtualRegister;
49 assert(Reg < VRegInfo.size() && "Invalid vreg!");
50 const TargetRegisterClass *OldRC = VRegInfo[Reg].first;
51 VRegInfo[Reg].first = RC;
53 // Remove from old register class's vregs list. This may be slow but
54 // fortunately this operation is rarely needed.
55 std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()];
56 std::vector<unsigned>::iterator I = std::find(VRegs.begin(), VRegs.end(), VR);
59 // Add to new register class's vregs list.
60 RegClass2VRegMap[RC->getID()].push_back(VR);
63 /// createVirtualRegister - Create and return a new virtual register in the
64 /// function with the specified register class.
67 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
68 assert(RegClass && "Cannot create register without RegClass!");
69 // Add a reg, but keep track of whether the vector reallocated or not.
70 void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
71 VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
72 RegAllocHints.push_back(std::make_pair(0, 0));
74 if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)))
75 // The vector reallocated, handle this now.
76 HandleVRegListReallocation();
77 unsigned VR = getLastVirtReg();
78 RegClass2VRegMap[RegClass->getID()].push_back(VR);
82 /// HandleVRegListReallocation - We just added a virtual register to the
83 /// VRegInfo info list and it reallocated. Update the use/def lists info
85 void MachineRegisterInfo::HandleVRegListReallocation() {
86 // The back pointers for the vreg lists point into the previous vector.
87 // Update them to point to their correct slots.
88 for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) {
89 MachineOperand *List = VRegInfo[i].second;
91 // Update the back-pointer to be accurate once more.
92 List->Contents.Reg.Prev = &VRegInfo[i].second;
96 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
97 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
98 /// except that it also changes any definitions of the register as well.
99 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
100 assert(FromReg != ToReg && "Cannot replace a reg with itself");
102 // TODO: This could be more efficient by bulk changing the operands.
103 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
104 MachineOperand &O = I.getOperand();
111 /// getVRegDef - Return the machine instr that defines the specified virtual
112 /// register or null if none is found. This assumes that the code is in SSA
113 /// form, so there should only be one definition.
114 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
115 assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
117 // Since we are in SSA form, we can use the first definition.
119 return &*def_begin(Reg);
123 bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const {
124 use_iterator UI = use_begin(RegNo);
127 return ++UI == use_end();
130 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
131 use_nodbg_iterator UI = use_nodbg_begin(RegNo);
132 if (UI == use_nodbg_end())
134 return ++UI == use_nodbg_end();
137 /// clearKillFlags - Iterate over all the uses of the given register and
138 /// clear the kill flag from the MachineOperand. This function is used by
139 /// optimization passes which extend register lifetimes and need only
140 /// preserve conservative kill flag information.
141 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
142 for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
143 UI.getOperand().setIsKill(false);
146 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
147 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
148 if (I->first == Reg || I->second == Reg)
153 bool MachineRegisterInfo::isLiveOut(unsigned Reg) const {
154 for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
160 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
161 /// corresponding live-in physical register.
162 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
163 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
164 if (I->second == VReg)
169 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
170 /// corresponding live-in physical register.
171 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
172 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
173 if (I->first == PReg)
178 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
179 /// into the given entry block.
181 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
182 const TargetRegisterInfo &TRI,
183 const TargetInstrInfo &TII) {
184 // Emit the copies into the top of the block.
185 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
186 if (LiveIns[i].second) {
187 if (use_empty(LiveIns[i].second)) {
188 // The livein has no uses. Drop it.
190 // It would be preferable to have isel avoid creating live-in
191 // records for unused arguments in the first place, but it's
192 // complicated by the debug info code for arguments.
193 LiveIns.erase(LiveIns.begin() + i);
197 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
198 TII.get(TargetOpcode::COPY), LiveIns[i].second)
199 .addReg(LiveIns[i].first);
201 // Add the register to the entry block live-in set.
202 EntryMBB->addLiveIn(LiveIns[i].first);
205 // Add the register to the entry block live-in set.
206 EntryMBB->addLiveIn(LiveIns[i].first);
210 void MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) {
211 for (int i = UsedPhysRegs.find_first(); i >= 0;
212 i = UsedPhysRegs.find_next(i))
213 for (const unsigned *SS = TRI.getSubRegisters(i);
214 unsigned SubReg = *SS; ++SS)
215 if (SubReg > unsigned(i))
216 UsedPhysRegs.set(SubReg);
220 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
221 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
222 I.getOperand().getParent()->dump();