1 //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implementation of the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineRegisterInfo.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Support/raw_os_ostream.h"
22 MachineRegisterInfo::MachineRegisterInfo(const TargetMachine &TM)
23 : TM(TM), IsSSA(true), TracksLiveness(true) {
24 VRegInfo.reserve(256);
25 RegAllocHints.reserve(256);
26 UsedRegUnits.resize(getTargetRegisterInfo()->getNumRegUnits());
27 UsedPhysRegMask.resize(getTargetRegisterInfo()->getNumRegs());
29 // Create the physreg use/def lists.
31 new MachineOperand*[getTargetRegisterInfo()->getNumRegs()];
32 memset(PhysRegUseDefLists, 0,
33 sizeof(MachineOperand*)*getTargetRegisterInfo()->getNumRegs());
36 MachineRegisterInfo::~MachineRegisterInfo() {
37 delete [] PhysRegUseDefLists;
40 /// setRegClass - Set the register class of the specified virtual register.
43 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
44 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
45 VRegInfo[Reg].first = RC;
48 const TargetRegisterClass *
49 MachineRegisterInfo::constrainRegClass(unsigned Reg,
50 const TargetRegisterClass *RC,
51 unsigned MinNumRegs) {
52 const TargetRegisterClass *OldRC = getRegClass(Reg);
55 const TargetRegisterClass *NewRC =
56 getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
57 if (!NewRC || NewRC == OldRC)
59 if (NewRC->getNumRegs() < MinNumRegs)
61 setRegClass(Reg, NewRC);
66 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
67 const TargetInstrInfo *TII = TM.getInstrInfo();
68 const TargetRegisterClass *OldRC = getRegClass(Reg);
69 const TargetRegisterClass *NewRC =
70 getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC);
72 // Stop early if there is no room to grow.
76 // Accumulate constraints from all uses.
77 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
79 const TargetRegisterClass *OpRC =
80 I->getRegClassConstraint(I.getOperandNo(), TII,
81 getTargetRegisterInfo());
82 if (unsigned SubIdx = I.getOperand().getSubReg()) {
84 NewRC = getTargetRegisterInfo()->getMatchingSuperRegClass(NewRC, OpRC,
87 NewRC = getTargetRegisterInfo()->getSubClassWithSubReg(NewRC, SubIdx);
89 NewRC = getTargetRegisterInfo()->getCommonSubClass(NewRC, OpRC);
90 if (!NewRC || NewRC == OldRC)
93 setRegClass(Reg, NewRC);
97 /// createVirtualRegister - Create and return a new virtual register in the
98 /// function with the specified register class.
101 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
102 assert(RegClass && "Cannot create register without RegClass!");
103 assert(RegClass->isAllocatable() &&
104 "Virtual register RegClass must be allocatable.");
106 // New virtual register number.
107 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
109 VRegInfo[Reg].first = RegClass;
110 RegAllocHints.grow(Reg);
114 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
115 void MachineRegisterInfo::clearVirtRegs() {
117 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
118 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
119 if (!VRegInfo[Reg].second)
122 llvm_unreachable("Remaining virtual register operands");
128 void MachineRegisterInfo::verifyUseList(unsigned Reg) const {
131 for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) {
132 MachineOperand *MO = &I.getOperand();
133 MachineInstr *MI = MO->getParent();
135 errs() << PrintReg(Reg, getTargetRegisterInfo())
136 << " use list MachineOperand " << MO
137 << " has no parent instruction.\n";
140 MachineOperand *MO0 = &MI->getOperand(0);
141 unsigned NumOps = MI->getNumOperands();
142 if (!(MO >= MO0 && MO < MO0+NumOps)) {
143 errs() << PrintReg(Reg, getTargetRegisterInfo())
144 << " use list MachineOperand " << MO
145 << " doesn't belong to parent MI: " << *MI;
149 errs() << PrintReg(Reg, getTargetRegisterInfo())
150 << " MachineOperand " << MO << ": " << *MO
151 << " is not a register\n";
154 if (MO->getReg() != Reg) {
155 errs() << PrintReg(Reg, getTargetRegisterInfo())
156 << " use-list MachineOperand " << MO << ": "
157 << *MO << " is the wrong register\n";
161 assert(Valid && "Invalid use list");
165 void MachineRegisterInfo::verifyUseLists() const {
167 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
168 verifyUseList(TargetRegisterInfo::index2VirtReg(i));
169 for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
174 /// Add MO to the linked list of operands for its register.
175 void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
176 assert(!MO->isOnRegUseList() && "Already on list");
177 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
178 MachineOperand *const Head = HeadRef;
180 // Head points to the first list element.
181 // Next is NULL on the last list element.
182 // Prev pointers are circular, so Head->Prev == Last.
184 // Head is NULL for an empty list.
186 MO->Contents.Reg.Prev = MO;
187 MO->Contents.Reg.Next = 0;
191 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
193 // Insert MO between Last and Head in the circular Prev chain.
194 MachineOperand *Last = Head->Contents.Reg.Prev;
195 assert(Last && "Inconsistent use list");
196 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
197 Head->Contents.Reg.Prev = MO;
198 MO->Contents.Reg.Prev = Last;
200 // Def operands always precede uses. This allows def_iterator to stop early.
201 // Insert def operands at the front, and use operands at the back.
203 // Insert def at the front.
204 MO->Contents.Reg.Next = Head;
207 // Insert use at the end.
208 MO->Contents.Reg.Next = 0;
209 Last->Contents.Reg.Next = MO;
213 /// Remove MO from its use-def list.
214 void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
215 assert(MO->isOnRegUseList() && "Operand not on use list");
216 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
217 MachineOperand *const Head = HeadRef;
218 assert(Head && "List already empty");
220 // Unlink this from the doubly linked list of operands.
221 MachineOperand *Next = MO->Contents.Reg.Next;
222 MachineOperand *Prev = MO->Contents.Reg.Prev;
224 // Prev links are circular, next link is NULL instead of looping back to Head.
228 Prev->Contents.Reg.Next = Next;
230 (Next ? Next : Head)->Contents.Reg.Prev = Prev;
232 MO->Contents.Reg.Prev = 0;
233 MO->Contents.Reg.Next = 0;
236 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
238 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
239 /// operands that won't be destroyed, which is OK because the MO destructor is
242 /// The Src and Dst ranges may overlap.
243 void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
246 assert(Src != Dst && NumOps && "Noop moveOperands");
248 // Copy backwards if Dst is within the Src range.
250 if (Dst >= Src && Dst < Src + NumOps) {
256 // Copy one operand at a time.
258 new (Dst) MachineOperand(*Src);
260 // Dst takes Src's place in the use-def chain.
262 MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
263 MachineOperand *Prev = Src->Contents.Reg.Prev;
264 MachineOperand *Next = Src->Contents.Reg.Next;
265 assert(Head && "List empty, but operand is chained");
266 assert(Prev && "Operand was not on use-def list");
268 // Prev links are circular, next link is NULL instead of looping back to
273 Prev->Contents.Reg.Next = Dst;
275 // Update Prev pointer. This also works when Src was pointing to itself
276 // in a 1-element list. In that case Head == Dst.
277 (Next ? Next : Head)->Contents.Reg.Prev = Dst;
285 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
286 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
287 /// except that it also changes any definitions of the register as well.
288 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
289 assert(FromReg != ToReg && "Cannot replace a reg with itself");
291 // TODO: This could be more efficient by bulk changing the operands.
292 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
293 MachineOperand &O = I.getOperand();
300 /// getVRegDef - Return the machine instr that defines the specified virtual
301 /// register or null if none is found. This assumes that the code is in SSA
302 /// form, so there should only be one definition.
303 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
304 // Since we are in SSA form, we can use the first definition.
305 def_iterator I = def_begin(Reg);
306 assert((I.atEnd() || llvm::next(I) == def_end()) &&
307 "getVRegDef assumes a single definition or no definition");
308 return !I.atEnd() ? &*I : 0;
311 /// getUniqueVRegDef - Return the unique machine instr that defines the
312 /// specified virtual register or null if none is found. If there are
313 /// multiple definitions or no definition, return null.
314 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const {
315 if (def_empty(Reg)) return 0;
316 def_iterator I = def_begin(Reg);
317 if (llvm::next(I) != def_end())
322 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
323 use_nodbg_iterator UI = use_nodbg_begin(RegNo);
324 if (UI == use_nodbg_end())
326 return ++UI == use_nodbg_end();
329 /// clearKillFlags - Iterate over all the uses of the given register and
330 /// clear the kill flag from the MachineOperand. This function is used by
331 /// optimization passes which extend register lifetimes and need only
332 /// preserve conservative kill flag information.
333 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
334 for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
335 UI.getOperand().setIsKill(false);
338 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
339 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
340 if (I->first == Reg || I->second == Reg)
345 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
346 /// corresponding live-in physical register.
347 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
348 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
349 if (I->second == VReg)
354 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
355 /// corresponding live-in physical register.
356 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
357 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
358 if (I->first == PReg)
363 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
364 /// into the given entry block.
366 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
367 const TargetRegisterInfo &TRI,
368 const TargetInstrInfo &TII) {
369 // Emit the copies into the top of the block.
370 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
371 if (LiveIns[i].second) {
372 if (use_empty(LiveIns[i].second)) {
373 // The livein has no uses. Drop it.
375 // It would be preferable to have isel avoid creating live-in
376 // records for unused arguments in the first place, but it's
377 // complicated by the debug info code for arguments.
378 LiveIns.erase(LiveIns.begin() + i);
382 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
383 TII.get(TargetOpcode::COPY), LiveIns[i].second)
384 .addReg(LiveIns[i].first);
386 // Add the register to the entry block live-in set.
387 EntryMBB->addLiveIn(LiveIns[i].first);
390 // Add the register to the entry block live-in set.
391 EntryMBB->addLiveIn(LiveIns[i].first);
396 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
397 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
398 I.getOperand().getParent()->dump();
402 void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
403 ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
404 assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
405 "Invalid ReservedRegs vector from target");
408 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
409 const MachineFunction &MF) const {
410 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
412 // Check if any overlapping register is modified, or allocatable so it may be
414 for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true);
416 if (!def_empty(*AI) || isAllocatable(*AI))