1 //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implementation of the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineRegisterInfo.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/Support/raw_os_ostream.h"
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "llvm/Target/TargetMachine.h"
22 // Pin the vtable to this file.
23 void MachineRegisterInfo::Delegate::anchor() {}
25 MachineRegisterInfo::MachineRegisterInfo(const TargetMachine &TM)
26 : TM(TM), TheDelegate(0), IsSSA(true), TracksLiveness(true) {
27 VRegInfo.reserve(256);
28 RegAllocHints.reserve(256);
29 UsedRegUnits.resize(getTargetRegisterInfo()->getNumRegUnits());
30 UsedPhysRegMask.resize(getTargetRegisterInfo()->getNumRegs());
32 // Create the physreg use/def lists.
34 new MachineOperand*[getTargetRegisterInfo()->getNumRegs()];
35 memset(PhysRegUseDefLists, 0,
36 sizeof(MachineOperand*)*getTargetRegisterInfo()->getNumRegs());
39 MachineRegisterInfo::~MachineRegisterInfo() {
40 delete [] PhysRegUseDefLists;
43 /// setRegClass - Set the register class of the specified virtual register.
46 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
47 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
48 VRegInfo[Reg].first = RC;
51 const TargetRegisterClass *
52 MachineRegisterInfo::constrainRegClass(unsigned Reg,
53 const TargetRegisterClass *RC,
54 unsigned MinNumRegs) {
55 const TargetRegisterClass *OldRC = getRegClass(Reg);
58 const TargetRegisterClass *NewRC =
59 getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
60 if (!NewRC || NewRC == OldRC)
62 if (NewRC->getNumRegs() < MinNumRegs)
64 setRegClass(Reg, NewRC);
69 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
70 const TargetInstrInfo *TII = TM.getInstrInfo();
71 const TargetRegisterClass *OldRC = getRegClass(Reg);
72 const TargetRegisterClass *NewRC =
73 getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC);
75 // Stop early if there is no room to grow.
79 // Accumulate constraints from all uses.
80 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
82 // Apply the effect of the given operand to NewRC.
83 NewRC = I->getRegClassConstraintEffect(I.getOperandNo(), NewRC, TII,
84 getTargetRegisterInfo());
85 if (!NewRC || NewRC == OldRC)
88 setRegClass(Reg, NewRC);
92 /// createVirtualRegister - Create and return a new virtual register in the
93 /// function with the specified register class.
96 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
97 assert(RegClass && "Cannot create register without RegClass!");
98 assert(RegClass->isAllocatable() &&
99 "Virtual register RegClass must be allocatable.");
101 // New virtual register number.
102 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
104 VRegInfo[Reg].first = RegClass;
105 RegAllocHints.grow(Reg);
107 TheDelegate->MRI_NoteNewVirtualRegister(Reg);
111 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
112 void MachineRegisterInfo::clearVirtRegs() {
114 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
115 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
116 if (!VRegInfo[Reg].second)
119 llvm_unreachable("Remaining virtual register operands");
125 void MachineRegisterInfo::verifyUseList(unsigned Reg) const {
128 for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) {
129 MachineOperand *MO = &I.getOperand();
130 MachineInstr *MI = MO->getParent();
132 errs() << PrintReg(Reg, getTargetRegisterInfo())
133 << " use list MachineOperand " << MO
134 << " has no parent instruction.\n";
137 MachineOperand *MO0 = &MI->getOperand(0);
138 unsigned NumOps = MI->getNumOperands();
139 if (!(MO >= MO0 && MO < MO0+NumOps)) {
140 errs() << PrintReg(Reg, getTargetRegisterInfo())
141 << " use list MachineOperand " << MO
142 << " doesn't belong to parent MI: " << *MI;
146 errs() << PrintReg(Reg, getTargetRegisterInfo())
147 << " MachineOperand " << MO << ": " << *MO
148 << " is not a register\n";
151 if (MO->getReg() != Reg) {
152 errs() << PrintReg(Reg, getTargetRegisterInfo())
153 << " use-list MachineOperand " << MO << ": "
154 << *MO << " is the wrong register\n";
158 assert(Valid && "Invalid use list");
162 void MachineRegisterInfo::verifyUseLists() const {
164 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
165 verifyUseList(TargetRegisterInfo::index2VirtReg(i));
166 for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
171 /// Add MO to the linked list of operands for its register.
172 void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
173 assert(!MO->isOnRegUseList() && "Already on list");
174 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
175 MachineOperand *const Head = HeadRef;
177 // Head points to the first list element.
178 // Next is NULL on the last list element.
179 // Prev pointers are circular, so Head->Prev == Last.
181 // Head is NULL for an empty list.
183 MO->Contents.Reg.Prev = MO;
184 MO->Contents.Reg.Next = 0;
188 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
190 // Insert MO between Last and Head in the circular Prev chain.
191 MachineOperand *Last = Head->Contents.Reg.Prev;
192 assert(Last && "Inconsistent use list");
193 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
194 Head->Contents.Reg.Prev = MO;
195 MO->Contents.Reg.Prev = Last;
197 // Def operands always precede uses. This allows def_iterator to stop early.
198 // Insert def operands at the front, and use operands at the back.
200 // Insert def at the front.
201 MO->Contents.Reg.Next = Head;
204 // Insert use at the end.
205 MO->Contents.Reg.Next = 0;
206 Last->Contents.Reg.Next = MO;
210 /// Remove MO from its use-def list.
211 void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
212 assert(MO->isOnRegUseList() && "Operand not on use list");
213 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
214 MachineOperand *const Head = HeadRef;
215 assert(Head && "List already empty");
217 // Unlink this from the doubly linked list of operands.
218 MachineOperand *Next = MO->Contents.Reg.Next;
219 MachineOperand *Prev = MO->Contents.Reg.Prev;
221 // Prev links are circular, next link is NULL instead of looping back to Head.
225 Prev->Contents.Reg.Next = Next;
227 (Next ? Next : Head)->Contents.Reg.Prev = Prev;
229 MO->Contents.Reg.Prev = 0;
230 MO->Contents.Reg.Next = 0;
233 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
235 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
236 /// operands that won't be destroyed, which is OK because the MO destructor is
239 /// The Src and Dst ranges may overlap.
240 void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
243 assert(Src != Dst && NumOps && "Noop moveOperands");
245 // Copy backwards if Dst is within the Src range.
247 if (Dst >= Src && Dst < Src + NumOps) {
253 // Copy one operand at a time.
255 new (Dst) MachineOperand(*Src);
257 // Dst takes Src's place in the use-def chain.
259 MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
260 MachineOperand *Prev = Src->Contents.Reg.Prev;
261 MachineOperand *Next = Src->Contents.Reg.Next;
262 assert(Head && "List empty, but operand is chained");
263 assert(Prev && "Operand was not on use-def list");
265 // Prev links are circular, next link is NULL instead of looping back to
270 Prev->Contents.Reg.Next = Dst;
272 // Update Prev pointer. This also works when Src was pointing to itself
273 // in a 1-element list. In that case Head == Dst.
274 (Next ? Next : Head)->Contents.Reg.Prev = Dst;
282 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
283 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
284 /// except that it also changes any definitions of the register as well.
285 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
286 assert(FromReg != ToReg && "Cannot replace a reg with itself");
288 // TODO: This could be more efficient by bulk changing the operands.
289 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
290 MachineOperand &O = I.getOperand();
297 /// getVRegDef - Return the machine instr that defines the specified virtual
298 /// register or null if none is found. This assumes that the code is in SSA
299 /// form, so there should only be one definition.
300 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
301 // Since we are in SSA form, we can use the first definition.
302 def_iterator I = def_begin(Reg);
303 assert((I.atEnd() || llvm::next(I) == def_end()) &&
304 "getVRegDef assumes a single definition or no definition");
305 return !I.atEnd() ? &*I : 0;
308 /// getUniqueVRegDef - Return the unique machine instr that defines the
309 /// specified virtual register or null if none is found. If there are
310 /// multiple definitions or no definition, return null.
311 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const {
312 if (def_empty(Reg)) return 0;
313 def_iterator I = def_begin(Reg);
314 if (llvm::next(I) != def_end())
319 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
320 use_nodbg_iterator UI = use_nodbg_begin(RegNo);
321 if (UI == use_nodbg_end())
323 return ++UI == use_nodbg_end();
326 /// clearKillFlags - Iterate over all the uses of the given register and
327 /// clear the kill flag from the MachineOperand. This function is used by
328 /// optimization passes which extend register lifetimes and need only
329 /// preserve conservative kill flag information.
330 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
331 for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
332 UI.getOperand().setIsKill(false);
335 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
336 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
337 if (I->first == Reg || I->second == Reg)
342 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
343 /// corresponding live-in physical register.
344 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
345 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
346 if (I->second == VReg)
351 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
352 /// corresponding live-in physical register.
353 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
354 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
355 if (I->first == PReg)
360 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
361 /// into the given entry block.
363 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
364 const TargetRegisterInfo &TRI,
365 const TargetInstrInfo &TII) {
366 // Emit the copies into the top of the block.
367 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
368 if (LiveIns[i].second) {
369 if (use_empty(LiveIns[i].second)) {
370 // The livein has no uses. Drop it.
372 // It would be preferable to have isel avoid creating live-in
373 // records for unused arguments in the first place, but it's
374 // complicated by the debug info code for arguments.
375 LiveIns.erase(LiveIns.begin() + i);
379 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
380 TII.get(TargetOpcode::COPY), LiveIns[i].second)
381 .addReg(LiveIns[i].first);
383 // Add the register to the entry block live-in set.
384 EntryMBB->addLiveIn(LiveIns[i].first);
387 // Add the register to the entry block live-in set.
388 EntryMBB->addLiveIn(LiveIns[i].first);
393 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
394 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
395 I.getOperand().getParent()->dump();
399 void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
400 ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
401 assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
402 "Invalid ReservedRegs vector from target");
405 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
406 const MachineFunction &MF) const {
407 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
409 // Check if any overlapping register is modified, or allocatable so it may be
411 for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true);
413 if (!def_empty(*AI) || isAllocatable(*AI))