1 //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implementation of the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineRegisterInfo.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/IR/Function.h"
17 #include "llvm/Support/raw_os_ostream.h"
18 #include "llvm/Target/TargetInstrInfo.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetSubtargetInfo.h"
24 // Pin the vtable to this file.
25 void MachineRegisterInfo::Delegate::anchor() {}
27 MachineRegisterInfo::MachineRegisterInfo(const MachineFunction *MF)
28 : MF(MF), TheDelegate(nullptr), IsSSA(true), TracksLiveness(true),
29 TracksSubRegLiveness(false) {
30 VRegInfo.reserve(256);
31 RegAllocHints.reserve(256);
32 UsedPhysRegMask.resize(getTargetRegisterInfo()->getNumRegs());
34 // Create the physreg use/def lists.
35 PhysRegUseDefLists.resize(getTargetRegisterInfo()->getNumRegs(), nullptr);
38 /// setRegClass - Set the register class of the specified virtual register.
41 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
42 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
43 VRegInfo[Reg].first = RC;
46 const TargetRegisterClass *
47 MachineRegisterInfo::constrainRegClass(unsigned Reg,
48 const TargetRegisterClass *RC,
49 unsigned MinNumRegs) {
50 const TargetRegisterClass *OldRC = getRegClass(Reg);
53 const TargetRegisterClass *NewRC =
54 getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
55 if (!NewRC || NewRC == OldRC)
57 if (NewRC->getNumRegs() < MinNumRegs)
59 setRegClass(Reg, NewRC);
64 MachineRegisterInfo::recomputeRegClass(unsigned Reg) {
65 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
66 const TargetRegisterClass *OldRC = getRegClass(Reg);
67 const TargetRegisterClass *NewRC =
68 getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC, *MF);
70 // Stop early if there is no room to grow.
74 // Accumulate constraints from all uses.
75 for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
76 // Apply the effect of the given operand to NewRC.
77 MachineInstr *MI = MO.getParent();
78 unsigned OpNo = &MO - &MI->getOperand(0);
79 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
80 getTargetRegisterInfo());
81 if (!NewRC || NewRC == OldRC)
84 setRegClass(Reg, NewRC);
88 /// createVirtualRegister - Create and return a new virtual register in the
89 /// function with the specified register class.
92 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
93 assert(RegClass && "Cannot create register without RegClass!");
94 assert(RegClass->isAllocatable() &&
95 "Virtual register RegClass must be allocatable.");
97 // New virtual register number.
98 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
100 VRegInfo[Reg].first = RegClass;
101 RegAllocHints.grow(Reg);
103 TheDelegate->MRI_NoteNewVirtualRegister(Reg);
107 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
108 void MachineRegisterInfo::clearVirtRegs() {
110 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
111 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
112 if (!VRegInfo[Reg].second)
115 llvm_unreachable("Remaining virtual register operands");
119 for (auto &I : LiveIns)
123 void MachineRegisterInfo::verifyUseList(unsigned Reg) const {
126 for (MachineOperand &M : reg_operands(Reg)) {
127 MachineOperand *MO = &M;
128 MachineInstr *MI = MO->getParent();
130 errs() << PrintReg(Reg, getTargetRegisterInfo())
131 << " use list MachineOperand " << MO
132 << " has no parent instruction.\n";
136 MachineOperand *MO0 = &MI->getOperand(0);
137 unsigned NumOps = MI->getNumOperands();
138 if (!(MO >= MO0 && MO < MO0+NumOps)) {
139 errs() << PrintReg(Reg, getTargetRegisterInfo())
140 << " use list MachineOperand " << MO
141 << " doesn't belong to parent MI: " << *MI;
145 errs() << PrintReg(Reg, getTargetRegisterInfo())
146 << " MachineOperand " << MO << ": " << *MO
147 << " is not a register\n";
150 if (MO->getReg() != Reg) {
151 errs() << PrintReg(Reg, getTargetRegisterInfo())
152 << " use-list MachineOperand " << MO << ": "
153 << *MO << " is the wrong register\n";
157 assert(Valid && "Invalid use list");
161 void MachineRegisterInfo::verifyUseLists() const {
163 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
164 verifyUseList(TargetRegisterInfo::index2VirtReg(i));
165 for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
170 /// Add MO to the linked list of operands for its register.
171 void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
172 assert(!MO->isOnRegUseList() && "Already on list");
173 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
174 MachineOperand *const Head = HeadRef;
176 // Head points to the first list element.
177 // Next is NULL on the last list element.
178 // Prev pointers are circular, so Head->Prev == Last.
180 // Head is NULL for an empty list.
182 MO->Contents.Reg.Prev = MO;
183 MO->Contents.Reg.Next = nullptr;
187 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
189 // Insert MO between Last and Head in the circular Prev chain.
190 MachineOperand *Last = Head->Contents.Reg.Prev;
191 assert(Last && "Inconsistent use list");
192 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
193 Head->Contents.Reg.Prev = MO;
194 MO->Contents.Reg.Prev = Last;
196 // Def operands always precede uses. This allows def_iterator to stop early.
197 // Insert def operands at the front, and use operands at the back.
199 // Insert def at the front.
200 MO->Contents.Reg.Next = Head;
203 // Insert use at the end.
204 MO->Contents.Reg.Next = nullptr;
205 Last->Contents.Reg.Next = MO;
209 /// Remove MO from its use-def list.
210 void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
211 assert(MO->isOnRegUseList() && "Operand not on use list");
212 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
213 MachineOperand *const Head = HeadRef;
214 assert(Head && "List already empty");
216 // Unlink this from the doubly linked list of operands.
217 MachineOperand *Next = MO->Contents.Reg.Next;
218 MachineOperand *Prev = MO->Contents.Reg.Prev;
220 // Prev links are circular, next link is NULL instead of looping back to Head.
224 Prev->Contents.Reg.Next = Next;
226 (Next ? Next : Head)->Contents.Reg.Prev = Prev;
228 MO->Contents.Reg.Prev = nullptr;
229 MO->Contents.Reg.Next = nullptr;
232 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
234 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
235 /// operands that won't be destroyed, which is OK because the MO destructor is
238 /// The Src and Dst ranges may overlap.
239 void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
242 assert(Src != Dst && NumOps && "Noop moveOperands");
244 // Copy backwards if Dst is within the Src range.
246 if (Dst >= Src && Dst < Src + NumOps) {
252 // Copy one operand at a time.
254 new (Dst) MachineOperand(*Src);
256 // Dst takes Src's place in the use-def chain.
258 MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
259 MachineOperand *Prev = Src->Contents.Reg.Prev;
260 MachineOperand *Next = Src->Contents.Reg.Next;
261 assert(Head && "List empty, but operand is chained");
262 assert(Prev && "Operand was not on use-def list");
264 // Prev links are circular, next link is NULL instead of looping back to
269 Prev->Contents.Reg.Next = Dst;
271 // Update Prev pointer. This also works when Src was pointing to itself
272 // in a 1-element list. In that case Head == Dst.
273 (Next ? Next : Head)->Contents.Reg.Prev = Dst;
281 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
282 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
283 /// except that it also changes any definitions of the register as well.
284 /// If ToReg is a physical register we apply the sub register to obtain the
285 /// final/proper physical register.
286 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
287 assert(FromReg != ToReg && "Cannot replace a reg with itself");
289 const TargetRegisterInfo *TRI = getTargetRegisterInfo();
291 // TODO: This could be more efficient by bulk changing the operands.
292 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
293 MachineOperand &O = *I;
295 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
296 O.substPhysReg(ToReg, *TRI);
303 /// getVRegDef - Return the machine instr that defines the specified virtual
304 /// register or null if none is found. This assumes that the code is in SSA
305 /// form, so there should only be one definition.
306 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
307 // Since we are in SSA form, we can use the first definition.
308 def_instr_iterator I = def_instr_begin(Reg);
309 assert((I.atEnd() || std::next(I) == def_instr_end()) &&
310 "getVRegDef assumes a single definition or no definition");
311 return !I.atEnd() ? &*I : nullptr;
314 /// getUniqueVRegDef - Return the unique machine instr that defines the
315 /// specified virtual register or null if none is found. If there are
316 /// multiple definitions or no definition, return null.
317 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const {
318 if (def_empty(Reg)) return nullptr;
319 def_instr_iterator I = def_instr_begin(Reg);
320 if (std::next(I) != def_instr_end())
325 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
326 use_nodbg_iterator UI = use_nodbg_begin(RegNo);
327 if (UI == use_nodbg_end())
329 return ++UI == use_nodbg_end();
332 /// clearKillFlags - Iterate over all the uses of the given register and
333 /// clear the kill flag from the MachineOperand. This function is used by
334 /// optimization passes which extend register lifetimes and need only
335 /// preserve conservative kill flag information.
336 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
337 for (MachineOperand &MO : use_operands(Reg))
341 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
342 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
343 if (I->first == Reg || I->second == Reg)
348 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
349 /// corresponding live-in physical register.
350 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
351 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
352 if (I->second == VReg)
357 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
358 /// corresponding live-in physical register.
359 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
360 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
361 if (I->first == PReg)
366 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
367 /// into the given entry block.
369 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
370 const TargetRegisterInfo &TRI,
371 const TargetInstrInfo &TII) {
372 // Emit the copies into the top of the block.
373 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
374 if (LiveIns[i].second) {
375 if (use_empty(LiveIns[i].second)) {
376 // The livein has no uses. Drop it.
378 // It would be preferable to have isel avoid creating live-in
379 // records for unused arguments in the first place, but it's
380 // complicated by the debug info code for arguments.
381 LiveIns.erase(LiveIns.begin() + i);
385 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
386 TII.get(TargetOpcode::COPY), LiveIns[i].second)
387 .addReg(LiveIns[i].first);
389 // Add the register to the entry block live-in set.
390 EntryMBB->addLiveIn(LiveIns[i].first);
393 // Add the register to the entry block live-in set.
394 EntryMBB->addLiveIn(LiveIns[i].first);
398 unsigned MachineRegisterInfo::getMaxLaneMaskForVReg(unsigned Reg) const
400 // Lane masks are only defined for vregs.
401 assert(TargetRegisterInfo::isVirtualRegister(Reg));
402 const TargetRegisterClass &TRC = *getRegClass(Reg);
403 return TRC.getLaneMask();
407 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
408 for (MachineInstr &I : use_instructions(Reg))
413 void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
414 ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
415 assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
416 "Invalid ReservedRegs vector from target");
419 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
420 const MachineFunction &MF) const {
421 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
423 // Check if any overlapping register is modified, or allocatable so it may be
425 for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true);
427 if (!def_empty(*AI) || isAllocatable(*AI))
432 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
433 /// specified register as undefined which causes the DBG_VALUE to be
434 /// deleted during LiveDebugVariables analysis.
435 void MachineRegisterInfo::markUsesInDebugValueAsUndef(unsigned Reg) const {
436 // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.)
437 MachineRegisterInfo::use_instr_iterator nextI;
438 for (use_instr_iterator I = use_instr_begin(Reg), E = use_instr_end();
440 nextI = std::next(I); // I is invalidated by the setReg
441 MachineInstr *UseMI = &*I;
442 if (UseMI->isDebugValue())
443 UseMI->getOperand(0).setReg(0U);
447 static const Function *getCalledFunction(const MachineInstr &MI) {
448 for (const MachineOperand &MO : MI.operands()) {
451 const Function *Func = dyn_cast<Function>(MO.getGlobal());
458 static bool isNoReturnDef(const MachineOperand &MO) {
459 // Anything which is not a noreturn function is a real def.
460 const MachineInstr &MI = *MO.getParent();
463 const MachineBasicBlock &MBB = *MI.getParent();
464 if (!MBB.succ_empty())
466 const MachineFunction &MF = *MBB.getParent();
467 // We need to keep correct unwind information even if the function will
468 // not return, since the runtime may need it.
469 if (MF.getFunction()->hasFnAttribute(Attribute::UWTable))
471 const Function *Called = getCalledFunction(MI);
472 if (Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn)
473 || !Called->hasFnAttribute(Attribute::NoUnwind))
479 bool MachineRegisterInfo::isPhysRegModified(unsigned PhysReg) const {
480 if (UsedPhysRegMask.test(PhysReg))
482 const TargetRegisterInfo *TRI = getTargetRegisterInfo();
483 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
484 for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
485 if (isNoReturnDef(MO))