1 //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implementation of the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineRegisterInfo.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/Support/raw_os_ostream.h"
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "llvm/Target/TargetMachine.h"
22 // Pin the vtable to this file.
23 void MachineRegisterInfo::Delegate::anchor() {}
25 MachineRegisterInfo::MachineRegisterInfo(const TargetMachine &TM)
26 : TM(TM), TheDelegate(0), IsSSA(true), TracksLiveness(true) {
27 VRegInfo.reserve(256);
28 RegAllocHints.reserve(256);
29 UsedRegUnits.resize(getTargetRegisterInfo()->getNumRegUnits());
30 UsedPhysRegMask.resize(getTargetRegisterInfo()->getNumRegs());
32 // Create the physreg use/def lists.
34 new MachineOperand*[getTargetRegisterInfo()->getNumRegs()];
35 memset(PhysRegUseDefLists, 0,
36 sizeof(MachineOperand*)*getTargetRegisterInfo()->getNumRegs());
39 MachineRegisterInfo::~MachineRegisterInfo() {
40 delete [] PhysRegUseDefLists;
43 /// setRegClass - Set the register class of the specified virtual register.
46 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
47 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
48 VRegInfo[Reg].first = RC;
51 const TargetRegisterClass *
52 MachineRegisterInfo::constrainRegClass(unsigned Reg,
53 const TargetRegisterClass *RC,
54 unsigned MinNumRegs) {
55 const TargetRegisterClass *OldRC = getRegClass(Reg);
58 const TargetRegisterClass *NewRC =
59 getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
60 if (!NewRC || NewRC == OldRC)
62 if (NewRC->getNumRegs() < MinNumRegs)
64 setRegClass(Reg, NewRC);
69 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
70 const TargetInstrInfo *TII = TM.getInstrInfo();
71 const TargetRegisterClass *OldRC = getRegClass(Reg);
72 const TargetRegisterClass *NewRC =
73 getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC);
75 // Stop early if there is no room to grow.
79 // Accumulate constraints from all uses.
80 for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
81 // Apply the effect of the given operand to NewRC.
82 MachineInstr *MI = MO.getParent();
83 unsigned OpNo = &MO - &MI->getOperand(0);
84 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
85 getTargetRegisterInfo());
86 if (!NewRC || NewRC == OldRC)
89 setRegClass(Reg, NewRC);
93 /// createVirtualRegister - Create and return a new virtual register in the
94 /// function with the specified register class.
97 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
98 assert(RegClass && "Cannot create register without RegClass!");
99 assert(RegClass->isAllocatable() &&
100 "Virtual register RegClass must be allocatable.");
102 // New virtual register number.
103 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
105 VRegInfo[Reg].first = RegClass;
106 RegAllocHints.grow(Reg);
108 TheDelegate->MRI_NoteNewVirtualRegister(Reg);
112 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
113 void MachineRegisterInfo::clearVirtRegs() {
115 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
116 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
117 if (!VRegInfo[Reg].second)
120 llvm_unreachable("Remaining virtual register operands");
126 void MachineRegisterInfo::verifyUseList(unsigned Reg) const {
129 for (MachineOperand &M : reg_operands(Reg)) {
130 MachineOperand *MO = &M;
131 MachineInstr *MI = MO->getParent();
133 errs() << PrintReg(Reg, getTargetRegisterInfo())
134 << " use list MachineOperand " << MO
135 << " has no parent instruction.\n";
138 MachineOperand *MO0 = &MI->getOperand(0);
139 unsigned NumOps = MI->getNumOperands();
140 if (!(MO >= MO0 && MO < MO0+NumOps)) {
141 errs() << PrintReg(Reg, getTargetRegisterInfo())
142 << " use list MachineOperand " << MO
143 << " doesn't belong to parent MI: " << *MI;
147 errs() << PrintReg(Reg, getTargetRegisterInfo())
148 << " MachineOperand " << MO << ": " << *MO
149 << " is not a register\n";
152 if (MO->getReg() != Reg) {
153 errs() << PrintReg(Reg, getTargetRegisterInfo())
154 << " use-list MachineOperand " << MO << ": "
155 << *MO << " is the wrong register\n";
159 assert(Valid && "Invalid use list");
163 void MachineRegisterInfo::verifyUseLists() const {
165 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
166 verifyUseList(TargetRegisterInfo::index2VirtReg(i));
167 for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
172 /// Add MO to the linked list of operands for its register.
173 void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
174 assert(!MO->isOnRegUseList() && "Already on list");
175 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
176 MachineOperand *const Head = HeadRef;
178 // Head points to the first list element.
179 // Next is NULL on the last list element.
180 // Prev pointers are circular, so Head->Prev == Last.
182 // Head is NULL for an empty list.
184 MO->Contents.Reg.Prev = MO;
185 MO->Contents.Reg.Next = 0;
189 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
191 // Insert MO between Last and Head in the circular Prev chain.
192 MachineOperand *Last = Head->Contents.Reg.Prev;
193 assert(Last && "Inconsistent use list");
194 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
195 Head->Contents.Reg.Prev = MO;
196 MO->Contents.Reg.Prev = Last;
198 // Def operands always precede uses. This allows def_iterator to stop early.
199 // Insert def operands at the front, and use operands at the back.
201 // Insert def at the front.
202 MO->Contents.Reg.Next = Head;
205 // Insert use at the end.
206 MO->Contents.Reg.Next = 0;
207 Last->Contents.Reg.Next = MO;
211 /// Remove MO from its use-def list.
212 void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
213 assert(MO->isOnRegUseList() && "Operand not on use list");
214 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
215 MachineOperand *const Head = HeadRef;
216 assert(Head && "List already empty");
218 // Unlink this from the doubly linked list of operands.
219 MachineOperand *Next = MO->Contents.Reg.Next;
220 MachineOperand *Prev = MO->Contents.Reg.Prev;
222 // Prev links are circular, next link is NULL instead of looping back to Head.
226 Prev->Contents.Reg.Next = Next;
228 (Next ? Next : Head)->Contents.Reg.Prev = Prev;
230 MO->Contents.Reg.Prev = 0;
231 MO->Contents.Reg.Next = 0;
234 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
236 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
237 /// operands that won't be destroyed, which is OK because the MO destructor is
240 /// The Src and Dst ranges may overlap.
241 void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
244 assert(Src != Dst && NumOps && "Noop moveOperands");
246 // Copy backwards if Dst is within the Src range.
248 if (Dst >= Src && Dst < Src + NumOps) {
254 // Copy one operand at a time.
256 new (Dst) MachineOperand(*Src);
258 // Dst takes Src's place in the use-def chain.
260 MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
261 MachineOperand *Prev = Src->Contents.Reg.Prev;
262 MachineOperand *Next = Src->Contents.Reg.Next;
263 assert(Head && "List empty, but operand is chained");
264 assert(Prev && "Operand was not on use-def list");
266 // Prev links are circular, next link is NULL instead of looping back to
271 Prev->Contents.Reg.Next = Dst;
273 // Update Prev pointer. This also works when Src was pointing to itself
274 // in a 1-element list. In that case Head == Dst.
275 (Next ? Next : Head)->Contents.Reg.Prev = Dst;
283 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
284 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
285 /// except that it also changes any definitions of the register as well.
286 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
287 assert(FromReg != ToReg && "Cannot replace a reg with itself");
289 // TODO: This could be more efficient by bulk changing the operands.
290 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
291 MachineOperand &O = *I;
298 /// getVRegDef - Return the machine instr that defines the specified virtual
299 /// register or null if none is found. This assumes that the code is in SSA
300 /// form, so there should only be one definition.
301 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
302 // Since we are in SSA form, we can use the first definition.
303 def_instr_iterator I = def_instr_begin(Reg);
304 assert((I.atEnd() || std::next(I) == def_instr_end()) &&
305 "getVRegDef assumes a single definition or no definition");
306 return !I.atEnd() ? &*I : 0;
309 /// getUniqueVRegDef - Return the unique machine instr that defines the
310 /// specified virtual register or null if none is found. If there are
311 /// multiple definitions or no definition, return null.
312 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const {
313 if (def_empty(Reg)) return 0;
314 def_instr_iterator I = def_instr_begin(Reg);
315 if (std::next(I) != def_instr_end())
320 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
321 use_nodbg_iterator UI = use_nodbg_begin(RegNo);
322 if (UI == use_nodbg_end())
324 return ++UI == use_nodbg_end();
327 /// clearKillFlags - Iterate over all the uses of the given register and
328 /// clear the kill flag from the MachineOperand. This function is used by
329 /// optimization passes which extend register lifetimes and need only
330 /// preserve conservative kill flag information.
331 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
332 for (MachineOperand &MO : use_operands(Reg))
336 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
337 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
338 if (I->first == Reg || I->second == Reg)
343 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
344 /// corresponding live-in physical register.
345 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
346 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
347 if (I->second == VReg)
352 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
353 /// corresponding live-in physical register.
354 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
355 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
356 if (I->first == PReg)
361 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
362 /// into the given entry block.
364 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
365 const TargetRegisterInfo &TRI,
366 const TargetInstrInfo &TII) {
367 // Emit the copies into the top of the block.
368 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
369 if (LiveIns[i].second) {
370 if (use_empty(LiveIns[i].second)) {
371 // The livein has no uses. Drop it.
373 // It would be preferable to have isel avoid creating live-in
374 // records for unused arguments in the first place, but it's
375 // complicated by the debug info code for arguments.
376 LiveIns.erase(LiveIns.begin() + i);
380 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
381 TII.get(TargetOpcode::COPY), LiveIns[i].second)
382 .addReg(LiveIns[i].first);
384 // Add the register to the entry block live-in set.
385 EntryMBB->addLiveIn(LiveIns[i].first);
388 // Add the register to the entry block live-in set.
389 EntryMBB->addLiveIn(LiveIns[i].first);
394 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
395 for (MachineInstr &I : use_instructions(Reg))
400 void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
401 ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
402 assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
403 "Invalid ReservedRegs vector from target");
406 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
407 const MachineFunction &MF) const {
408 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
410 // Check if any overlapping register is modified, or allocatable so it may be
412 for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true);
414 if (!def_empty(*AI) || isAllocatable(*AI))
419 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
420 /// specified register as undefined which causes the DBG_VALUE to be
421 /// deleted during LiveDebugVariables analysis.
422 void MachineRegisterInfo::markUsesInDebugValueAsUndef(unsigned Reg) const {
423 // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.)
424 MachineRegisterInfo::use_instr_iterator nextI;
425 for (use_instr_iterator I = use_instr_begin(Reg), E = use_instr_end();
427 nextI = std::next(I); // I is invalidated by the setReg
428 MachineInstr *UseMI = &*I;
429 if (UseMI->isDebugValue())
430 UseMI->getOperand(0).setReg(0U);