1 //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implementation of the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineRegisterInfo.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Support/CommandLine.h"
20 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
21 VRegInfo.reserve(256);
22 RegAllocHints.reserve(256);
23 RegClass2VRegMap.resize(TRI.getNumRegClasses()+1); // RC ID starts at 1.
24 UsedPhysRegs.resize(TRI.getNumRegs());
26 // Create the physreg use/def lists.
27 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
28 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
31 MachineRegisterInfo::~MachineRegisterInfo() {
33 for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i)
34 assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?");
35 for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
36 assert(!PhysRegUseDefLists[i] &&
37 "PhysRegUseDefLists has entries after all instructions are deleted");
39 delete [] PhysRegUseDefLists;
42 /// setRegClass - Set the register class of the specified virtual register.
45 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
47 Reg -= TargetRegisterInfo::FirstVirtualRegister;
48 assert(Reg < VRegInfo.size() && "Invalid vreg!");
49 const TargetRegisterClass *OldRC = VRegInfo[Reg].first;
50 VRegInfo[Reg].first = RC;
52 // Remove from old register class's vregs list. This may be slow but
53 // fortunately this operation is rarely needed.
54 std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()];
55 std::vector<unsigned>::iterator I=std::find(VRegs.begin(), VRegs.end(), VR);
58 // Add to new register class's vregs list.
59 RegClass2VRegMap[RC->getID()].push_back(VR);
62 /// createVirtualRegister - Create and return a new virtual register in the
63 /// function with the specified register class.
66 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
67 assert(RegClass && "Cannot create register without RegClass!");
68 // Add a reg, but keep track of whether the vector reallocated or not.
69 void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
70 VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
71 RegAllocHints.push_back(std::make_pair(0, 0));
73 if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)))
74 // The vector reallocated, handle this now.
75 HandleVRegListReallocation();
76 unsigned VR = getLastVirtReg();
77 RegClass2VRegMap[RegClass->getID()].push_back(VR);
81 /// HandleVRegListReallocation - We just added a virtual register to the
82 /// VRegInfo info list and it reallocated. Update the use/def lists info
84 void MachineRegisterInfo::HandleVRegListReallocation() {
85 // The back pointers for the vreg lists point into the previous vector.
86 // Update them to point to their correct slots.
87 for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) {
88 MachineOperand *List = VRegInfo[i].second;
90 // Update the back-pointer to be accurate once more.
91 List->Contents.Reg.Prev = &VRegInfo[i].second;
95 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
96 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
97 /// except that it also changes any definitions of the register as well.
98 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
99 assert(FromReg != ToReg && "Cannot replace a reg with itself");
101 // TODO: This could be more efficient by bulk changing the operands.
102 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
103 MachineOperand &O = I.getOperand();
110 /// getVRegDef - Return the machine instr that defines the specified virtual
111 /// register or null if none is found. This assumes that the code is in SSA
112 /// form, so there should only be one definition.
113 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
114 assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
116 // Since we are in SSA form, we can use the first definition.
118 return &*def_begin(Reg);
122 bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const {
123 use_iterator UI = use_begin(RegNo);
126 return ++UI == use_end();
129 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
130 use_nodbg_iterator UI = use_nodbg_begin(RegNo);
131 if (UI == use_nodbg_end())
133 return ++UI == use_nodbg_end();
136 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
137 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
138 if (I->first == Reg || I->second == Reg)
143 bool MachineRegisterInfo::isLiveOut(unsigned Reg) const {
144 for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
150 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
151 /// corresponding live-in physical register.
152 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
153 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
154 if (I->second == VReg)
160 SchedLiveInCopies("schedule-livein-copies", cl::Hidden,
161 cl::desc("Schedule copies of livein registers"),
164 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
165 /// physical register has only a single copy use, then coalesced the copy
167 static void EmitLiveInCopy(MachineBasicBlock *MBB,
168 MachineBasicBlock::iterator &InsertPos,
169 unsigned VirtReg, unsigned PhysReg,
170 const TargetRegisterClass *RC,
171 DenseMap<MachineInstr*, unsigned> &CopyRegMap,
172 const MachineRegisterInfo &MRI,
173 const TargetRegisterInfo &TRI,
174 const TargetInstrInfo &TII) {
175 unsigned NumUses = 0;
176 MachineInstr *UseMI = NULL;
177 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
178 UE = MRI.use_end(); UI != UE; ++UI) {
184 // If the number of uses is not one, or the use is not a move instruction,
185 // don't coalesce. Also, only coalesce away a virtual register to virtual
187 bool Coalesced = false;
188 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
190 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
191 TargetRegisterInfo::isVirtualRegister(DstReg)) {
196 // Now find an ideal location to insert the copy.
197 MachineBasicBlock::iterator Pos = InsertPos;
198 while (Pos != MBB->begin()) {
199 MachineInstr *PrevMI = prior(Pos);
200 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
201 // copyRegToReg might emit multiple instructions to do a copy.
202 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
203 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
204 // This is what the BB looks like right now:
209 // We want to insert "r1025 = mov r1". Inserting this copy below the
210 // move to r1024 makes it impossible for that move to be coalesced.
217 break; // Woot! Found a good location.
221 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
222 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
225 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
227 if (&*InsertPos == UseMI) ++InsertPos;
232 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
233 /// into the given entry block.
235 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
236 const TargetRegisterInfo &TRI,
237 const TargetInstrInfo &TII) {
238 if (SchedLiveInCopies) {
239 // Emit the copies at a heuristically-determined location in the block.
240 DenseMap<MachineInstr*, unsigned> CopyRegMap;
241 MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
242 for (MachineRegisterInfo::livein_iterator LI = livein_begin(),
243 E = livein_end(); LI != E; ++LI)
245 const TargetRegisterClass *RC = getRegClass(LI->second);
246 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
247 RC, CopyRegMap, *this, TRI, TII);
250 // Emit the copies into the top of the block.
251 for (MachineRegisterInfo::livein_iterator LI = livein_begin(),
252 E = livein_end(); LI != E; ++LI)
254 const TargetRegisterClass *RC = getRegClass(LI->second);
255 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
256 LI->second, LI->first, RC, RC);
257 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
262 // Add function live-ins to entry block live-in set.
263 for (MachineRegisterInfo::livein_iterator I = livein_begin(),
264 E = livein_end(); I != E; ++I)
265 EntryMBB->addLiveIn(I->first);
269 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
270 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
271 I.getOperand().getParent()->dump();