1 //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implementation of the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineRegisterInfo.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Support/CommandLine.h"
20 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
21 VRegInfo.reserve(256);
22 RegAllocHints.reserve(256);
23 RegClass2VRegMap.resize(TRI.getNumRegClasses()+1); // RC ID starts at 1.
24 UsedPhysRegs.resize(TRI.getNumRegs());
26 // Create the physreg use/def lists.
27 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
28 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
31 MachineRegisterInfo::~MachineRegisterInfo() {
33 for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i)
34 assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?");
35 for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
36 assert(!PhysRegUseDefLists[i] &&
37 "PhysRegUseDefLists has entries after all instructions are deleted");
39 delete [] PhysRegUseDefLists;
42 /// setRegClass - Set the register class of the specified virtual register.
45 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
47 Reg -= TargetRegisterInfo::FirstVirtualRegister;
48 assert(Reg < VRegInfo.size() && "Invalid vreg!");
49 const TargetRegisterClass *OldRC = VRegInfo[Reg].first;
50 VRegInfo[Reg].first = RC;
52 // Remove from old register class's vregs list. This may be slow but
53 // fortunately this operation is rarely needed.
54 std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()];
55 std::vector<unsigned>::iterator I=std::find(VRegs.begin(), VRegs.end(), VR);
58 // Add to new register class's vregs list.
59 RegClass2VRegMap[RC->getID()].push_back(VR);
62 /// createVirtualRegister - Create and return a new virtual register in the
63 /// function with the specified register class.
66 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
67 assert(RegClass && "Cannot create register without RegClass!");
68 // Add a reg, but keep track of whether the vector reallocated or not.
69 void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
70 VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
71 RegAllocHints.push_back(std::make_pair(0, 0));
73 if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)))
74 // The vector reallocated, handle this now.
75 HandleVRegListReallocation();
76 unsigned VR = getLastVirtReg();
77 RegClass2VRegMap[RegClass->getID()].push_back(VR);
81 /// HandleVRegListReallocation - We just added a virtual register to the
82 /// VRegInfo info list and it reallocated. Update the use/def lists info
84 void MachineRegisterInfo::HandleVRegListReallocation() {
85 // The back pointers for the vreg lists point into the previous vector.
86 // Update them to point to their correct slots.
87 for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) {
88 MachineOperand *List = VRegInfo[i].second;
90 // Update the back-pointer to be accurate once more.
91 List->Contents.Reg.Prev = &VRegInfo[i].second;
95 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
96 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
97 /// except that it also changes any definitions of the register as well.
98 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
99 assert(FromReg != ToReg && "Cannot replace a reg with itself");
101 // TODO: This could be more efficient by bulk changing the operands.
102 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
103 MachineOperand &O = I.getOperand();
110 /// getVRegDef - Return the machine instr that defines the specified virtual
111 /// register or null if none is found. This assumes that the code is in SSA
112 /// form, so there should only be one definition.
113 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
114 assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
116 // Since we are in SSA form, we can use the first definition.
118 return &*def_begin(Reg);
122 bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const {
123 use_iterator UI = use_begin(RegNo);
126 return ++UI == use_end();
129 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
130 use_nodbg_iterator UI = use_nodbg_begin(RegNo);
131 if (UI == use_nodbg_end())
133 return ++UI == use_nodbg_end();
136 /// clearKillFlags - Iterate over all the uses of the given register and
137 /// clear the kill flag from the MachineOperand. This function is used by
138 /// optimization passes which extend register lifetimes and need only
139 /// preserve conservative kill flag information.
140 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
141 for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
142 UI.getOperand().setIsKill(false);
145 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
146 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
147 if (I->first == Reg || I->second == Reg)
152 bool MachineRegisterInfo::isLiveOut(unsigned Reg) const {
153 for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
159 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
160 /// corresponding live-in physical register.
161 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
162 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
163 if (I->second == VReg)
168 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
169 /// corresponding live-in physical register.
170 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
171 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
172 if (I->first == PReg)
178 SchedLiveInCopies("schedule-livein-copies", cl::Hidden,
179 cl::desc("Schedule copies of livein registers"),
182 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
183 /// physical register has only a single copy use, then coalesced the copy
185 static void EmitLiveInCopy(MachineBasicBlock *MBB,
186 MachineBasicBlock::iterator &InsertPos,
187 unsigned VirtReg, unsigned PhysReg,
188 const TargetRegisterClass *RC,
189 DenseMap<MachineInstr*, unsigned> &CopyRegMap,
190 const MachineRegisterInfo &MRI,
191 const TargetRegisterInfo &TRI,
192 const TargetInstrInfo &TII) {
193 unsigned NumUses = 0;
194 MachineInstr *UseMI = NULL;
195 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
196 UE = MRI.use_end(); UI != UE; ++UI) {
202 // If the number of uses is not one, or the use is not a move instruction,
203 // don't coalesce. Also, only coalesce away a virtual register to virtual
205 bool Coalesced = false;
206 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
208 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
209 TargetRegisterInfo::isVirtualRegister(DstReg)) {
214 // Now find an ideal location to insert the copy.
215 MachineBasicBlock::iterator Pos = InsertPos;
216 while (Pos != MBB->begin()) {
217 MachineInstr *PrevMI = prior(Pos);
218 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
219 // copyRegToReg might emit multiple instructions to do a copy.
220 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
221 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
222 // This is what the BB looks like right now:
227 // We want to insert "r1025 = mov r1". Inserting this copy below the
228 // move to r1024 makes it impossible for that move to be coalesced.
235 break; // Woot! Found a good location.
239 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC,
241 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
244 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
246 if (&*InsertPos == UseMI) ++InsertPos;
251 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
252 /// into the given entry block.
254 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
255 const TargetRegisterInfo &TRI,
256 const TargetInstrInfo &TII) {
257 if (SchedLiveInCopies) {
258 // Emit the copies at a heuristically-determined location in the block.
259 DenseMap<MachineInstr*, unsigned> CopyRegMap;
260 MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
261 for (MachineRegisterInfo::livein_iterator LI = livein_begin(),
262 E = livein_end(); LI != E; ++LI)
264 const TargetRegisterClass *RC = getRegClass(LI->second);
265 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
266 RC, CopyRegMap, *this, TRI, TII);
269 // Emit the copies into the top of the block.
270 for (MachineRegisterInfo::livein_iterator LI = livein_begin(),
271 E = livein_end(); LI != E; ++LI)
273 const TargetRegisterClass *RC = getRegClass(LI->second);
274 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
275 LI->second, LI->first, RC, RC,
277 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
282 // Add function live-ins to entry block live-in set.
283 for (MachineRegisterInfo::livein_iterator I = livein_begin(),
284 E = livein_end(); I != E; ++I)
285 EntryMBB->addLiveIn(I->first);
288 void MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) {
289 for (int i = UsedPhysRegs.find_first(); i >= 0;
290 i = UsedPhysRegs.find_next(i))
291 for (const unsigned *SS = TRI.getSubRegisters(i);
292 unsigned SubReg = *SS; ++SS)
293 if (SubReg > unsigned(i))
294 UsedPhysRegs.set(SubReg);
298 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
299 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
300 I.getOperand().getParent()->dump();