1 //===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MachineScheduler schedules machine instructions after phi elimination. It
11 // preserves LiveIntervals so it can be invoked before register allocation.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "misched"
17 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
18 #include "llvm/CodeGen/MachineScheduler.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/CodeGen/RegisterClassInfo.h"
21 #include "llvm/CodeGen/RegisterPressure.h"
22 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
23 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/MC/MCInstrItineraries.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/ADT/OwningPtr.h"
32 #include "llvm/ADT/PriorityQueue.h"
38 static cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
39 cl::desc("Force top-down list scheduling"));
40 static cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
41 cl::desc("Force bottom-up list scheduling"));
44 static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden,
45 cl::desc("Pop up a window to show MISched dags after they are processed"));
47 static cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden,
48 cl::desc("Stop scheduling after N instructions"), cl::init(~0U));
50 static bool ViewMISchedDAGs = false;
53 //===----------------------------------------------------------------------===//
54 // Machine Instruction Scheduling Pass and Registry
55 //===----------------------------------------------------------------------===//
57 MachineSchedContext::MachineSchedContext():
58 MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {
59 RegClassInfo = new RegisterClassInfo();
62 MachineSchedContext::~MachineSchedContext() {
67 /// MachineScheduler runs after coalescing and before register allocation.
68 class MachineScheduler : public MachineSchedContext,
69 public MachineFunctionPass {
73 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
75 virtual void releaseMemory() {}
77 virtual bool runOnMachineFunction(MachineFunction&);
79 virtual void print(raw_ostream &O, const Module* = 0) const;
81 static char ID; // Class identification, replacement for typeinfo
85 char MachineScheduler::ID = 0;
87 char &llvm::MachineSchedulerID = MachineScheduler::ID;
89 INITIALIZE_PASS_BEGIN(MachineScheduler, "misched",
90 "Machine Instruction Scheduler", false, false)
91 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
92 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
93 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
94 INITIALIZE_PASS_END(MachineScheduler, "misched",
95 "Machine Instruction Scheduler", false, false)
97 MachineScheduler::MachineScheduler()
98 : MachineFunctionPass(ID) {
99 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
102 void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
103 AU.setPreservesCFG();
104 AU.addRequiredID(MachineDominatorsID);
105 AU.addRequired<MachineLoopInfo>();
106 AU.addRequired<AliasAnalysis>();
107 AU.addRequired<TargetPassConfig>();
108 AU.addRequired<SlotIndexes>();
109 AU.addPreserved<SlotIndexes>();
110 AU.addRequired<LiveIntervals>();
111 AU.addPreserved<LiveIntervals>();
112 MachineFunctionPass::getAnalysisUsage(AU);
115 MachinePassRegistry MachineSchedRegistry::Registry;
117 /// A dummy default scheduler factory indicates whether the scheduler
118 /// is overridden on the command line.
119 static ScheduleDAGInstrs *useDefaultMachineSched(MachineSchedContext *C) {
123 /// MachineSchedOpt allows command line selection of the scheduler.
124 static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
125 RegisterPassParser<MachineSchedRegistry> >
126 MachineSchedOpt("misched",
127 cl::init(&useDefaultMachineSched), cl::Hidden,
128 cl::desc("Machine instruction scheduler to use"));
130 static MachineSchedRegistry
131 DefaultSchedRegistry("default", "Use the target's default scheduler choice.",
132 useDefaultMachineSched);
134 /// Forward declare the standard machine scheduler. This will be used as the
135 /// default scheduler if the target does not set a default.
136 static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C);
139 /// Decrement this iterator until reaching the top or a non-debug instr.
140 static MachineBasicBlock::iterator
141 priorNonDebug(MachineBasicBlock::iterator I, MachineBasicBlock::iterator Beg) {
142 assert(I != Beg && "reached the top of the region, cannot decrement");
144 if (!I->isDebugValue())
150 /// If this iterator is a debug value, increment until reaching the End or a
151 /// non-debug instruction.
152 static MachineBasicBlock::iterator
153 nextIfDebug(MachineBasicBlock::iterator I, MachineBasicBlock::iterator End) {
154 for(; I != End; ++I) {
155 if (!I->isDebugValue())
161 /// Top-level MachineScheduler pass driver.
163 /// Visit blocks in function order. Divide each block into scheduling regions
164 /// and visit them bottom-up. Visiting regions bottom-up is not required, but is
165 /// consistent with the DAG builder, which traverses the interior of the
166 /// scheduling regions bottom-up.
168 /// This design avoids exposing scheduling boundaries to the DAG builder,
169 /// simplifying the DAG builder's support for "special" target instructions.
170 /// At the same time the design allows target schedulers to operate across
171 /// scheduling boundaries, for example to bundle the boudary instructions
172 /// without reordering them. This creates complexity, because the target
173 /// scheduler must update the RegionBegin and RegionEnd positions cached by
174 /// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler
175 /// design would be to split blocks at scheduling boundaries, but LLVM has a
176 /// general bias against block splitting purely for implementation simplicity.
177 bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
178 DEBUG(dbgs() << "Before MISsched:\n"; mf.print(dbgs()));
180 // Initialize the context of the pass.
182 MLI = &getAnalysis<MachineLoopInfo>();
183 MDT = &getAnalysis<MachineDominatorTree>();
184 PassConfig = &getAnalysis<TargetPassConfig>();
185 AA = &getAnalysis<AliasAnalysis>();
187 LIS = &getAnalysis<LiveIntervals>();
188 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
190 RegClassInfo->runOnMachineFunction(*MF);
192 // Select the scheduler, or set the default.
193 MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
194 if (Ctor == useDefaultMachineSched) {
195 // Get the default scheduler set by the target.
196 Ctor = MachineSchedRegistry::getDefault();
198 Ctor = createConvergingSched;
199 MachineSchedRegistry::setDefault(Ctor);
202 // Instantiate the selected scheduler.
203 OwningPtr<ScheduleDAGInstrs> Scheduler(Ctor(this));
205 // Visit all machine basic blocks.
207 // TODO: Visit blocks in global postorder or postorder within the bottom-up
208 // loop tree. Then we can optionally compute global RegPressure.
209 for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
210 MBB != MBBEnd; ++MBB) {
212 Scheduler->startBlock(MBB);
214 // Break the block into scheduling regions [I, RegionEnd), and schedule each
215 // region as soon as it is discovered. RegionEnd points the the scheduling
216 // boundary at the bottom of the region. The DAG does not include RegionEnd,
217 // but the region does (i.e. the next RegionEnd is above the previous
218 // RegionBegin). If the current block has no terminator then RegionEnd ==
219 // MBB->end() for the bottom region.
221 // The Scheduler may insert instructions during either schedule() or
222 // exitRegion(), even for empty regions. So the local iterators 'I' and
223 // 'RegionEnd' are invalid across these calls.
224 unsigned RemainingCount = MBB->size();
225 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
226 RegionEnd != MBB->begin(); RegionEnd = Scheduler->begin()) {
228 // Avoid decrementing RegionEnd for blocks with no terminator.
229 if (RegionEnd != MBB->end()
230 || TII->isSchedulingBoundary(llvm::prior(RegionEnd), MBB, *MF)) {
232 // Count the boundary instruction.
236 // The next region starts above the previous region. Look backward in the
237 // instruction stream until we find the nearest boundary.
238 MachineBasicBlock::iterator I = RegionEnd;
239 for(;I != MBB->begin(); --I, --RemainingCount) {
240 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, *MF))
243 // Notify the scheduler of the region, even if we may skip scheduling
244 // it. Perhaps it still needs to be bundled.
245 Scheduler->enterRegion(MBB, I, RegionEnd, RemainingCount);
247 // Skip empty scheduling regions (0 or 1 schedulable instructions).
248 if (I == RegionEnd || I == llvm::prior(RegionEnd)) {
249 // Close the current region. Bundle the terminator if needed.
250 // This invalidates 'RegionEnd' and 'I'.
251 Scheduler->exitRegion();
254 DEBUG(dbgs() << "********** MI Scheduling **********\n");
255 DEBUG(dbgs() << MF->getFunction()->getName()
256 << ":BB#" << MBB->getNumber() << "\n From: " << *I << " To: ";
257 if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
258 else dbgs() << "End";
259 dbgs() << " Remaining: " << RemainingCount << "\n");
261 // Schedule a region: possibly reorder instructions.
262 // This invalidates 'RegionEnd' and 'I'.
263 Scheduler->schedule();
265 // Close the current region.
266 Scheduler->exitRegion();
268 // Scheduling has invalidated the current iterator 'I'. Ask the
269 // scheduler for the top of it's scheduled region.
270 RegionEnd = Scheduler->begin();
272 assert(RemainingCount == 0 && "Instruction count mismatch!");
273 Scheduler->finishBlock();
275 Scheduler->finalizeSchedule();
276 DEBUG(LIS->print(dbgs()));
280 void MachineScheduler::print(raw_ostream &O, const Module* m) const {
284 //===----------------------------------------------------------------------===//
285 // MachineSchedStrategy - Interface to a machine scheduling algorithm.
286 //===----------------------------------------------------------------------===//
291 /// MachineSchedStrategy - Interface used by ScheduleDAGMI to drive the selected
292 /// scheduling algorithm.
294 /// If this works well and targets wish to reuse ScheduleDAGMI, we may expose it
295 /// in ScheduleDAGInstrs.h
296 class MachineSchedStrategy {
298 virtual ~MachineSchedStrategy() {}
300 /// Initialize the strategy after building the DAG for a new region.
301 virtual void initialize(ScheduleDAGMI *DAG) = 0;
303 /// Pick the next node to schedule, or return NULL. Set IsTopNode to true to
304 /// schedule the node at the top of the unscheduled region. Otherwise it will
305 /// be scheduled at the bottom.
306 virtual SUnit *pickNode(bool &IsTopNode) = 0;
308 /// Notify MachineSchedStrategy that ScheduleDAGMI has scheduled a node.
309 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
311 /// When all predecessor dependencies have been resolved, free this node for
312 /// top-down scheduling.
313 virtual void releaseTopNode(SUnit *SU) = 0;
314 /// When all successor dependencies have been resolved, free this node for
315 /// bottom-up scheduling.
316 virtual void releaseBottomNode(SUnit *SU) = 0;
320 //===----------------------------------------------------------------------===//
321 // ScheduleDAGMI - Base class for MachineInstr scheduling with LiveIntervals
323 //===----------------------------------------------------------------------===//
326 /// ScheduleDAGMI is an implementation of ScheduleDAGInstrs that schedules
327 /// machine instructions while updating LiveIntervals.
328 class ScheduleDAGMI : public ScheduleDAGInstrs {
330 RegisterClassInfo *RegClassInfo;
331 MachineSchedStrategy *SchedImpl;
333 MachineBasicBlock::iterator LiveRegionEnd;
335 /// Register pressure in this region computed by buildSchedGraph.
336 IntervalPressure RegPressure;
337 RegPressureTracker RPTracker;
339 /// List of pressure sets that exceed the target's pressure limit before
340 /// scheduling, listed in increasing set ID order. Each pressure set is paired
341 /// with its max pressure in the currently scheduled regions.
342 std::vector<PressureElement> RegionCriticalPSets;
344 /// The top of the unscheduled zone.
345 MachineBasicBlock::iterator CurrentTop;
346 IntervalPressure TopPressure;
347 RegPressureTracker TopRPTracker;
349 /// The bottom of the unscheduled zone.
350 MachineBasicBlock::iterator CurrentBottom;
351 IntervalPressure BotPressure;
352 RegPressureTracker BotRPTracker;
355 /// The number of instructions scheduled so far. Used to cut off the
356 /// scheduler at the point determined by misched-cutoff.
357 unsigned NumInstrsScheduled;
360 ScheduleDAGMI(MachineSchedContext *C, MachineSchedStrategy *S):
361 ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
362 AA(C->AA), RegClassInfo(C->RegClassInfo), SchedImpl(S),
363 RPTracker(RegPressure), CurrentTop(), TopRPTracker(TopPressure),
364 CurrentBottom(), BotRPTracker(BotPressure) {
366 NumInstrsScheduled = 0;
374 MachineBasicBlock::iterator top() const { return CurrentTop; }
375 MachineBasicBlock::iterator bottom() const { return CurrentBottom; }
377 /// Implement the ScheduleDAGInstrs interface for handling the next scheduling
378 /// region. This covers all instructions in a block, while schedule() may only
380 void enterRegion(MachineBasicBlock *bb,
381 MachineBasicBlock::iterator begin,
382 MachineBasicBlock::iterator end,
385 /// Implement ScheduleDAGInstrs interface for scheduling a sequence of
386 /// reorderable instructions.
389 /// Get current register pressure for the top scheduled instructions.
390 const IntervalPressure &getTopPressure() const { return TopPressure; }
391 const RegPressureTracker &getTopRPTracker() const { return TopRPTracker; }
393 /// Get current register pressure for the bottom scheduled instructions.
394 const IntervalPressure &getBotPressure() const { return BotPressure; }
395 const RegPressureTracker &getBotRPTracker() const { return BotRPTracker; }
397 /// Get register pressure for the entire scheduling region before scheduling.
398 const IntervalPressure &getRegPressure() const { return RegPressure; }
400 const std::vector<PressureElement> &getRegionCriticalPSets() const {
401 return RegionCriticalPSets;
404 /// getIssueWidth - Return the max instructions per scheduling group.
405 unsigned getIssueWidth() const {
406 return InstrItins ? InstrItins->Props.IssueWidth : 1;
409 /// getNumMicroOps - Return the number of issue slots required for this MI.
410 unsigned getNumMicroOps(MachineInstr *MI) const {
411 int UOps = InstrItins->getNumMicroOps(MI->getDesc().getSchedClass());
412 return (UOps >= 0) ? UOps : TII->getNumMicroOps(InstrItins, MI);
416 void initRegPressure();
417 void updateScheduledPressure(std::vector<unsigned> NewMaxPressure);
419 void moveInstruction(MachineInstr *MI, MachineBasicBlock::iterator InsertPos);
420 bool checkSchedLimit();
424 void releaseSucc(SUnit *SU, SDep *SuccEdge);
425 void releaseSuccessors(SUnit *SU);
426 void releasePred(SUnit *SU, SDep *PredEdge);
427 void releasePredecessors(SUnit *SU);
429 void placeDebugValues();
433 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
434 /// NumPredsLeft reaches zero, release the successor node.
436 /// FIXME: Adjust SuccSU height based on MinLatency.
437 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
438 SUnit *SuccSU = SuccEdge->getSUnit();
441 if (SuccSU->NumPredsLeft == 0) {
442 dbgs() << "*** Scheduling failed! ***\n";
444 dbgs() << " has been released too many times!\n";
448 --SuccSU->NumPredsLeft;
449 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
450 SchedImpl->releaseTopNode(SuccSU);
453 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
454 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
455 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
457 releaseSucc(SU, &*I);
461 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. When
462 /// NumSuccsLeft reaches zero, release the predecessor node.
464 /// FIXME: Adjust PredSU height based on MinLatency.
465 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
466 SUnit *PredSU = PredEdge->getSUnit();
469 if (PredSU->NumSuccsLeft == 0) {
470 dbgs() << "*** Scheduling failed! ***\n";
472 dbgs() << " has been released too many times!\n";
476 --PredSU->NumSuccsLeft;
477 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU)
478 SchedImpl->releaseBottomNode(PredSU);
481 /// releasePredecessors - Call releasePred on each of SU's predecessors.
482 void ScheduleDAGMI::releasePredecessors(SUnit *SU) {
483 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
485 releasePred(SU, &*I);
489 void ScheduleDAGMI::moveInstruction(MachineInstr *MI,
490 MachineBasicBlock::iterator InsertPos) {
491 // Advance RegionBegin if the first instruction moves down.
492 if (&*RegionBegin == MI)
495 // Update the instruction stream.
496 BB->splice(InsertPos, BB, MI);
498 // Update LiveIntervals
501 // Recede RegionBegin if an instruction moves above the first.
502 if (RegionBegin == InsertPos)
506 bool ScheduleDAGMI::checkSchedLimit() {
508 if (NumInstrsScheduled == MISchedCutoff && MISchedCutoff != ~0U) {
509 CurrentTop = CurrentBottom;
512 ++NumInstrsScheduled;
517 /// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
518 /// crossing a scheduling boundary. [begin, end) includes all instructions in
519 /// the region, including the boundary itself and single-instruction regions
520 /// that don't get scheduled.
521 void ScheduleDAGMI::enterRegion(MachineBasicBlock *bb,
522 MachineBasicBlock::iterator begin,
523 MachineBasicBlock::iterator end,
526 ScheduleDAGInstrs::enterRegion(bb, begin, end, endcount);
528 // For convenience remember the end of the liveness region.
530 (RegionEnd == bb->end()) ? RegionEnd : llvm::next(RegionEnd);
533 // Setup the register pressure trackers for the top scheduled top and bottom
534 // scheduled regions.
535 void ScheduleDAGMI::initRegPressure() {
536 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin);
537 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
539 // Close the RPTracker to finalize live ins.
540 RPTracker.closeRegion();
542 DEBUG(RPTracker.getPressure().dump(TRI));
544 // Initialize the live ins and live outs.
545 TopRPTracker.addLiveRegs(RPTracker.getPressure().LiveInRegs);
546 BotRPTracker.addLiveRegs(RPTracker.getPressure().LiveOutRegs);
548 // Close one end of the tracker so we can call
549 // getMaxUpward/DownwardPressureDelta before advancing across any
550 // instructions. This converts currently live regs into live ins/outs.
551 TopRPTracker.closeTop();
552 BotRPTracker.closeBottom();
554 // Account for liveness generated by the region boundary.
555 if (LiveRegionEnd != RegionEnd)
556 BotRPTracker.recede();
558 assert(BotRPTracker.getPos() == RegionEnd && "Can't find the region bottom");
560 // Cache the list of excess pressure sets in this region. This will also track
561 // the max pressure in the scheduled code for these sets.
562 RegionCriticalPSets.clear();
563 std::vector<unsigned> RegionPressure = RPTracker.getPressure().MaxSetPressure;
564 for (unsigned i = 0, e = RegionPressure.size(); i < e; ++i) {
565 unsigned Limit = TRI->getRegPressureSetLimit(i);
566 if (RegionPressure[i] > Limit)
567 RegionCriticalPSets.push_back(PressureElement(i, 0));
569 DEBUG(dbgs() << "Excess PSets: ";
570 for (unsigned i = 0, e = RegionCriticalPSets.size(); i != e; ++i)
571 dbgs() << TRI->getRegPressureSetName(
572 RegionCriticalPSets[i].PSetID) << " ";
576 // FIXME: When the pressure tracker deals in pressure differences then we won't
577 // iterate over all RegionCriticalPSets[i].
579 updateScheduledPressure(std::vector<unsigned> NewMaxPressure) {
580 for (unsigned i = 0, e = RegionCriticalPSets.size(); i < e; ++i) {
581 unsigned ID = RegionCriticalPSets[i].PSetID;
582 int &MaxUnits = RegionCriticalPSets[i].UnitIncrease;
583 if ((int)NewMaxPressure[ID] > MaxUnits)
584 MaxUnits = NewMaxPressure[ID];
588 // Release all DAG roots for scheduling.
589 void ScheduleDAGMI::releaseRoots() {
590 SmallVector<SUnit*, 16> BotRoots;
592 for (std::vector<SUnit>::iterator
593 I = SUnits.begin(), E = SUnits.end(); I != E; ++I) {
594 // A SUnit is ready to top schedule if it has no predecessors.
595 if (I->Preds.empty())
596 SchedImpl->releaseTopNode(&(*I));
597 // A SUnit is ready to bottom schedule if it has no successors.
598 if (I->Succs.empty())
599 BotRoots.push_back(&(*I));
601 // Release bottom roots in reverse order so the higher priority nodes appear
602 // first. This is more natural and slightly more efficient.
603 for (SmallVectorImpl<SUnit*>::const_reverse_iterator
604 I = BotRoots.rbegin(), E = BotRoots.rend(); I != E; ++I)
605 SchedImpl->releaseBottomNode(*I);
608 /// schedule - Called back from MachineScheduler::runOnMachineFunction
609 /// after setting up the current scheduling region. [RegionBegin, RegionEnd)
610 /// only includes instructions that have DAG nodes, not scheduling boundaries.
611 void ScheduleDAGMI::schedule() {
612 // Initialize the register pressure tracker used by buildSchedGraph.
613 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
615 // Account for liveness generate by the region boundary.
616 if (LiveRegionEnd != RegionEnd)
619 // Build the DAG, and compute current register pressure.
620 buildSchedGraph(AA, &RPTracker);
622 // Initialize top/bottom trackers after computing region pressure.
625 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
626 SUnits[su].dumpAll(this));
628 if (ViewMISchedDAGs) viewGraph();
630 SchedImpl->initialize(this);
632 // Release edges from the special Entry node or to the special Exit node.
633 releaseSuccessors(&EntrySU);
634 releasePredecessors(&ExitSU);
636 // Release all DAG roots for scheduling.
639 CurrentTop = nextIfDebug(RegionBegin, RegionEnd);
640 CurrentBottom = RegionEnd;
641 bool IsTopNode = false;
642 while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) {
643 if (!checkSchedLimit())
646 // Move the instruction to its new location in the instruction stream.
647 MachineInstr *MI = SU->getInstr();
650 assert(SU->isTopReady() && "node still has unscheduled dependencies");
651 if (&*CurrentTop == MI)
652 CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);
654 moveInstruction(MI, CurrentTop);
655 TopRPTracker.setPos(MI);
658 // Update top scheduled pressure.
659 TopRPTracker.advance();
660 assert(TopRPTracker.getPos() == CurrentTop && "out of sync");
661 updateScheduledPressure(TopRPTracker.getPressure().MaxSetPressure);
663 // Release dependent instructions for scheduling.
664 releaseSuccessors(SU);
667 assert(SU->isBottomReady() && "node still has unscheduled dependencies");
668 MachineBasicBlock::iterator priorII =
669 priorNonDebug(CurrentBottom, CurrentTop);
671 CurrentBottom = priorII;
673 if (&*CurrentTop == MI) {
674 CurrentTop = nextIfDebug(++CurrentTop, priorII);
675 TopRPTracker.setPos(CurrentTop);
677 moveInstruction(MI, CurrentBottom);
680 // Update bottom scheduled pressure.
681 BotRPTracker.recede();
682 assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
683 updateScheduledPressure(BotRPTracker.getPressure().MaxSetPressure);
685 // Release dependent instructions for scheduling.
686 releasePredecessors(SU);
688 SU->isScheduled = true;
689 SchedImpl->schedNode(SU, IsTopNode);
691 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
696 /// Reinsert any remaining debug_values, just like the PostRA scheduler.
697 void ScheduleDAGMI::placeDebugValues() {
698 // If first instruction was a DBG_VALUE then put it back.
700 BB->splice(RegionBegin, BB, FirstDbgValue);
701 RegionBegin = FirstDbgValue;
704 for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
705 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
706 std::pair<MachineInstr *, MachineInstr *> P = *prior(DI);
707 MachineInstr *DbgValue = P.first;
708 MachineBasicBlock::iterator OrigPrevMI = P.second;
709 BB->splice(++OrigPrevMI, BB, DbgValue);
710 if (OrigPrevMI == llvm::prior(RegionEnd))
711 RegionEnd = DbgValue;
714 FirstDbgValue = NULL;
717 //===----------------------------------------------------------------------===//
718 // ConvergingScheduler - Implementation of the standard MachineSchedStrategy.
719 //===----------------------------------------------------------------------===//
722 /// ReadyQueue encapsulates vector of "ready" SUnits with basic convenience
723 /// methods for pushing and removing nodes. ReadyQueue's are uniquely identified
724 /// by an ID. SUnit::NodeQueueId is a mask of the ReadyQueues the SUnit is in.
728 std::vector<SUnit*> Queue;
731 ReadyQueue(unsigned id, const Twine &name): ID(id), Name(name.str()) {}
733 unsigned getID() const { return ID; }
735 StringRef getName() const { return Name; }
737 // SU is in this queue if it's NodeQueueID is a superset of this ID.
738 bool isInQueue(SUnit *SU) const { return (SU->NodeQueueId & ID); }
740 bool empty() const { return Queue.empty(); }
742 unsigned size() const { return Queue.size(); }
744 typedef std::vector<SUnit*>::iterator iterator;
746 iterator begin() { return Queue.begin(); }
748 iterator end() { return Queue.end(); }
750 iterator find(SUnit *SU) {
751 return std::find(Queue.begin(), Queue.end(), SU);
754 void push(SUnit *SU) {
756 SU->NodeQueueId |= ID;
759 void remove(iterator I) {
760 (*I)->NodeQueueId &= ~ID;
766 dbgs() << Name << ": ";
767 for (unsigned i = 0, e = Queue.size(); i < e; ++i)
768 dbgs() << Queue[i]->NodeNum << " ";
773 /// ConvergingScheduler shrinks the unscheduled zone using heuristics to balance
775 class ConvergingScheduler : public MachineSchedStrategy {
777 /// Store the state used by ConvergingScheduler heuristics, required for the
778 /// lifetime of one invocation of pickNode().
779 struct SchedCandidate {
780 // The best SUnit candidate.
783 // Register pressure values for the best candidate.
784 RegPressureDelta RPDelta;
786 SchedCandidate(): SU(NULL) {}
788 /// Represent the type of SchedCandidate found within a single queue.
790 NoCand, NodeOrder, SingleExcess, SingleCritical, SingleMax, MultiPressure };
792 /// Each Scheduling boundary is associated with ready queues. It tracks the
793 /// current cycle in whichever direction at has moved, and maintains the state
794 /// of "hazards" and other interlocks at the current cycle.
795 struct SchedBoundary {
798 ReadyQueue Available;
802 ScheduleHazardRecognizer *HazardRec;
807 /// MinReadyCycle - Cycle of the soonest available instruction.
808 unsigned MinReadyCycle;
810 // Remember the greatest min operand latency.
811 unsigned MaxMinLatency;
813 /// Pending queues extend the ready queues with the same ID and the
815 SchedBoundary(unsigned ID, const Twine &Name):
816 DAG(0), Available(ID, Name+".A"),
817 Pending(ID << ConvergingScheduler::LogMaxQID, Name+".P"),
818 CheckPending(false), HazardRec(0), CurrCycle(0), IssueCount(0),
819 MinReadyCycle(UINT_MAX), MaxMinLatency(0) {}
821 ~SchedBoundary() { delete HazardRec; }
824 return Available.getID() == ConvergingScheduler::TopQID;
827 bool checkHazard(SUnit *SU);
829 void releaseNode(SUnit *SU, unsigned ReadyCycle);
833 void bumpNode(SUnit *SU);
835 void releasePending();
837 void removeReady(SUnit *SU);
839 SUnit *pickOnlyChoice();
843 const TargetRegisterInfo *TRI;
845 // State of the top and bottom scheduled instruction boundaries.
850 /// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both)
857 ConvergingScheduler():
858 DAG(0), TRI(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
860 virtual void initialize(ScheduleDAGMI *dag);
862 virtual SUnit *pickNode(bool &IsTopNode);
864 virtual void schedNode(SUnit *SU, bool IsTopNode);
866 virtual void releaseTopNode(SUnit *SU);
868 virtual void releaseBottomNode(SUnit *SU);
871 SUnit *pickNodeBidrectional(bool &IsTopNode);
873 CandResult pickNodeFromQueue(ReadyQueue &Q,
874 const RegPressureTracker &RPTracker,
875 SchedCandidate &Candidate);
877 void traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU,
878 PressureElement P = PressureElement());
883 void ConvergingScheduler::initialize(ScheduleDAGMI *dag) {
889 // Initialize the HazardRecognizers.
890 const TargetMachine &TM = DAG->MF.getTarget();
891 const InstrItineraryData *Itin = TM.getInstrItineraryData();
892 Top.HazardRec = TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
893 Bot.HazardRec = TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
895 assert((!ForceTopDown || !ForceBottomUp) &&
896 "-misched-topdown incompatible with -misched-bottomup");
899 void ConvergingScheduler::releaseTopNode(SUnit *SU) {
903 for (SUnit::succ_iterator I = SU->Preds.begin(), E = SU->Preds.end();
905 unsigned PredReadyCycle = I->getSUnit()->TopReadyCycle;
907 DAG->computeOperandLatency(I->getSUnit(), SU, *I, /*FindMin=*/true);
909 Top.MaxMinLatency = std::max(Latency, Top.MaxMinLatency);
911 if (SU->TopReadyCycle < PredReadyCycle + Latency)
912 SU->TopReadyCycle = PredReadyCycle + Latency;
914 Top.releaseNode(SU, SU->TopReadyCycle);
917 void ConvergingScheduler::releaseBottomNode(SUnit *SU) {
921 assert(SU->getInstr() && "Scheduled SUnit must have instr");
923 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
925 unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle;
927 DAG->computeOperandLatency(SU, I->getSUnit(), *I, /*FindMin=*/true);
929 Bot.MaxMinLatency = std::max(Latency, Bot.MaxMinLatency);
931 if (SU->BotReadyCycle < SuccReadyCycle + Latency)
932 SU->BotReadyCycle = SuccReadyCycle + Latency;
934 Bot.releaseNode(SU, SU->BotReadyCycle);
937 /// Does this SU have a hazard within the current instruction group.
939 /// The scheduler supports two modes of hazard recognition. The first is the
940 /// ScheduleHazardRecognizer API. It is a fully general hazard recognizer that
941 /// supports highly complicated in-order reservation tables
942 /// (ScoreboardHazardRecognizer) and arbitraty target-specific logic.
944 /// The second is a streamlined mechanism that checks for hazards based on
945 /// simple counters that the scheduler itself maintains. It explicitly checks
946 /// for instruction dispatch limitations, including the number of micro-ops that
947 /// can dispatch per cycle.
949 /// TODO: Also check whether the SU must start a new group.
950 bool ConvergingScheduler::SchedBoundary::checkHazard(SUnit *SU) {
951 if (HazardRec->isEnabled())
952 return HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard;
954 if (IssueCount + DAG->getNumMicroOps(SU->getInstr()) > DAG->getIssueWidth())
960 void ConvergingScheduler::SchedBoundary::releaseNode(SUnit *SU,
961 unsigned ReadyCycle) {
962 if (ReadyCycle < MinReadyCycle)
963 MinReadyCycle = ReadyCycle;
965 // Check for interlocks first. For the purpose of other heuristics, an
966 // instruction that cannot issue appears as if it's not in the ReadyQueue.
967 if (ReadyCycle > CurrCycle || checkHazard(SU))
973 /// Move the boundary of scheduled code by one cycle.
974 void ConvergingScheduler::SchedBoundary::bumpCycle() {
975 unsigned Width = DAG->getIssueWidth();
976 IssueCount = (IssueCount <= Width) ? 0 : IssueCount - Width;
978 assert(MinReadyCycle < UINT_MAX && "MinReadyCycle uninitialized");
979 unsigned NextCycle = std::max(CurrCycle + 1, MinReadyCycle);
981 if (!HazardRec->isEnabled()) {
982 // Bypass HazardRec virtual calls.
983 CurrCycle = NextCycle;
986 // Bypass getHazardType calls in case of long latency.
987 for (; CurrCycle != NextCycle; ++CurrCycle) {
989 HazardRec->AdvanceCycle();
991 HazardRec->RecedeCycle();
996 DEBUG(dbgs() << "*** " << Available.getName() << " cycle "
997 << CurrCycle << '\n');
1000 /// Move the boundary of scheduled code by one SUnit.
1001 void ConvergingScheduler::SchedBoundary::bumpNode(SUnit *SU) {
1002 // Update the reservation table.
1003 if (HazardRec->isEnabled()) {
1004 if (!isTop() && SU->isCall) {
1005 // Calls are scheduled with their preceding instructions. For bottom-up
1006 // scheduling, clear the pipeline state before emitting.
1009 HazardRec->EmitInstruction(SU);
1011 // Check the instruction group dispatch limit.
1012 // TODO: Check if this SU must end a dispatch group.
1013 IssueCount += DAG->getNumMicroOps(SU->getInstr());
1014 if (IssueCount >= DAG->getIssueWidth()) {
1015 DEBUG(dbgs() << "*** Max instrs at cycle " << CurrCycle << '\n');
1020 /// Release pending ready nodes in to the available queue. This makes them
1021 /// visible to heuristics.
1022 void ConvergingScheduler::SchedBoundary::releasePending() {
1023 // If the available queue is empty, it is safe to reset MinReadyCycle.
1024 if (Available.empty())
1025 MinReadyCycle = UINT_MAX;
1027 // Check to see if any of the pending instructions are ready to issue. If
1028 // so, add them to the available queue.
1029 for (unsigned i = 0, e = Pending.size(); i != e; ++i) {
1030 SUnit *SU = *(Pending.begin()+i);
1031 unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle;
1033 if (ReadyCycle < MinReadyCycle)
1034 MinReadyCycle = ReadyCycle;
1036 if (ReadyCycle > CurrCycle)
1039 if (checkHazard(SU))
1043 Pending.remove(Pending.begin()+i);
1046 CheckPending = false;
1049 /// Remove SU from the ready set for this boundary.
1050 void ConvergingScheduler::SchedBoundary::removeReady(SUnit *SU) {
1051 if (Available.isInQueue(SU))
1052 Available.remove(Available.find(SU));
1054 assert(Pending.isInQueue(SU) && "bad ready count");
1055 Pending.remove(Pending.find(SU));
1059 /// If this queue only has one ready candidate, return it. As a side effect,
1060 /// advance the cycle until at least one node is ready. If multiple instructions
1061 /// are ready, return NULL.
1062 SUnit *ConvergingScheduler::SchedBoundary::pickOnlyChoice() {
1066 for (unsigned i = 0; Available.empty(); ++i) {
1067 assert(i <= (HazardRec->getMaxLookAhead() + MaxMinLatency) &&
1068 "permanent hazard"); (void)i;
1072 if (Available.size() == 1)
1073 return *Available.begin();
1078 void ConvergingScheduler::traceCandidate(const char *Label, const ReadyQueue &Q,
1079 SUnit *SU, PressureElement P) {
1080 dbgs() << Label << " " << Q.getName() << " ";
1082 dbgs() << TRI->getRegPressureSetName(P.PSetID) << ":" << P.UnitIncrease
1090 /// pickNodeFromQueue helper that returns true if the LHS reg pressure effect is
1091 /// more desirable than RHS from scheduling standpoint.
1092 static bool compareRPDelta(const RegPressureDelta &LHS,
1093 const RegPressureDelta &RHS) {
1094 // Compare each component of pressure in decreasing order of importance
1095 // without checking if any are valid. Invalid PressureElements are assumed to
1096 // have UnitIncrease==0, so are neutral.
1098 // Avoid increasing the max critical pressure in the scheduled region.
1099 if (LHS.Excess.UnitIncrease != RHS.Excess.UnitIncrease)
1100 return LHS.Excess.UnitIncrease < RHS.Excess.UnitIncrease;
1102 // Avoid increasing the max critical pressure in the scheduled region.
1103 if (LHS.CriticalMax.UnitIncrease != RHS.CriticalMax.UnitIncrease)
1104 return LHS.CriticalMax.UnitIncrease < RHS.CriticalMax.UnitIncrease;
1106 // Avoid increasing the max pressure of the entire region.
1107 if (LHS.CurrentMax.UnitIncrease != RHS.CurrentMax.UnitIncrease)
1108 return LHS.CurrentMax.UnitIncrease < RHS.CurrentMax.UnitIncrease;
1113 /// Pick the best candidate from the top queue.
1115 /// TODO: getMaxPressureDelta results can be mostly cached for each SUnit during
1116 /// DAG building. To adjust for the current scheduling location we need to
1117 /// maintain the number of vreg uses remaining to be top-scheduled.
1118 ConvergingScheduler::CandResult ConvergingScheduler::
1119 pickNodeFromQueue(ReadyQueue &Q, const RegPressureTracker &RPTracker,
1120 SchedCandidate &Candidate) {
1123 // getMaxPressureDelta temporarily modifies the tracker.
1124 RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker);
1126 // BestSU remains NULL if no top candidates beat the best existing candidate.
1127 CandResult FoundCandidate = NoCand;
1128 for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
1129 RegPressureDelta RPDelta;
1130 TempTracker.getMaxPressureDelta((*I)->getInstr(), RPDelta,
1131 DAG->getRegionCriticalPSets(),
1132 DAG->getRegPressure().MaxSetPressure);
1134 // Initialize the candidate if needed.
1135 if (!Candidate.SU) {
1137 Candidate.RPDelta = RPDelta;
1138 FoundCandidate = NodeOrder;
1141 // Avoid exceeding the target's limit.
1142 if (RPDelta.Excess.UnitIncrease < Candidate.RPDelta.Excess.UnitIncrease) {
1143 DEBUG(traceCandidate("ECAND", Q, *I, RPDelta.Excess));
1145 Candidate.RPDelta = RPDelta;
1146 FoundCandidate = SingleExcess;
1149 if (RPDelta.Excess.UnitIncrease > Candidate.RPDelta.Excess.UnitIncrease)
1151 if (FoundCandidate == SingleExcess)
1152 FoundCandidate = MultiPressure;
1154 // Avoid increasing the max critical pressure in the scheduled region.
1155 if (RPDelta.CriticalMax.UnitIncrease
1156 < Candidate.RPDelta.CriticalMax.UnitIncrease) {
1157 DEBUG(traceCandidate("PCAND", Q, *I, RPDelta.CriticalMax));
1159 Candidate.RPDelta = RPDelta;
1160 FoundCandidate = SingleCritical;
1163 if (RPDelta.CriticalMax.UnitIncrease
1164 > Candidate.RPDelta.CriticalMax.UnitIncrease)
1166 if (FoundCandidate == SingleCritical)
1167 FoundCandidate = MultiPressure;
1169 // Avoid increasing the max pressure of the entire region.
1170 if (RPDelta.CurrentMax.UnitIncrease
1171 < Candidate.RPDelta.CurrentMax.UnitIncrease) {
1172 DEBUG(traceCandidate("MCAND", Q, *I, RPDelta.CurrentMax));
1174 Candidate.RPDelta = RPDelta;
1175 FoundCandidate = SingleMax;
1178 if (RPDelta.CurrentMax.UnitIncrease
1179 > Candidate.RPDelta.CurrentMax.UnitIncrease)
1181 if (FoundCandidate == SingleMax)
1182 FoundCandidate = MultiPressure;
1184 // Fall through to original instruction order.
1185 // Only consider node order if Candidate was chosen from this Q.
1186 if (FoundCandidate == NoCand)
1189 if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum)
1190 || (Q.getID() == BotQID && (*I)->NodeNum > Candidate.SU->NodeNum)) {
1191 DEBUG(traceCandidate("NCAND", Q, *I));
1193 Candidate.RPDelta = RPDelta;
1194 FoundCandidate = NodeOrder;
1197 return FoundCandidate;
1200 /// Pick the best candidate node from either the top or bottom queue.
1201 SUnit *ConvergingScheduler::pickNodeBidrectional(bool &IsTopNode) {
1202 // Schedule as far as possible in the direction of no choice. This is most
1203 // efficient, but also provides the best heuristics for CriticalPSets.
1204 if (SUnit *SU = Bot.pickOnlyChoice()) {
1208 if (SUnit *SU = Top.pickOnlyChoice()) {
1212 SchedCandidate BotCand;
1213 // Prefer bottom scheduling when heuristics are silent.
1214 CandResult BotResult = pickNodeFromQueue(Bot.Available,
1215 DAG->getBotRPTracker(), BotCand);
1216 assert(BotResult != NoCand && "failed to find the first candidate");
1218 // If either Q has a single candidate that provides the least increase in
1219 // Excess pressure, we can immediately schedule from that Q.
1221 // RegionCriticalPSets summarizes the pressure within the scheduled region and
1222 // affects picking from either Q. If scheduling in one direction must
1223 // increase pressure for one of the excess PSets, then schedule in that
1224 // direction first to provide more freedom in the other direction.
1225 if (BotResult == SingleExcess || BotResult == SingleCritical) {
1229 // Check if the top Q has a better candidate.
1230 SchedCandidate TopCand;
1231 CandResult TopResult = pickNodeFromQueue(Top.Available,
1232 DAG->getTopRPTracker(), TopCand);
1233 assert(TopResult != NoCand && "failed to find the first candidate");
1235 if (TopResult == SingleExcess || TopResult == SingleCritical) {
1239 // If either Q has a single candidate that minimizes pressure above the
1240 // original region's pressure pick it.
1241 if (BotResult == SingleMax) {
1245 if (TopResult == SingleMax) {
1249 // Check for a salient pressure difference and pick the best from either side.
1250 if (compareRPDelta(TopCand.RPDelta, BotCand.RPDelta)) {
1254 // Otherwise prefer the bottom candidate in node order.
1259 /// Pick the best node to balance the schedule. Implements MachineSchedStrategy.
1260 SUnit *ConvergingScheduler::pickNode(bool &IsTopNode) {
1261 if (DAG->top() == DAG->bottom()) {
1262 assert(Top.Available.empty() && Top.Pending.empty() &&
1263 Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage");
1268 SU = Top.pickOnlyChoice();
1270 SchedCandidate TopCand;
1271 CandResult TopResult =
1272 pickNodeFromQueue(Top.Available, DAG->getTopRPTracker(), TopCand);
1273 assert(TopResult != NoCand && "failed to find the first candidate");
1279 else if (ForceBottomUp) {
1280 SU = Bot.pickOnlyChoice();
1282 SchedCandidate BotCand;
1283 CandResult BotResult =
1284 pickNodeFromQueue(Bot.Available, DAG->getBotRPTracker(), BotCand);
1285 assert(BotResult != NoCand && "failed to find the first candidate");
1292 SU = pickNodeBidrectional(IsTopNode);
1294 if (SU->isTopReady())
1295 Top.removeReady(SU);
1296 if (SU->isBottomReady())
1297 Bot.removeReady(SU);
1299 DEBUG(dbgs() << "*** " << (IsTopNode ? "Top" : "Bottom")
1300 << " Scheduling Instruction in cycle "
1301 << (IsTopNode ? Top.CurrCycle : Bot.CurrCycle) << '\n';
1306 /// Update the scheduler's state after scheduling a node. This is the same node
1307 /// that was just returned by pickNode(). However, ScheduleDAGMI needs to update
1308 /// it's state based on the current cycle before MachineSchedStrategy does.
1309 void ConvergingScheduler::schedNode(SUnit *SU, bool IsTopNode) {
1311 SU->TopReadyCycle = Top.CurrCycle;
1315 SU->BotReadyCycle = Bot.CurrCycle;
1320 /// Create the standard converging machine scheduler. This will be used as the
1321 /// default scheduler if the target does not set a default.
1322 static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C) {
1323 assert((!ForceTopDown || !ForceBottomUp) &&
1324 "-misched-topdown incompatible with -misched-bottomup");
1325 return new ScheduleDAGMI(C, new ConvergingScheduler());
1327 static MachineSchedRegistry
1328 ConvergingSchedRegistry("converge", "Standard converging scheduler.",
1329 createConvergingSched);
1331 //===----------------------------------------------------------------------===//
1332 // Machine Instruction Shuffler for Correctness Testing
1333 //===----------------------------------------------------------------------===//
1337 /// Apply a less-than relation on the node order, which corresponds to the
1338 /// instruction order prior to scheduling. IsReverse implements greater-than.
1339 template<bool IsReverse>
1341 bool operator()(SUnit *A, SUnit *B) const {
1343 return A->NodeNum > B->NodeNum;
1345 return A->NodeNum < B->NodeNum;
1349 /// Reorder instructions as much as possible.
1350 class InstructionShuffler : public MachineSchedStrategy {
1354 // Using a less-than relation (SUnitOrder<false>) for the TopQ priority
1355 // gives nodes with a higher number higher priority causing the latest
1356 // instructions to be scheduled first.
1357 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false> >
1359 // When scheduling bottom-up, use greater-than as the queue priority.
1360 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true> >
1363 InstructionShuffler(bool alternate, bool topdown)
1364 : IsAlternating(alternate), IsTopDown(topdown) {}
1366 virtual void initialize(ScheduleDAGMI *) {
1371 /// Implement MachineSchedStrategy interface.
1372 /// -----------------------------------------
1374 virtual SUnit *pickNode(bool &IsTopNode) {
1378 if (TopQ.empty()) return NULL;
1381 } while (SU->isScheduled);
1386 if (BottomQ.empty()) return NULL;
1389 } while (SU->isScheduled);
1393 IsTopDown = !IsTopDown;
1397 virtual void schedNode(SUnit *SU, bool IsTopNode) {}
1399 virtual void releaseTopNode(SUnit *SU) {
1402 virtual void releaseBottomNode(SUnit *SU) {
1408 static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
1409 bool Alternate = !ForceTopDown && !ForceBottomUp;
1410 bool TopDown = !ForceBottomUp;
1411 assert((TopDown || !ForceTopDown) &&
1412 "-misched-topdown incompatible with -misched-bottomup");
1413 return new ScheduleDAGMI(C, new InstructionShuffler(Alternate, TopDown));
1415 static MachineSchedRegistry ShufflerRegistry(
1416 "shuffle", "Shuffle machine instructions alternating directions",
1417 createInstructionShuffler);