1 //===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MachineScheduler schedules machine instructions after phi elimination. It
11 // preserves LiveIntervals so it can be invoked before register allocation.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/MachineScheduler.h"
16 #include "llvm/ADT/PriorityQueue.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/MachineDominators.h"
20 #include "llvm/CodeGen/MachineLoopInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/CodeGen/RegisterClassInfo.h"
24 #include "llvm/CodeGen/ScheduleDFS.h"
25 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/GraphWriter.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/Target/TargetInstrInfo.h"
36 #define DEBUG_TYPE "misched"
39 cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
40 cl::desc("Force top-down list scheduling"));
41 cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
42 cl::desc("Force bottom-up list scheduling"));
44 DumpCriticalPathLength("misched-dcpl", cl::Hidden,
45 cl::desc("Print critical path length to stdout"));
49 static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden,
50 cl::desc("Pop up a window to show MISched dags after they are processed"));
52 static cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden,
53 cl::desc("Stop scheduling after N instructions"), cl::init(~0U));
55 static cl::opt<std::string> SchedOnlyFunc("misched-only-func", cl::Hidden,
56 cl::desc("Only schedule this function"));
57 static cl::opt<unsigned> SchedOnlyBlock("misched-only-block", cl::Hidden,
58 cl::desc("Only schedule this MBB#"));
60 static bool ViewMISchedDAGs = false;
63 static cl::opt<bool> EnableRegPressure("misched-regpressure", cl::Hidden,
64 cl::desc("Enable register pressure scheduling."), cl::init(true));
66 static cl::opt<bool> EnableCyclicPath("misched-cyclicpath", cl::Hidden,
67 cl::desc("Enable cyclic critical path analysis."), cl::init(true));
69 static cl::opt<bool> EnableLoadCluster("misched-cluster", cl::Hidden,
70 cl::desc("Enable load clustering."), cl::init(true));
72 // Experimental heuristics
73 static cl::opt<bool> EnableMacroFusion("misched-fusion", cl::Hidden,
74 cl::desc("Enable scheduling for macro fusion."), cl::init(true));
76 static cl::opt<bool> VerifyScheduling("verify-misched", cl::Hidden,
77 cl::desc("Verify machine instrs before and after machine scheduling"));
79 // DAG subtrees must have at least this many nodes.
80 static const unsigned MinSubtreeSize = 8;
82 // Pin the vtables to this file.
83 void MachineSchedStrategy::anchor() {}
84 void ScheduleDAGMutation::anchor() {}
86 //===----------------------------------------------------------------------===//
87 // Machine Instruction Scheduling Pass and Registry
88 //===----------------------------------------------------------------------===//
90 MachineSchedContext::MachineSchedContext():
91 MF(nullptr), MLI(nullptr), MDT(nullptr), PassConfig(nullptr), AA(nullptr), LIS(nullptr) {
92 RegClassInfo = new RegisterClassInfo();
95 MachineSchedContext::~MachineSchedContext() {
100 /// Base class for a machine scheduler class that can run at any point.
101 class MachineSchedulerBase : public MachineSchedContext,
102 public MachineFunctionPass {
104 MachineSchedulerBase(char &ID): MachineFunctionPass(ID) {}
106 void print(raw_ostream &O, const Module* = nullptr) const override;
109 void scheduleRegions(ScheduleDAGInstrs &Scheduler);
112 /// MachineScheduler runs after coalescing and before register allocation.
113 class MachineScheduler : public MachineSchedulerBase {
117 void getAnalysisUsage(AnalysisUsage &AU) const override;
119 bool runOnMachineFunction(MachineFunction&) override;
121 static char ID; // Class identification, replacement for typeinfo
124 ScheduleDAGInstrs *createMachineScheduler();
127 /// PostMachineScheduler runs after shortly before code emission.
128 class PostMachineScheduler : public MachineSchedulerBase {
130 PostMachineScheduler();
132 void getAnalysisUsage(AnalysisUsage &AU) const override;
134 bool runOnMachineFunction(MachineFunction&) override;
136 static char ID; // Class identification, replacement for typeinfo
139 ScheduleDAGInstrs *createPostMachineScheduler();
143 char MachineScheduler::ID = 0;
145 char &llvm::MachineSchedulerID = MachineScheduler::ID;
147 INITIALIZE_PASS_BEGIN(MachineScheduler, "misched",
148 "Machine Instruction Scheduler", false, false)
149 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
150 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
151 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
152 INITIALIZE_PASS_END(MachineScheduler, "misched",
153 "Machine Instruction Scheduler", false, false)
155 MachineScheduler::MachineScheduler()
156 : MachineSchedulerBase(ID) {
157 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
160 void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
161 AU.setPreservesCFG();
162 AU.addRequiredID(MachineDominatorsID);
163 AU.addRequired<MachineLoopInfo>();
164 AU.addRequired<AliasAnalysis>();
165 AU.addRequired<TargetPassConfig>();
166 AU.addRequired<SlotIndexes>();
167 AU.addPreserved<SlotIndexes>();
168 AU.addRequired<LiveIntervals>();
169 AU.addPreserved<LiveIntervals>();
170 MachineFunctionPass::getAnalysisUsage(AU);
173 char PostMachineScheduler::ID = 0;
175 char &llvm::PostMachineSchedulerID = PostMachineScheduler::ID;
177 INITIALIZE_PASS(PostMachineScheduler, "postmisched",
178 "PostRA Machine Instruction Scheduler", false, false)
180 PostMachineScheduler::PostMachineScheduler()
181 : MachineSchedulerBase(ID) {
182 initializePostMachineSchedulerPass(*PassRegistry::getPassRegistry());
185 void PostMachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
186 AU.setPreservesCFG();
187 AU.addRequiredID(MachineDominatorsID);
188 AU.addRequired<MachineLoopInfo>();
189 AU.addRequired<TargetPassConfig>();
190 MachineFunctionPass::getAnalysisUsage(AU);
193 MachinePassRegistry MachineSchedRegistry::Registry;
195 /// A dummy default scheduler factory indicates whether the scheduler
196 /// is overridden on the command line.
197 static ScheduleDAGInstrs *useDefaultMachineSched(MachineSchedContext *C) {
201 /// MachineSchedOpt allows command line selection of the scheduler.
202 static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
203 RegisterPassParser<MachineSchedRegistry> >
204 MachineSchedOpt("misched",
205 cl::init(&useDefaultMachineSched), cl::Hidden,
206 cl::desc("Machine instruction scheduler to use"));
208 static MachineSchedRegistry
209 DefaultSchedRegistry("default", "Use the target's default scheduler choice.",
210 useDefaultMachineSched);
212 /// Forward declare the standard machine scheduler. This will be used as the
213 /// default scheduler if the target does not set a default.
214 static ScheduleDAGInstrs *createGenericSchedLive(MachineSchedContext *C);
215 static ScheduleDAGInstrs *createGenericSchedPostRA(MachineSchedContext *C);
217 /// Decrement this iterator until reaching the top or a non-debug instr.
218 static MachineBasicBlock::const_iterator
219 priorNonDebug(MachineBasicBlock::const_iterator I,
220 MachineBasicBlock::const_iterator Beg) {
221 assert(I != Beg && "reached the top of the region, cannot decrement");
223 if (!I->isDebugValue())
229 /// Non-const version.
230 static MachineBasicBlock::iterator
231 priorNonDebug(MachineBasicBlock::iterator I,
232 MachineBasicBlock::const_iterator Beg) {
233 return const_cast<MachineInstr*>(
234 &*priorNonDebug(MachineBasicBlock::const_iterator(I), Beg));
237 /// If this iterator is a debug value, increment until reaching the End or a
238 /// non-debug instruction.
239 static MachineBasicBlock::const_iterator
240 nextIfDebug(MachineBasicBlock::const_iterator I,
241 MachineBasicBlock::const_iterator End) {
242 for(; I != End; ++I) {
243 if (!I->isDebugValue())
249 /// Non-const version.
250 static MachineBasicBlock::iterator
251 nextIfDebug(MachineBasicBlock::iterator I,
252 MachineBasicBlock::const_iterator End) {
253 // Cast the return value to nonconst MachineInstr, then cast to an
254 // instr_iterator, which does not check for null, finally return a
256 return MachineBasicBlock::instr_iterator(
257 const_cast<MachineInstr*>(
258 &*nextIfDebug(MachineBasicBlock::const_iterator(I), End)));
261 /// Instantiate a ScheduleDAGInstrs that will be owned by the caller.
262 ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() {
263 // Select the scheduler, or set the default.
264 MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
265 if (Ctor != useDefaultMachineSched)
268 // Get the default scheduler set by the target for this function.
269 ScheduleDAGInstrs *Scheduler = PassConfig->createMachineScheduler(this);
273 // Default to GenericScheduler.
274 return createGenericSchedLive(this);
277 /// Instantiate a ScheduleDAGInstrs for PostRA scheduling that will be owned by
278 /// the caller. We don't have a command line option to override the postRA
279 /// scheduler. The Target must configure it.
280 ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
281 // Get the postRA scheduler set by the target for this function.
282 ScheduleDAGInstrs *Scheduler = PassConfig->createPostMachineScheduler(this);
286 // Default to GenericScheduler.
287 return createGenericSchedPostRA(this);
290 /// Top-level MachineScheduler pass driver.
292 /// Visit blocks in function order. Divide each block into scheduling regions
293 /// and visit them bottom-up. Visiting regions bottom-up is not required, but is
294 /// consistent with the DAG builder, which traverses the interior of the
295 /// scheduling regions bottom-up.
297 /// This design avoids exposing scheduling boundaries to the DAG builder,
298 /// simplifying the DAG builder's support for "special" target instructions.
299 /// At the same time the design allows target schedulers to operate across
300 /// scheduling boundaries, for example to bundle the boudary instructions
301 /// without reordering them. This creates complexity, because the target
302 /// scheduler must update the RegionBegin and RegionEnd positions cached by
303 /// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler
304 /// design would be to split blocks at scheduling boundaries, but LLVM has a
305 /// general bias against block splitting purely for implementation simplicity.
306 bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
307 DEBUG(dbgs() << "Before MISsched:\n"; mf.print(dbgs()));
309 // Initialize the context of the pass.
311 MLI = &getAnalysis<MachineLoopInfo>();
312 MDT = &getAnalysis<MachineDominatorTree>();
313 PassConfig = &getAnalysis<TargetPassConfig>();
314 AA = &getAnalysis<AliasAnalysis>();
316 LIS = &getAnalysis<LiveIntervals>();
318 if (VerifyScheduling) {
320 MF->verify(this, "Before machine scheduling.");
322 RegClassInfo->runOnMachineFunction(*MF);
324 // Instantiate the selected scheduler for this target, function, and
325 // optimization level.
326 std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler());
327 scheduleRegions(*Scheduler);
330 if (VerifyScheduling)
331 MF->verify(this, "After machine scheduling.");
335 bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) {
336 if (skipOptnoneFunction(*mf.getFunction()))
339 const TargetSubtargetInfo &ST =
340 mf.getTarget().getSubtarget<TargetSubtargetInfo>();
341 if (!ST.enablePostMachineScheduler()) {
342 DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n");
345 DEBUG(dbgs() << "Before post-MI-sched:\n"; mf.print(dbgs()));
347 // Initialize the context of the pass.
349 PassConfig = &getAnalysis<TargetPassConfig>();
351 if (VerifyScheduling)
352 MF->verify(this, "Before post machine scheduling.");
354 // Instantiate the selected scheduler for this target, function, and
355 // optimization level.
356 std::unique_ptr<ScheduleDAGInstrs> Scheduler(createPostMachineScheduler());
357 scheduleRegions(*Scheduler);
359 if (VerifyScheduling)
360 MF->verify(this, "After post machine scheduling.");
364 /// Return true of the given instruction should not be included in a scheduling
367 /// MachineScheduler does not currently support scheduling across calls. To
368 /// handle calls, the DAG builder needs to be modified to create register
369 /// anti/output dependencies on the registers clobbered by the call's regmask
370 /// operand. In PreRA scheduling, the stack pointer adjustment already prevents
371 /// scheduling across calls. In PostRA scheduling, we need the isCall to enforce
372 /// the boundary, but there would be no benefit to postRA scheduling across
373 /// calls this late anyway.
374 static bool isSchedBoundary(MachineBasicBlock::iterator MI,
375 MachineBasicBlock *MBB,
377 const TargetInstrInfo *TII,
379 return MI->isCall() || TII->isSchedulingBoundary(MI, MBB, *MF);
382 /// Main driver for both MachineScheduler and PostMachineScheduler.
383 void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler) {
384 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
385 bool IsPostRA = Scheduler.isPostRA();
387 // Visit all machine basic blocks.
389 // TODO: Visit blocks in global postorder or postorder within the bottom-up
390 // loop tree. Then we can optionally compute global RegPressure.
391 for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
392 MBB != MBBEnd; ++MBB) {
394 Scheduler.startBlock(MBB);
397 if (SchedOnlyFunc.getNumOccurrences() && SchedOnlyFunc != MF->getName())
399 if (SchedOnlyBlock.getNumOccurrences()
400 && (int)SchedOnlyBlock != MBB->getNumber())
404 // Break the block into scheduling regions [I, RegionEnd), and schedule each
405 // region as soon as it is discovered. RegionEnd points the scheduling
406 // boundary at the bottom of the region. The DAG does not include RegionEnd,
407 // but the region does (i.e. the next RegionEnd is above the previous
408 // RegionBegin). If the current block has no terminator then RegionEnd ==
409 // MBB->end() for the bottom region.
411 // The Scheduler may insert instructions during either schedule() or
412 // exitRegion(), even for empty regions. So the local iterators 'I' and
413 // 'RegionEnd' are invalid across these calls.
415 // MBB::size() uses instr_iterator to count. Here we need a bundle to count
416 // as a single instruction.
417 unsigned RemainingInstrs = std::distance(MBB->begin(), MBB->end());
418 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
419 RegionEnd != MBB->begin(); RegionEnd = Scheduler.begin()) {
421 // Avoid decrementing RegionEnd for blocks with no terminator.
422 if (RegionEnd != MBB->end() ||
423 isSchedBoundary(std::prev(RegionEnd), MBB, MF, TII, IsPostRA)) {
425 // Count the boundary instruction.
429 // The next region starts above the previous region. Look backward in the
430 // instruction stream until we find the nearest boundary.
431 unsigned NumRegionInstrs = 0;
432 MachineBasicBlock::iterator I = RegionEnd;
433 for(;I != MBB->begin(); --I, --RemainingInstrs, ++NumRegionInstrs) {
434 if (isSchedBoundary(std::prev(I), MBB, MF, TII, IsPostRA))
437 // Notify the scheduler of the region, even if we may skip scheduling
438 // it. Perhaps it still needs to be bundled.
439 Scheduler.enterRegion(MBB, I, RegionEnd, NumRegionInstrs);
441 // Skip empty scheduling regions (0 or 1 schedulable instructions).
442 if (I == RegionEnd || I == std::prev(RegionEnd)) {
443 // Close the current region. Bundle the terminator if needed.
444 // This invalidates 'RegionEnd' and 'I'.
445 Scheduler.exitRegion();
448 DEBUG(dbgs() << "********** " << ((Scheduler.isPostRA()) ? "PostRA " : "")
449 << "MI Scheduling **********\n");
450 DEBUG(dbgs() << MF->getName()
451 << ":BB#" << MBB->getNumber() << " " << MBB->getName()
452 << "\n From: " << *I << " To: ";
453 if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
454 else dbgs() << "End";
455 dbgs() << " RegionInstrs: " << NumRegionInstrs
456 << " Remaining: " << RemainingInstrs << "\n");
457 if (DumpCriticalPathLength) {
458 errs() << MF->getName();
459 errs() << ":BB# " << MBB->getNumber();
460 errs() << " " << MBB->getName() << " \n";
463 // Schedule a region: possibly reorder instructions.
464 // This invalidates 'RegionEnd' and 'I'.
465 Scheduler.schedule();
467 // Close the current region.
468 Scheduler.exitRegion();
470 // Scheduling has invalidated the current iterator 'I'. Ask the
471 // scheduler for the top of it's scheduled region.
472 RegionEnd = Scheduler.begin();
474 assert(RemainingInstrs == 0 && "Instruction count mismatch!");
475 Scheduler.finishBlock();
476 if (Scheduler.isPostRA()) {
477 // FIXME: Ideally, no further passes should rely on kill flags. However,
478 // thumb2 size reduction is currently an exception.
479 Scheduler.fixupKills(MBB);
482 Scheduler.finalizeSchedule();
485 void MachineSchedulerBase::print(raw_ostream &O, const Module* m) const {
490 void ReadyQueue::dump() {
491 dbgs() << Name << ": ";
492 for (unsigned i = 0, e = Queue.size(); i < e; ++i)
493 dbgs() << Queue[i]->NodeNum << " ";
497 //===----------------------------------------------------------------------===//
498 // ScheduleDAGMI - Basic machine instruction scheduling. This is
499 // independent of PreRA/PostRA scheduling and involves no extra book-keeping for
500 // virtual registers.
501 // ===----------------------------------------------------------------------===/
503 // Provide a vtable anchor.
504 ScheduleDAGMI::~ScheduleDAGMI() {
507 bool ScheduleDAGMI::canAddEdge(SUnit *SuccSU, SUnit *PredSU) {
508 return SuccSU == &ExitSU || !Topo.IsReachable(PredSU, SuccSU);
511 bool ScheduleDAGMI::addEdge(SUnit *SuccSU, const SDep &PredDep) {
512 if (SuccSU != &ExitSU) {
513 // Do not use WillCreateCycle, it assumes SD scheduling.
514 // If Pred is reachable from Succ, then the edge creates a cycle.
515 if (Topo.IsReachable(PredDep.getSUnit(), SuccSU))
517 Topo.AddPred(SuccSU, PredDep.getSUnit());
519 SuccSU->addPred(PredDep, /*Required=*/!PredDep.isArtificial());
520 // Return true regardless of whether a new edge needed to be inserted.
524 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
525 /// NumPredsLeft reaches zero, release the successor node.
527 /// FIXME: Adjust SuccSU height based on MinLatency.
528 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
529 SUnit *SuccSU = SuccEdge->getSUnit();
531 if (SuccEdge->isWeak()) {
532 --SuccSU->WeakPredsLeft;
533 if (SuccEdge->isCluster())
534 NextClusterSucc = SuccSU;
538 if (SuccSU->NumPredsLeft == 0) {
539 dbgs() << "*** Scheduling failed! ***\n";
541 dbgs() << " has been released too many times!\n";
542 llvm_unreachable(nullptr);
545 // SU->TopReadyCycle was set to CurrCycle when it was scheduled. However,
546 // CurrCycle may have advanced since then.
547 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency())
548 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency();
550 --SuccSU->NumPredsLeft;
551 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
552 SchedImpl->releaseTopNode(SuccSU);
555 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
556 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
557 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
559 releaseSucc(SU, &*I);
563 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. When
564 /// NumSuccsLeft reaches zero, release the predecessor node.
566 /// FIXME: Adjust PredSU height based on MinLatency.
567 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
568 SUnit *PredSU = PredEdge->getSUnit();
570 if (PredEdge->isWeak()) {
571 --PredSU->WeakSuccsLeft;
572 if (PredEdge->isCluster())
573 NextClusterPred = PredSU;
577 if (PredSU->NumSuccsLeft == 0) {
578 dbgs() << "*** Scheduling failed! ***\n";
580 dbgs() << " has been released too many times!\n";
581 llvm_unreachable(nullptr);
584 // SU->BotReadyCycle was set to CurrCycle when it was scheduled. However,
585 // CurrCycle may have advanced since then.
586 if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency())
587 PredSU->BotReadyCycle = SU->BotReadyCycle + PredEdge->getLatency();
589 --PredSU->NumSuccsLeft;
590 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU)
591 SchedImpl->releaseBottomNode(PredSU);
594 /// releasePredecessors - Call releasePred on each of SU's predecessors.
595 void ScheduleDAGMI::releasePredecessors(SUnit *SU) {
596 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
598 releasePred(SU, &*I);
602 /// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
603 /// crossing a scheduling boundary. [begin, end) includes all instructions in
604 /// the region, including the boundary itself and single-instruction regions
605 /// that don't get scheduled.
606 void ScheduleDAGMI::enterRegion(MachineBasicBlock *bb,
607 MachineBasicBlock::iterator begin,
608 MachineBasicBlock::iterator end,
609 unsigned regioninstrs)
611 ScheduleDAGInstrs::enterRegion(bb, begin, end, regioninstrs);
613 SchedImpl->initPolicy(begin, end, regioninstrs);
616 /// This is normally called from the main scheduler loop but may also be invoked
617 /// by the scheduling strategy to perform additional code motion.
618 void ScheduleDAGMI::moveInstruction(
619 MachineInstr *MI, MachineBasicBlock::iterator InsertPos) {
620 // Advance RegionBegin if the first instruction moves down.
621 if (&*RegionBegin == MI)
624 // Update the instruction stream.
625 BB->splice(InsertPos, BB, MI);
627 // Update LiveIntervals
629 LIS->handleMove(MI, /*UpdateFlags=*/true);
631 // Recede RegionBegin if an instruction moves above the first.
632 if (RegionBegin == InsertPos)
636 bool ScheduleDAGMI::checkSchedLimit() {
638 if (NumInstrsScheduled == MISchedCutoff && MISchedCutoff != ~0U) {
639 CurrentTop = CurrentBottom;
642 ++NumInstrsScheduled;
647 /// Per-region scheduling driver, called back from
648 /// MachineScheduler::runOnMachineFunction. This is a simplified driver that
649 /// does not consider liveness or register pressure. It is useful for PostRA
650 /// scheduling and potentially other custom schedulers.
651 void ScheduleDAGMI::schedule() {
655 Topo.InitDAGTopologicalSorting();
659 SmallVector<SUnit*, 8> TopRoots, BotRoots;
660 findRootsAndBiasEdges(TopRoots, BotRoots);
662 // Initialize the strategy before modifying the DAG.
663 // This may initialize a DFSResult to be used for queue priority.
664 SchedImpl->initialize(this);
666 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
667 SUnits[su].dumpAll(this));
668 if (ViewMISchedDAGs) viewGraph();
670 // Initialize ready queues now that the DAG and priority data are finalized.
671 initQueues(TopRoots, BotRoots);
673 bool IsTopNode = false;
674 while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) {
675 assert(!SU->isScheduled && "Node already scheduled");
676 if (!checkSchedLimit())
679 MachineInstr *MI = SU->getInstr();
681 assert(SU->isTopReady() && "node still has unscheduled dependencies");
682 if (&*CurrentTop == MI)
683 CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);
685 moveInstruction(MI, CurrentTop);
688 assert(SU->isBottomReady() && "node still has unscheduled dependencies");
689 MachineBasicBlock::iterator priorII =
690 priorNonDebug(CurrentBottom, CurrentTop);
692 CurrentBottom = priorII;
694 if (&*CurrentTop == MI)
695 CurrentTop = nextIfDebug(++CurrentTop, priorII);
696 moveInstruction(MI, CurrentBottom);
700 // Notify the scheduling strategy before updating the DAG.
701 // This sets the scheduled node's ReadyCycle to CurrCycle. When updateQueues
702 // runs, it can then use the accurate ReadyCycle time to determine whether
703 // newly released nodes can move to the readyQ.
704 SchedImpl->schedNode(SU, IsTopNode);
706 updateQueues(SU, IsTopNode);
708 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
713 unsigned BBNum = begin()->getParent()->getNumber();
714 dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
720 /// Apply each ScheduleDAGMutation step in order.
721 void ScheduleDAGMI::postprocessDAG() {
722 for (unsigned i = 0, e = Mutations.size(); i < e; ++i) {
723 Mutations[i]->apply(this);
728 findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots,
729 SmallVectorImpl<SUnit*> &BotRoots) {
730 for (std::vector<SUnit>::iterator
731 I = SUnits.begin(), E = SUnits.end(); I != E; ++I) {
733 assert(!SU->isBoundaryNode() && "Boundary node should not be in SUnits");
735 // Order predecessors so DFSResult follows the critical path.
736 SU->biasCriticalPath();
738 // A SUnit is ready to top schedule if it has no predecessors.
739 if (!I->NumPredsLeft)
740 TopRoots.push_back(SU);
741 // A SUnit is ready to bottom schedule if it has no successors.
742 if (!I->NumSuccsLeft)
743 BotRoots.push_back(SU);
745 ExitSU.biasCriticalPath();
748 /// Identify DAG roots and setup scheduler queues.
749 void ScheduleDAGMI::initQueues(ArrayRef<SUnit*> TopRoots,
750 ArrayRef<SUnit*> BotRoots) {
751 NextClusterSucc = nullptr;
752 NextClusterPred = nullptr;
754 // Release all DAG roots for scheduling, not including EntrySU/ExitSU.
756 // Nodes with unreleased weak edges can still be roots.
757 // Release top roots in forward order.
758 for (SmallVectorImpl<SUnit*>::const_iterator
759 I = TopRoots.begin(), E = TopRoots.end(); I != E; ++I) {
760 SchedImpl->releaseTopNode(*I);
762 // Release bottom roots in reverse order so the higher priority nodes appear
763 // first. This is more natural and slightly more efficient.
764 for (SmallVectorImpl<SUnit*>::const_reverse_iterator
765 I = BotRoots.rbegin(), E = BotRoots.rend(); I != E; ++I) {
766 SchedImpl->releaseBottomNode(*I);
769 releaseSuccessors(&EntrySU);
770 releasePredecessors(&ExitSU);
772 SchedImpl->registerRoots();
774 // Advance past initial DebugValues.
775 CurrentTop = nextIfDebug(RegionBegin, RegionEnd);
776 CurrentBottom = RegionEnd;
779 /// Update scheduler queues after scheduling an instruction.
780 void ScheduleDAGMI::updateQueues(SUnit *SU, bool IsTopNode) {
781 // Release dependent instructions for scheduling.
783 releaseSuccessors(SU);
785 releasePredecessors(SU);
787 SU->isScheduled = true;
790 /// Reinsert any remaining debug_values, just like the PostRA scheduler.
791 void ScheduleDAGMI::placeDebugValues() {
792 // If first instruction was a DBG_VALUE then put it back.
794 BB->splice(RegionBegin, BB, FirstDbgValue);
795 RegionBegin = FirstDbgValue;
798 for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
799 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
800 std::pair<MachineInstr *, MachineInstr *> P = *std::prev(DI);
801 MachineInstr *DbgValue = P.first;
802 MachineBasicBlock::iterator OrigPrevMI = P.second;
803 if (&*RegionBegin == DbgValue)
805 BB->splice(++OrigPrevMI, BB, DbgValue);
806 if (OrigPrevMI == std::prev(RegionEnd))
807 RegionEnd = DbgValue;
810 FirstDbgValue = nullptr;
813 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
814 void ScheduleDAGMI::dumpSchedule() const {
815 for (MachineBasicBlock::iterator MI = begin(), ME = end(); MI != ME; ++MI) {
816 if (SUnit *SU = getSUnit(&(*MI)))
819 dbgs() << "Missing SUnit\n";
824 //===----------------------------------------------------------------------===//
825 // ScheduleDAGMILive - Base class for MachineInstr scheduling with LiveIntervals
827 //===----------------------------------------------------------------------===//
829 ScheduleDAGMILive::~ScheduleDAGMILive() {
833 /// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
834 /// crossing a scheduling boundary. [begin, end) includes all instructions in
835 /// the region, including the boundary itself and single-instruction regions
836 /// that don't get scheduled.
837 void ScheduleDAGMILive::enterRegion(MachineBasicBlock *bb,
838 MachineBasicBlock::iterator begin,
839 MachineBasicBlock::iterator end,
840 unsigned regioninstrs)
842 // ScheduleDAGMI initializes SchedImpl's per-region policy.
843 ScheduleDAGMI::enterRegion(bb, begin, end, regioninstrs);
845 // For convenience remember the end of the liveness region.
846 LiveRegionEnd = (RegionEnd == bb->end()) ? RegionEnd : std::next(RegionEnd);
848 SUPressureDiffs.clear();
850 ShouldTrackPressure = SchedImpl->shouldTrackPressure();
853 // Setup the register pressure trackers for the top scheduled top and bottom
854 // scheduled regions.
855 void ScheduleDAGMILive::initRegPressure() {
856 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin);
857 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
859 // Close the RPTracker to finalize live ins.
860 RPTracker.closeRegion();
862 DEBUG(RPTracker.dump());
864 // Initialize the live ins and live outs.
865 TopRPTracker.addLiveRegs(RPTracker.getPressure().LiveInRegs);
866 BotRPTracker.addLiveRegs(RPTracker.getPressure().LiveOutRegs);
868 // Close one end of the tracker so we can call
869 // getMaxUpward/DownwardPressureDelta before advancing across any
870 // instructions. This converts currently live regs into live ins/outs.
871 TopRPTracker.closeTop();
872 BotRPTracker.closeBottom();
874 BotRPTracker.initLiveThru(RPTracker);
875 if (!BotRPTracker.getLiveThru().empty()) {
876 TopRPTracker.initLiveThru(BotRPTracker.getLiveThru());
877 DEBUG(dbgs() << "Live Thru: ";
878 dumpRegSetPressure(BotRPTracker.getLiveThru(), TRI));
881 // For each live out vreg reduce the pressure change associated with other
882 // uses of the same vreg below the live-out reaching def.
883 updatePressureDiffs(RPTracker.getPressure().LiveOutRegs);
885 // Account for liveness generated by the region boundary.
886 if (LiveRegionEnd != RegionEnd) {
887 SmallVector<unsigned, 8> LiveUses;
888 BotRPTracker.recede(&LiveUses);
889 updatePressureDiffs(LiveUses);
892 assert(BotRPTracker.getPos() == RegionEnd && "Can't find the region bottom");
894 // Cache the list of excess pressure sets in this region. This will also track
895 // the max pressure in the scheduled code for these sets.
896 RegionCriticalPSets.clear();
897 const std::vector<unsigned> &RegionPressure =
898 RPTracker.getPressure().MaxSetPressure;
899 for (unsigned i = 0, e = RegionPressure.size(); i < e; ++i) {
900 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i);
901 if (RegionPressure[i] > Limit) {
902 DEBUG(dbgs() << TRI->getRegPressureSetName(i)
903 << " Limit " << Limit
904 << " Actual " << RegionPressure[i] << "\n");
905 RegionCriticalPSets.push_back(PressureChange(i));
908 DEBUG(dbgs() << "Excess PSets: ";
909 for (unsigned i = 0, e = RegionCriticalPSets.size(); i != e; ++i)
910 dbgs() << TRI->getRegPressureSetName(
911 RegionCriticalPSets[i].getPSet()) << " ";
915 void ScheduleDAGMILive::
916 updateScheduledPressure(const SUnit *SU,
917 const std::vector<unsigned> &NewMaxPressure) {
918 const PressureDiff &PDiff = getPressureDiff(SU);
919 unsigned CritIdx = 0, CritEnd = RegionCriticalPSets.size();
920 for (PressureDiff::const_iterator I = PDiff.begin(), E = PDiff.end();
924 unsigned ID = I->getPSet();
925 while (CritIdx != CritEnd && RegionCriticalPSets[CritIdx].getPSet() < ID)
927 if (CritIdx != CritEnd && RegionCriticalPSets[CritIdx].getPSet() == ID) {
928 if ((int)NewMaxPressure[ID] > RegionCriticalPSets[CritIdx].getUnitInc()
929 && NewMaxPressure[ID] <= INT16_MAX)
930 RegionCriticalPSets[CritIdx].setUnitInc(NewMaxPressure[ID]);
932 unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID);
933 if (NewMaxPressure[ID] >= Limit - 2) {
934 DEBUG(dbgs() << " " << TRI->getRegPressureSetName(ID) << ": "
935 << NewMaxPressure[ID] << " > " << Limit << "(+ "
936 << BotRPTracker.getLiveThru()[ID] << " livethru)\n");
941 /// Update the PressureDiff array for liveness after scheduling this
943 void ScheduleDAGMILive::updatePressureDiffs(ArrayRef<unsigned> LiveUses) {
944 for (unsigned LUIdx = 0, LUEnd = LiveUses.size(); LUIdx != LUEnd; ++LUIdx) {
945 /// FIXME: Currently assuming single-use physregs.
946 unsigned Reg = LiveUses[LUIdx];
947 DEBUG(dbgs() << " LiveReg: " << PrintVRegOrUnit(Reg, TRI) << "\n");
948 if (!TRI->isVirtualRegister(Reg))
951 // This may be called before CurrentBottom has been initialized. However,
952 // BotRPTracker must have a valid position. We want the value live into the
953 // instruction or live out of the block, so ask for the previous
954 // instruction's live-out.
955 const LiveInterval &LI = LIS->getInterval(Reg);
957 MachineBasicBlock::const_iterator I =
958 nextIfDebug(BotRPTracker.getPos(), BB->end());
960 VNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
962 LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(I));
965 // RegisterPressureTracker guarantees that readsReg is true for LiveUses.
966 assert(VNI && "No live value at use.");
967 for (VReg2UseMap::iterator
968 UI = VRegUses.find(Reg); UI != VRegUses.end(); ++UI) {
970 DEBUG(dbgs() << " UpdateRegP: SU(" << SU->NodeNum << ") "
972 // If this use comes before the reaching def, it cannot be a last use, so
973 // descrease its pressure change.
974 if (!SU->isScheduled && SU != &ExitSU) {
976 = LI.Query(LIS->getInstructionIndex(SU->getInstr()));
977 if (LRQ.valueIn() == VNI)
978 getPressureDiff(SU).addPressureChange(Reg, true, &MRI);
984 /// schedule - Called back from MachineScheduler::runOnMachineFunction
985 /// after setting up the current scheduling region. [RegionBegin, RegionEnd)
986 /// only includes instructions that have DAG nodes, not scheduling boundaries.
988 /// This is a skeletal driver, with all the functionality pushed into helpers,
989 /// so that it can be easilly extended by experimental schedulers. Generally,
990 /// implementing MachineSchedStrategy should be sufficient to implement a new
991 /// scheduling algorithm. However, if a scheduler further subclasses
992 /// ScheduleDAGMILive then it will want to override this virtual method in order
993 /// to update any specialized state.
994 void ScheduleDAGMILive::schedule() {
995 buildDAGWithRegPressure();
997 Topo.InitDAGTopologicalSorting();
1001 SmallVector<SUnit*, 8> TopRoots, BotRoots;
1002 findRootsAndBiasEdges(TopRoots, BotRoots);
1004 // Initialize the strategy before modifying the DAG.
1005 // This may initialize a DFSResult to be used for queue priority.
1006 SchedImpl->initialize(this);
1008 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
1009 SUnits[su].dumpAll(this));
1010 if (ViewMISchedDAGs) viewGraph();
1012 // Initialize ready queues now that the DAG and priority data are finalized.
1013 initQueues(TopRoots, BotRoots);
1015 if (ShouldTrackPressure) {
1016 assert(TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker");
1017 TopRPTracker.setPos(CurrentTop);
1020 bool IsTopNode = false;
1021 while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) {
1022 assert(!SU->isScheduled && "Node already scheduled");
1023 if (!checkSchedLimit())
1026 scheduleMI(SU, IsTopNode);
1028 updateQueues(SU, IsTopNode);
1031 unsigned SubtreeID = DFSResult->getSubtreeID(SU);
1032 if (!ScheduledTrees.test(SubtreeID)) {
1033 ScheduledTrees.set(SubtreeID);
1034 DFSResult->scheduleTree(SubtreeID);
1035 SchedImpl->scheduleTree(SubtreeID);
1039 // Notify the scheduling strategy after updating the DAG.
1040 SchedImpl->schedNode(SU, IsTopNode);
1042 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
1047 unsigned BBNum = begin()->getParent()->getNumber();
1048 dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
1054 /// Build the DAG and setup three register pressure trackers.
1055 void ScheduleDAGMILive::buildDAGWithRegPressure() {
1056 if (!ShouldTrackPressure) {
1058 RegionCriticalPSets.clear();
1059 buildSchedGraph(AA);
1063 // Initialize the register pressure tracker used by buildSchedGraph.
1064 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd,
1065 /*TrackUntiedDefs=*/true);
1067 // Account for liveness generate by the region boundary.
1068 if (LiveRegionEnd != RegionEnd)
1071 // Build the DAG, and compute current register pressure.
1072 buildSchedGraph(AA, &RPTracker, &SUPressureDiffs);
1074 // Initialize top/bottom trackers after computing region pressure.
1078 void ScheduleDAGMILive::computeDFSResult() {
1080 DFSResult = new SchedDFSResult(/*BottomU*/true, MinSubtreeSize);
1082 ScheduledTrees.clear();
1083 DFSResult->resize(SUnits.size());
1084 DFSResult->compute(SUnits);
1085 ScheduledTrees.resize(DFSResult->getNumSubtrees());
1088 /// Compute the max cyclic critical path through the DAG. The scheduling DAG
1089 /// only provides the critical path for single block loops. To handle loops that
1090 /// span blocks, we could use the vreg path latencies provided by
1091 /// MachineTraceMetrics instead. However, MachineTraceMetrics is not currently
1092 /// available for use in the scheduler.
1094 /// The cyclic path estimation identifies a def-use pair that crosses the back
1095 /// edge and considers the depth and height of the nodes. For example, consider
1096 /// the following instruction sequence where each instruction has unit latency
1097 /// and defines an epomymous virtual register:
1099 /// a->b(a,c)->c(b)->d(c)->exit
1101 /// The cyclic critical path is a two cycles: b->c->b
1102 /// The acyclic critical path is four cycles: a->b->c->d->exit
1103 /// LiveOutHeight = height(c) = len(c->d->exit) = 2
1104 /// LiveOutDepth = depth(c) + 1 = len(a->b->c) + 1 = 3
1105 /// LiveInHeight = height(b) + 1 = len(b->c->d->exit) + 1 = 4
1106 /// LiveInDepth = depth(b) = len(a->b) = 1
1108 /// LiveOutDepth - LiveInDepth = 3 - 1 = 2
1109 /// LiveInHeight - LiveOutHeight = 4 - 2 = 2
1110 /// CyclicCriticalPath = min(2, 2) = 2
1112 /// This could be relevant to PostRA scheduling, but is currently implemented
1113 /// assuming LiveIntervals.
1114 unsigned ScheduleDAGMILive::computeCyclicCriticalPath() {
1115 // This only applies to single block loop.
1116 if (!BB->isSuccessor(BB))
1119 unsigned MaxCyclicLatency = 0;
1120 // Visit each live out vreg def to find def/use pairs that cross iterations.
1121 ArrayRef<unsigned> LiveOuts = RPTracker.getPressure().LiveOutRegs;
1122 for (ArrayRef<unsigned>::iterator RI = LiveOuts.begin(), RE = LiveOuts.end();
1125 if (!TRI->isVirtualRegister(Reg))
1127 const LiveInterval &LI = LIS->getInterval(Reg);
1128 const VNInfo *DefVNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
1132 MachineInstr *DefMI = LIS->getInstructionFromIndex(DefVNI->def);
1133 const SUnit *DefSU = getSUnit(DefMI);
1137 unsigned LiveOutHeight = DefSU->getHeight();
1138 unsigned LiveOutDepth = DefSU->getDepth() + DefSU->Latency;
1139 // Visit all local users of the vreg def.
1140 for (VReg2UseMap::iterator
1141 UI = VRegUses.find(Reg); UI != VRegUses.end(); ++UI) {
1142 if (UI->SU == &ExitSU)
1145 // Only consider uses of the phi.
1146 LiveQueryResult LRQ =
1147 LI.Query(LIS->getInstructionIndex(UI->SU->getInstr()));
1148 if (!LRQ.valueIn()->isPHIDef())
1151 // Assume that a path spanning two iterations is a cycle, which could
1152 // overestimate in strange cases. This allows cyclic latency to be
1153 // estimated as the minimum slack of the vreg's depth or height.
1154 unsigned CyclicLatency = 0;
1155 if (LiveOutDepth > UI->SU->getDepth())
1156 CyclicLatency = LiveOutDepth - UI->SU->getDepth();
1158 unsigned LiveInHeight = UI->SU->getHeight() + DefSU->Latency;
1159 if (LiveInHeight > LiveOutHeight) {
1160 if (LiveInHeight - LiveOutHeight < CyclicLatency)
1161 CyclicLatency = LiveInHeight - LiveOutHeight;
1166 DEBUG(dbgs() << "Cyclic Path: SU(" << DefSU->NodeNum << ") -> SU("
1167 << UI->SU->NodeNum << ") = " << CyclicLatency << "c\n");
1168 if (CyclicLatency > MaxCyclicLatency)
1169 MaxCyclicLatency = CyclicLatency;
1172 DEBUG(dbgs() << "Cyclic Critical Path: " << MaxCyclicLatency << "c\n");
1173 return MaxCyclicLatency;
1176 /// Move an instruction and update register pressure.
1177 void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) {
1178 // Move the instruction to its new location in the instruction stream.
1179 MachineInstr *MI = SU->getInstr();
1182 assert(SU->isTopReady() && "node still has unscheduled dependencies");
1183 if (&*CurrentTop == MI)
1184 CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);
1186 moveInstruction(MI, CurrentTop);
1187 TopRPTracker.setPos(MI);
1190 if (ShouldTrackPressure) {
1191 // Update top scheduled pressure.
1192 TopRPTracker.advance();
1193 assert(TopRPTracker.getPos() == CurrentTop && "out of sync");
1194 updateScheduledPressure(SU, TopRPTracker.getPressure().MaxSetPressure);
1198 assert(SU->isBottomReady() && "node still has unscheduled dependencies");
1199 MachineBasicBlock::iterator priorII =
1200 priorNonDebug(CurrentBottom, CurrentTop);
1201 if (&*priorII == MI)
1202 CurrentBottom = priorII;
1204 if (&*CurrentTop == MI) {
1205 CurrentTop = nextIfDebug(++CurrentTop, priorII);
1206 TopRPTracker.setPos(CurrentTop);
1208 moveInstruction(MI, CurrentBottom);
1211 if (ShouldTrackPressure) {
1212 // Update bottom scheduled pressure.
1213 SmallVector<unsigned, 8> LiveUses;
1214 BotRPTracker.recede(&LiveUses);
1215 assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
1216 updateScheduledPressure(SU, BotRPTracker.getPressure().MaxSetPressure);
1217 updatePressureDiffs(LiveUses);
1222 //===----------------------------------------------------------------------===//
1223 // LoadClusterMutation - DAG post-processing to cluster loads.
1224 //===----------------------------------------------------------------------===//
1227 /// \brief Post-process the DAG to create cluster edges between neighboring
1229 class LoadClusterMutation : public ScheduleDAGMutation {
1234 LoadInfo(SUnit *su, unsigned reg, unsigned ofs)
1235 : SU(su), BaseReg(reg), Offset(ofs) {}
1237 bool operator<(const LoadInfo &RHS) const {
1238 return std::tie(BaseReg, Offset) < std::tie(RHS.BaseReg, RHS.Offset);
1242 const TargetInstrInfo *TII;
1243 const TargetRegisterInfo *TRI;
1245 LoadClusterMutation(const TargetInstrInfo *tii,
1246 const TargetRegisterInfo *tri)
1247 : TII(tii), TRI(tri) {}
1249 void apply(ScheduleDAGMI *DAG) override;
1251 void clusterNeighboringLoads(ArrayRef<SUnit*> Loads, ScheduleDAGMI *DAG);
1255 void LoadClusterMutation::clusterNeighboringLoads(ArrayRef<SUnit*> Loads,
1256 ScheduleDAGMI *DAG) {
1257 SmallVector<LoadClusterMutation::LoadInfo,32> LoadRecords;
1258 for (unsigned Idx = 0, End = Loads.size(); Idx != End; ++Idx) {
1259 SUnit *SU = Loads[Idx];
1262 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
1263 LoadRecords.push_back(LoadInfo(SU, BaseReg, Offset));
1265 if (LoadRecords.size() < 2)
1267 std::sort(LoadRecords.begin(), LoadRecords.end());
1268 unsigned ClusterLength = 1;
1269 for (unsigned Idx = 0, End = LoadRecords.size(); Idx < (End - 1); ++Idx) {
1270 if (LoadRecords[Idx].BaseReg != LoadRecords[Idx+1].BaseReg) {
1275 SUnit *SUa = LoadRecords[Idx].SU;
1276 SUnit *SUb = LoadRecords[Idx+1].SU;
1277 if (TII->shouldClusterLoads(SUa->getInstr(), SUb->getInstr(), ClusterLength)
1278 && DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
1280 DEBUG(dbgs() << "Cluster loads SU(" << SUa->NodeNum << ") - SU("
1281 << SUb->NodeNum << ")\n");
1282 // Copy successor edges from SUa to SUb. Interleaving computation
1283 // dependent on SUa can prevent load combining due to register reuse.
1284 // Predecessor edges do not need to be copied from SUb to SUa since nearby
1285 // loads should have effectively the same inputs.
1286 for (SUnit::const_succ_iterator
1287 SI = SUa->Succs.begin(), SE = SUa->Succs.end(); SI != SE; ++SI) {
1288 if (SI->getSUnit() == SUb)
1290 DEBUG(dbgs() << " Copy Succ SU(" << SI->getSUnit()->NodeNum << ")\n");
1291 DAG->addEdge(SI->getSUnit(), SDep(SUb, SDep::Artificial));
1300 /// \brief Callback from DAG postProcessing to create cluster edges for loads.
1301 void LoadClusterMutation::apply(ScheduleDAGMI *DAG) {
1302 // Map DAG NodeNum to store chain ID.
1303 DenseMap<unsigned, unsigned> StoreChainIDs;
1304 // Map each store chain to a set of dependent loads.
1305 SmallVector<SmallVector<SUnit*,4>, 32> StoreChainDependents;
1306 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
1307 SUnit *SU = &DAG->SUnits[Idx];
1308 if (!SU->getInstr()->mayLoad())
1310 unsigned ChainPredID = DAG->SUnits.size();
1311 for (SUnit::const_pred_iterator
1312 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) {
1314 ChainPredID = PI->getSUnit()->NodeNum;
1318 // Check if this chain-like pred has been seen
1319 // before. ChainPredID==MaxNodeID for loads at the top of the schedule.
1320 unsigned NumChains = StoreChainDependents.size();
1321 std::pair<DenseMap<unsigned, unsigned>::iterator, bool> Result =
1322 StoreChainIDs.insert(std::make_pair(ChainPredID, NumChains));
1324 StoreChainDependents.resize(NumChains + 1);
1325 StoreChainDependents[Result.first->second].push_back(SU);
1327 // Iterate over the store chains.
1328 for (unsigned Idx = 0, End = StoreChainDependents.size(); Idx != End; ++Idx)
1329 clusterNeighboringLoads(StoreChainDependents[Idx], DAG);
1332 //===----------------------------------------------------------------------===//
1333 // MacroFusion - DAG post-processing to encourage fusion of macro ops.
1334 //===----------------------------------------------------------------------===//
1337 /// \brief Post-process the DAG to create cluster edges between instructions
1338 /// that may be fused by the processor into a single operation.
1339 class MacroFusion : public ScheduleDAGMutation {
1340 const TargetInstrInfo *TII;
1342 MacroFusion(const TargetInstrInfo *tii): TII(tii) {}
1344 void apply(ScheduleDAGMI *DAG) override;
1348 /// \brief Callback from DAG postProcessing to create cluster edges to encourage
1349 /// fused operations.
1350 void MacroFusion::apply(ScheduleDAGMI *DAG) {
1351 // For now, assume targets can only fuse with the branch.
1352 MachineInstr *Branch = DAG->ExitSU.getInstr();
1356 for (unsigned Idx = DAG->SUnits.size(); Idx > 0;) {
1357 SUnit *SU = &DAG->SUnits[--Idx];
1358 if (!TII->shouldScheduleAdjacent(SU->getInstr(), Branch))
1361 // Create a single weak edge from SU to ExitSU. The only effect is to cause
1362 // bottom-up scheduling to heavily prioritize the clustered SU. There is no
1363 // need to copy predecessor edges from ExitSU to SU, since top-down
1364 // scheduling cannot prioritize ExitSU anyway. To defer top-down scheduling
1365 // of SU, we could create an artificial edge from the deepest root, but it
1366 // hasn't been needed yet.
1367 bool Success = DAG->addEdge(&DAG->ExitSU, SDep(SU, SDep::Cluster));
1369 assert(Success && "No DAG nodes should be reachable from ExitSU");
1371 DEBUG(dbgs() << "Macro Fuse SU(" << SU->NodeNum << ")\n");
1376 //===----------------------------------------------------------------------===//
1377 // CopyConstrain - DAG post-processing to encourage copy elimination.
1378 //===----------------------------------------------------------------------===//
1381 /// \brief Post-process the DAG to create weak edges from all uses of a copy to
1382 /// the one use that defines the copy's source vreg, most likely an induction
1383 /// variable increment.
1384 class CopyConstrain : public ScheduleDAGMutation {
1386 SlotIndex RegionBeginIdx;
1387 // RegionEndIdx is the slot index of the last non-debug instruction in the
1388 // scheduling region. So we may have RegionBeginIdx == RegionEndIdx.
1389 SlotIndex RegionEndIdx;
1391 CopyConstrain(const TargetInstrInfo *, const TargetRegisterInfo *) {}
1393 void apply(ScheduleDAGMI *DAG) override;
1396 void constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG);
1400 /// constrainLocalCopy handles two possibilities:
1405 /// I3: dst = src (copy)
1406 /// (create pred->succ edges I0->I1, I2->I1)
1409 /// I0: dst = src (copy)
1413 /// (create pred->succ edges I1->I2, I3->I2)
1415 /// Although the MachineScheduler is currently constrained to single blocks,
1416 /// this algorithm should handle extended blocks. An EBB is a set of
1417 /// contiguously numbered blocks such that the previous block in the EBB is
1418 /// always the single predecessor.
1419 void CopyConstrain::constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG) {
1420 LiveIntervals *LIS = DAG->getLIS();
1421 MachineInstr *Copy = CopySU->getInstr();
1423 // Check for pure vreg copies.
1424 unsigned SrcReg = Copy->getOperand(1).getReg();
1425 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
1428 unsigned DstReg = Copy->getOperand(0).getReg();
1429 if (!TargetRegisterInfo::isVirtualRegister(DstReg))
1432 // Check if either the dest or source is local. If it's live across a back
1433 // edge, it's not local. Note that if both vregs are live across the back
1434 // edge, we cannot successfully contrain the copy without cyclic scheduling.
1435 unsigned LocalReg = DstReg;
1436 unsigned GlobalReg = SrcReg;
1437 LiveInterval *LocalLI = &LIS->getInterval(LocalReg);
1438 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx)) {
1441 LocalLI = &LIS->getInterval(LocalReg);
1442 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx))
1445 LiveInterval *GlobalLI = &LIS->getInterval(GlobalReg);
1447 // Find the global segment after the start of the local LI.
1448 LiveInterval::iterator GlobalSegment = GlobalLI->find(LocalLI->beginIndex());
1449 // If GlobalLI does not overlap LocalLI->start, then a copy directly feeds a
1450 // local live range. We could create edges from other global uses to the local
1451 // start, but the coalescer should have already eliminated these cases, so
1452 // don't bother dealing with it.
1453 if (GlobalSegment == GlobalLI->end())
1456 // If GlobalSegment is killed at the LocalLI->start, the call to find()
1457 // returned the next global segment. But if GlobalSegment overlaps with
1458 // LocalLI->start, then advance to the next segement. If a hole in GlobalLI
1459 // exists in LocalLI's vicinity, GlobalSegment will be the end of the hole.
1460 if (GlobalSegment->contains(LocalLI->beginIndex()))
1463 if (GlobalSegment == GlobalLI->end())
1466 // Check if GlobalLI contains a hole in the vicinity of LocalLI.
1467 if (GlobalSegment != GlobalLI->begin()) {
1468 // Two address defs have no hole.
1469 if (SlotIndex::isSameInstr(std::prev(GlobalSegment)->end,
1470 GlobalSegment->start)) {
1473 // If the prior global segment may be defined by the same two-address
1474 // instruction that also defines LocalLI, then can't make a hole here.
1475 if (SlotIndex::isSameInstr(std::prev(GlobalSegment)->start,
1476 LocalLI->beginIndex())) {
1479 // If GlobalLI has a prior segment, it must be live into the EBB. Otherwise
1480 // it would be a disconnected component in the live range.
1481 assert(std::prev(GlobalSegment)->start < LocalLI->beginIndex() &&
1482 "Disconnected LRG within the scheduling region.");
1484 MachineInstr *GlobalDef = LIS->getInstructionFromIndex(GlobalSegment->start);
1488 SUnit *GlobalSU = DAG->getSUnit(GlobalDef);
1492 // GlobalDef is the bottom of the GlobalLI hole. Open the hole by
1493 // constraining the uses of the last local def to precede GlobalDef.
1494 SmallVector<SUnit*,8> LocalUses;
1495 const VNInfo *LastLocalVN = LocalLI->getVNInfoBefore(LocalLI->endIndex());
1496 MachineInstr *LastLocalDef = LIS->getInstructionFromIndex(LastLocalVN->def);
1497 SUnit *LastLocalSU = DAG->getSUnit(LastLocalDef);
1498 for (SUnit::const_succ_iterator
1499 I = LastLocalSU->Succs.begin(), E = LastLocalSU->Succs.end();
1501 if (I->getKind() != SDep::Data || I->getReg() != LocalReg)
1503 if (I->getSUnit() == GlobalSU)
1505 if (!DAG->canAddEdge(GlobalSU, I->getSUnit()))
1507 LocalUses.push_back(I->getSUnit());
1509 // Open the top of the GlobalLI hole by constraining any earlier global uses
1510 // to precede the start of LocalLI.
1511 SmallVector<SUnit*,8> GlobalUses;
1512 MachineInstr *FirstLocalDef =
1513 LIS->getInstructionFromIndex(LocalLI->beginIndex());
1514 SUnit *FirstLocalSU = DAG->getSUnit(FirstLocalDef);
1515 for (SUnit::const_pred_iterator
1516 I = GlobalSU->Preds.begin(), E = GlobalSU->Preds.end(); I != E; ++I) {
1517 if (I->getKind() != SDep::Anti || I->getReg() != GlobalReg)
1519 if (I->getSUnit() == FirstLocalSU)
1521 if (!DAG->canAddEdge(FirstLocalSU, I->getSUnit()))
1523 GlobalUses.push_back(I->getSUnit());
1525 DEBUG(dbgs() << "Constraining copy SU(" << CopySU->NodeNum << ")\n");
1526 // Add the weak edges.
1527 for (SmallVectorImpl<SUnit*>::const_iterator
1528 I = LocalUses.begin(), E = LocalUses.end(); I != E; ++I) {
1529 DEBUG(dbgs() << " Local use SU(" << (*I)->NodeNum << ") -> SU("
1530 << GlobalSU->NodeNum << ")\n");
1531 DAG->addEdge(GlobalSU, SDep(*I, SDep::Weak));
1533 for (SmallVectorImpl<SUnit*>::const_iterator
1534 I = GlobalUses.begin(), E = GlobalUses.end(); I != E; ++I) {
1535 DEBUG(dbgs() << " Global use SU(" << (*I)->NodeNum << ") -> SU("
1536 << FirstLocalSU->NodeNum << ")\n");
1537 DAG->addEdge(FirstLocalSU, SDep(*I, SDep::Weak));
1541 /// \brief Callback from DAG postProcessing to create weak edges to encourage
1542 /// copy elimination.
1543 void CopyConstrain::apply(ScheduleDAGMI *DAG) {
1544 assert(DAG->hasVRegLiveness() && "Expect VRegs with LiveIntervals");
1546 MachineBasicBlock::iterator FirstPos = nextIfDebug(DAG->begin(), DAG->end());
1547 if (FirstPos == DAG->end())
1549 RegionBeginIdx = DAG->getLIS()->getInstructionIndex(&*FirstPos);
1550 RegionEndIdx = DAG->getLIS()->getInstructionIndex(
1551 &*priorNonDebug(DAG->end(), DAG->begin()));
1553 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
1554 SUnit *SU = &DAG->SUnits[Idx];
1555 if (!SU->getInstr()->isCopy())
1558 constrainLocalCopy(SU, static_cast<ScheduleDAGMILive*>(DAG));
1562 //===----------------------------------------------------------------------===//
1563 // MachineSchedStrategy helpers used by GenericScheduler, GenericPostScheduler
1564 // and possibly other custom schedulers.
1565 //===----------------------------------------------------------------------===//
1567 static const unsigned InvalidCycle = ~0U;
1569 SchedBoundary::~SchedBoundary() { delete HazardRec; }
1571 void SchedBoundary::reset() {
1572 // A new HazardRec is created for each DAG and owned by SchedBoundary.
1573 // Destroying and reconstructing it is very expensive though. So keep
1574 // invalid, placeholder HazardRecs.
1575 if (HazardRec && HazardRec->isEnabled()) {
1577 HazardRec = nullptr;
1581 CheckPending = false;
1585 MinReadyCycle = UINT_MAX;
1586 ExpectedLatency = 0;
1587 DependentLatency = 0;
1589 MaxExecutedResCount = 0;
1591 IsResourceLimited = false;
1592 ReservedCycles.clear();
1594 // Track the maximum number of stall cycles that could arise either from the
1595 // latency of a DAG edge or the number of cycles that a processor resource is
1596 // reserved (SchedBoundary::ReservedCycles).
1597 MaxObservedStall = 0;
1599 // Reserve a zero-count for invalid CritResIdx.
1600 ExecutedResCounts.resize(1);
1601 assert(!ExecutedResCounts[0] && "nonzero count for bad resource");
1604 void SchedRemainder::
1605 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) {
1607 if (!SchedModel->hasInstrSchedModel())
1609 RemainingCounts.resize(SchedModel->getNumProcResourceKinds());
1610 for (std::vector<SUnit>::iterator
1611 I = DAG->SUnits.begin(), E = DAG->SUnits.end(); I != E; ++I) {
1612 const MCSchedClassDesc *SC = DAG->getSchedClass(&*I);
1613 RemIssueCount += SchedModel->getNumMicroOps(I->getInstr(), SC)
1614 * SchedModel->getMicroOpFactor();
1615 for (TargetSchedModel::ProcResIter
1616 PI = SchedModel->getWriteProcResBegin(SC),
1617 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1618 unsigned PIdx = PI->ProcResourceIdx;
1619 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1620 RemainingCounts[PIdx] += (Factor * PI->Cycles);
1625 void SchedBoundary::
1626 init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem) {
1629 SchedModel = smodel;
1631 if (SchedModel->hasInstrSchedModel()) {
1632 ExecutedResCounts.resize(SchedModel->getNumProcResourceKinds());
1633 ReservedCycles.resize(SchedModel->getNumProcResourceKinds(), InvalidCycle);
1637 /// Compute the stall cycles based on this SUnit's ready time. Heuristics treat
1638 /// these "soft stalls" differently than the hard stall cycles based on CPU
1639 /// resources and computed by checkHazard(). A fully in-order model
1640 /// (MicroOpBufferSize==0) will not make use of this since instructions are not
1641 /// available for scheduling until they are ready. However, a weaker in-order
1642 /// model may use this for heuristics. For example, if a processor has in-order
1643 /// behavior when reading certain resources, this may come into play.
1644 unsigned SchedBoundary::getLatencyStallCycles(SUnit *SU) {
1645 if (!SU->isUnbuffered)
1648 unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle);
1649 if (ReadyCycle > CurrCycle)
1650 return ReadyCycle - CurrCycle;
1654 /// Compute the next cycle at which the given processor resource can be
1656 unsigned SchedBoundary::
1657 getNextResourceCycle(unsigned PIdx, unsigned Cycles) {
1658 unsigned NextUnreserved = ReservedCycles[PIdx];
1659 // If this resource has never been used, always return cycle zero.
1660 if (NextUnreserved == InvalidCycle)
1662 // For bottom-up scheduling add the cycles needed for the current operation.
1664 NextUnreserved += Cycles;
1665 return NextUnreserved;
1668 /// Does this SU have a hazard within the current instruction group.
1670 /// The scheduler supports two modes of hazard recognition. The first is the
1671 /// ScheduleHazardRecognizer API. It is a fully general hazard recognizer that
1672 /// supports highly complicated in-order reservation tables
1673 /// (ScoreboardHazardRecognizer) and arbitraty target-specific logic.
1675 /// The second is a streamlined mechanism that checks for hazards based on
1676 /// simple counters that the scheduler itself maintains. It explicitly checks
1677 /// for instruction dispatch limitations, including the number of micro-ops that
1678 /// can dispatch per cycle.
1680 /// TODO: Also check whether the SU must start a new group.
1681 bool SchedBoundary::checkHazard(SUnit *SU) {
1682 if (HazardRec->isEnabled()
1683 && HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard) {
1686 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
1687 if ((CurrMOps > 0) && (CurrMOps + uops > SchedModel->getIssueWidth())) {
1688 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") uops="
1689 << SchedModel->getNumMicroOps(SU->getInstr()) << '\n');
1692 if (SchedModel->hasInstrSchedModel() && SU->hasReservedResource) {
1693 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
1694 for (TargetSchedModel::ProcResIter
1695 PI = SchedModel->getWriteProcResBegin(SC),
1696 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1697 unsigned NRCycle = getNextResourceCycle(PI->ProcResourceIdx, PI->Cycles);
1698 if (NRCycle > CurrCycle) {
1700 MaxObservedStall = std::max(PI->Cycles, MaxObservedStall);
1702 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") "
1703 << SchedModel->getResourceName(PI->ProcResourceIdx)
1704 << "=" << NRCycle << "c\n");
1712 // Find the unscheduled node in ReadySUs with the highest latency.
1713 unsigned SchedBoundary::
1714 findMaxLatency(ArrayRef<SUnit*> ReadySUs) {
1715 SUnit *LateSU = nullptr;
1716 unsigned RemLatency = 0;
1717 for (ArrayRef<SUnit*>::iterator I = ReadySUs.begin(), E = ReadySUs.end();
1719 unsigned L = getUnscheduledLatency(*I);
1720 if (L > RemLatency) {
1726 DEBUG(dbgs() << Available.getName() << " RemLatency SU("
1727 << LateSU->NodeNum << ") " << RemLatency << "c\n");
1732 // Count resources in this zone and the remaining unscheduled
1733 // instruction. Return the max count, scaled. Set OtherCritIdx to the critical
1734 // resource index, or zero if the zone is issue limited.
1735 unsigned SchedBoundary::
1736 getOtherResourceCount(unsigned &OtherCritIdx) {
1738 if (!SchedModel->hasInstrSchedModel())
1741 unsigned OtherCritCount = Rem->RemIssueCount
1742 + (RetiredMOps * SchedModel->getMicroOpFactor());
1743 DEBUG(dbgs() << " " << Available.getName() << " + Remain MOps: "
1744 << OtherCritCount / SchedModel->getMicroOpFactor() << '\n');
1745 for (unsigned PIdx = 1, PEnd = SchedModel->getNumProcResourceKinds();
1746 PIdx != PEnd; ++PIdx) {
1747 unsigned OtherCount = getResourceCount(PIdx) + Rem->RemainingCounts[PIdx];
1748 if (OtherCount > OtherCritCount) {
1749 OtherCritCount = OtherCount;
1750 OtherCritIdx = PIdx;
1754 DEBUG(dbgs() << " " << Available.getName() << " + Remain CritRes: "
1755 << OtherCritCount / SchedModel->getResourceFactor(OtherCritIdx)
1756 << " " << SchedModel->getResourceName(OtherCritIdx) << "\n");
1758 return OtherCritCount;
1761 void SchedBoundary::releaseNode(SUnit *SU, unsigned ReadyCycle) {
1762 assert(SU->getInstr() && "Scheduled SUnit must have instr");
1765 // ReadyCycle was been bumped up to the CurrCycle when this node was
1766 // scheduled, but CurrCycle may have been eagerly advanced immediately after
1767 // scheduling, so may now be greater than ReadyCycle.
1768 if (ReadyCycle > CurrCycle)
1769 MaxObservedStall = std::max(ReadyCycle - CurrCycle, MaxObservedStall);
1772 if (ReadyCycle < MinReadyCycle)
1773 MinReadyCycle = ReadyCycle;
1775 // Check for interlocks first. For the purpose of other heuristics, an
1776 // instruction that cannot issue appears as if it's not in the ReadyQueue.
1777 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
1778 if ((!IsBuffered && ReadyCycle > CurrCycle) || checkHazard(SU))
1783 // Record this node as an immediate dependent of the scheduled node.
1787 void SchedBoundary::releaseTopNode(SUnit *SU) {
1788 if (SU->isScheduled)
1791 releaseNode(SU, SU->TopReadyCycle);
1794 void SchedBoundary::releaseBottomNode(SUnit *SU) {
1795 if (SU->isScheduled)
1798 releaseNode(SU, SU->BotReadyCycle);
1801 /// Move the boundary of scheduled code by one cycle.
1802 void SchedBoundary::bumpCycle(unsigned NextCycle) {
1803 if (SchedModel->getMicroOpBufferSize() == 0) {
1804 assert(MinReadyCycle < UINT_MAX && "MinReadyCycle uninitialized");
1805 if (MinReadyCycle > NextCycle)
1806 NextCycle = MinReadyCycle;
1808 // Update the current micro-ops, which will issue in the next cycle.
1809 unsigned DecMOps = SchedModel->getIssueWidth() * (NextCycle - CurrCycle);
1810 CurrMOps = (CurrMOps <= DecMOps) ? 0 : CurrMOps - DecMOps;
1812 // Decrement DependentLatency based on the next cycle.
1813 if ((NextCycle - CurrCycle) > DependentLatency)
1814 DependentLatency = 0;
1816 DependentLatency -= (NextCycle - CurrCycle);
1818 if (!HazardRec->isEnabled()) {
1819 // Bypass HazardRec virtual calls.
1820 CurrCycle = NextCycle;
1823 // Bypass getHazardType calls in case of long latency.
1824 for (; CurrCycle != NextCycle; ++CurrCycle) {
1826 HazardRec->AdvanceCycle();
1828 HazardRec->RecedeCycle();
1831 CheckPending = true;
1832 unsigned LFactor = SchedModel->getLatencyFactor();
1834 (int)(getCriticalCount() - (getScheduledLatency() * LFactor))
1837 DEBUG(dbgs() << "Cycle: " << CurrCycle << ' ' << Available.getName() << '\n');
1840 void SchedBoundary::incExecutedResources(unsigned PIdx, unsigned Count) {
1841 ExecutedResCounts[PIdx] += Count;
1842 if (ExecutedResCounts[PIdx] > MaxExecutedResCount)
1843 MaxExecutedResCount = ExecutedResCounts[PIdx];
1846 /// Add the given processor resource to this scheduled zone.
1848 /// \param Cycles indicates the number of consecutive (non-pipelined) cycles
1849 /// during which this resource is consumed.
1851 /// \return the next cycle at which the instruction may execute without
1852 /// oversubscribing resources.
1853 unsigned SchedBoundary::
1854 countResource(unsigned PIdx, unsigned Cycles, unsigned NextCycle) {
1855 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1856 unsigned Count = Factor * Cycles;
1857 DEBUG(dbgs() << " " << SchedModel->getResourceName(PIdx)
1858 << " +" << Cycles << "x" << Factor << "u\n");
1860 // Update Executed resources counts.
1861 incExecutedResources(PIdx, Count);
1862 assert(Rem->RemainingCounts[PIdx] >= Count && "resource double counted");
1863 Rem->RemainingCounts[PIdx] -= Count;
1865 // Check if this resource exceeds the current critical resource. If so, it
1866 // becomes the critical resource.
1867 if (ZoneCritResIdx != PIdx && (getResourceCount(PIdx) > getCriticalCount())) {
1868 ZoneCritResIdx = PIdx;
1869 DEBUG(dbgs() << " *** Critical resource "
1870 << SchedModel->getResourceName(PIdx) << ": "
1871 << getResourceCount(PIdx) / SchedModel->getLatencyFactor() << "c\n");
1873 // For reserved resources, record the highest cycle using the resource.
1874 unsigned NextAvailable = getNextResourceCycle(PIdx, Cycles);
1875 if (NextAvailable > CurrCycle) {
1876 DEBUG(dbgs() << " Resource conflict: "
1877 << SchedModel->getProcResource(PIdx)->Name << " reserved until @"
1878 << NextAvailable << "\n");
1880 return NextAvailable;
1883 /// Move the boundary of scheduled code by one SUnit.
1884 void SchedBoundary::bumpNode(SUnit *SU) {
1885 // Update the reservation table.
1886 if (HazardRec->isEnabled()) {
1887 if (!isTop() && SU->isCall) {
1888 // Calls are scheduled with their preceding instructions. For bottom-up
1889 // scheduling, clear the pipeline state before emitting.
1892 HazardRec->EmitInstruction(SU);
1894 // checkHazard should prevent scheduling multiple instructions per cycle that
1895 // exceed the issue width.
1896 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
1897 unsigned IncMOps = SchedModel->getNumMicroOps(SU->getInstr());
1899 (CurrMOps == 0 || (CurrMOps + IncMOps) <= SchedModel->getIssueWidth()) &&
1900 "Cannot schedule this instruction's MicroOps in the current cycle.");
1902 unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle);
1903 DEBUG(dbgs() << " Ready @" << ReadyCycle << "c\n");
1905 unsigned NextCycle = CurrCycle;
1906 switch (SchedModel->getMicroOpBufferSize()) {
1908 assert(ReadyCycle <= CurrCycle && "Broken PendingQueue");
1911 if (ReadyCycle > NextCycle) {
1912 NextCycle = ReadyCycle;
1913 DEBUG(dbgs() << " *** Stall until: " << ReadyCycle << "\n");
1917 // We don't currently model the OOO reorder buffer, so consider all
1918 // scheduled MOps to be "retired". We do loosely model in-order resource
1919 // latency. If this instruction uses an in-order resource, account for any
1920 // likely stall cycles.
1921 if (SU->isUnbuffered && ReadyCycle > NextCycle)
1922 NextCycle = ReadyCycle;
1925 RetiredMOps += IncMOps;
1927 // Update resource counts and critical resource.
1928 if (SchedModel->hasInstrSchedModel()) {
1929 unsigned DecRemIssue = IncMOps * SchedModel->getMicroOpFactor();
1930 assert(Rem->RemIssueCount >= DecRemIssue && "MOps double counted");
1931 Rem->RemIssueCount -= DecRemIssue;
1932 if (ZoneCritResIdx) {
1933 // Scale scheduled micro-ops for comparing with the critical resource.
1934 unsigned ScaledMOps =
1935 RetiredMOps * SchedModel->getMicroOpFactor();
1937 // If scaled micro-ops are now more than the previous critical resource by
1938 // a full cycle, then micro-ops issue becomes critical.
1939 if ((int)(ScaledMOps - getResourceCount(ZoneCritResIdx))
1940 >= (int)SchedModel->getLatencyFactor()) {
1942 DEBUG(dbgs() << " *** Critical resource NumMicroOps: "
1943 << ScaledMOps / SchedModel->getLatencyFactor() << "c\n");
1946 for (TargetSchedModel::ProcResIter
1947 PI = SchedModel->getWriteProcResBegin(SC),
1948 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1950 countResource(PI->ProcResourceIdx, PI->Cycles, NextCycle);
1951 if (RCycle > NextCycle)
1954 if (SU->hasReservedResource) {
1955 // For reserved resources, record the highest cycle using the resource.
1956 // For top-down scheduling, this is the cycle in which we schedule this
1957 // instruction plus the number of cycles the operations reserves the
1958 // resource. For bottom-up is it simply the instruction's cycle.
1959 for (TargetSchedModel::ProcResIter
1960 PI = SchedModel->getWriteProcResBegin(SC),
1961 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1962 unsigned PIdx = PI->ProcResourceIdx;
1963 if (SchedModel->getProcResource(PIdx)->BufferSize == 0) {
1965 ReservedCycles[PIdx] =
1966 std::max(getNextResourceCycle(PIdx, 0), NextCycle + PI->Cycles);
1969 ReservedCycles[PIdx] = NextCycle;
1974 // Update ExpectedLatency and DependentLatency.
1975 unsigned &TopLatency = isTop() ? ExpectedLatency : DependentLatency;
1976 unsigned &BotLatency = isTop() ? DependentLatency : ExpectedLatency;
1977 if (SU->getDepth() > TopLatency) {
1978 TopLatency = SU->getDepth();
1979 DEBUG(dbgs() << " " << Available.getName()
1980 << " TopLatency SU(" << SU->NodeNum << ") " << TopLatency << "c\n");
1982 if (SU->getHeight() > BotLatency) {
1983 BotLatency = SU->getHeight();
1984 DEBUG(dbgs() << " " << Available.getName()
1985 << " BotLatency SU(" << SU->NodeNum << ") " << BotLatency << "c\n");
1987 // If we stall for any reason, bump the cycle.
1988 if (NextCycle > CurrCycle) {
1989 bumpCycle(NextCycle);
1992 // After updating ZoneCritResIdx and ExpectedLatency, check if we're
1993 // resource limited. If a stall occurred, bumpCycle does this.
1994 unsigned LFactor = SchedModel->getLatencyFactor();
1996 (int)(getCriticalCount() - (getScheduledLatency() * LFactor))
1999 // Update CurrMOps after calling bumpCycle to handle stalls, since bumpCycle
2000 // resets CurrMOps. Loop to handle instructions with more MOps than issue in
2001 // one cycle. Since we commonly reach the max MOps here, opportunistically
2002 // bump the cycle to avoid uselessly checking everything in the readyQ.
2003 CurrMOps += IncMOps;
2004 while (CurrMOps >= SchedModel->getIssueWidth()) {
2005 DEBUG(dbgs() << " *** Max MOps " << CurrMOps
2006 << " at cycle " << CurrCycle << '\n');
2007 bumpCycle(++NextCycle);
2009 DEBUG(dumpScheduledState());
2012 /// Release pending ready nodes in to the available queue. This makes them
2013 /// visible to heuristics.
2014 void SchedBoundary::releasePending() {
2015 // If the available queue is empty, it is safe to reset MinReadyCycle.
2016 if (Available.empty())
2017 MinReadyCycle = UINT_MAX;
2019 // Check to see if any of the pending instructions are ready to issue. If
2020 // so, add them to the available queue.
2021 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
2022 for (unsigned i = 0, e = Pending.size(); i != e; ++i) {
2023 SUnit *SU = *(Pending.begin()+i);
2024 unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle;
2026 if (ReadyCycle < MinReadyCycle)
2027 MinReadyCycle = ReadyCycle;
2029 if (!IsBuffered && ReadyCycle > CurrCycle)
2032 if (checkHazard(SU))
2036 Pending.remove(Pending.begin()+i);
2039 DEBUG(if (!Pending.empty()) Pending.dump());
2040 CheckPending = false;
2043 /// Remove SU from the ready set for this boundary.
2044 void SchedBoundary::removeReady(SUnit *SU) {
2045 if (Available.isInQueue(SU))
2046 Available.remove(Available.find(SU));
2048 assert(Pending.isInQueue(SU) && "bad ready count");
2049 Pending.remove(Pending.find(SU));
2053 /// If this queue only has one ready candidate, return it. As a side effect,
2054 /// defer any nodes that now hit a hazard, and advance the cycle until at least
2055 /// one node is ready. If multiple instructions are ready, return NULL.
2056 SUnit *SchedBoundary::pickOnlyChoice() {
2061 // Defer any ready instrs that now have a hazard.
2062 for (ReadyQueue::iterator I = Available.begin(); I != Available.end();) {
2063 if (checkHazard(*I)) {
2065 I = Available.remove(I);
2071 for (unsigned i = 0; Available.empty(); ++i) {
2072 // FIXME: Re-enable assert once PR20057 is resolved.
2073 // assert(i <= (HazardRec->getMaxLookAhead() + MaxObservedStall) &&
2074 // "permanent hazard");
2076 bumpCycle(CurrCycle + 1);
2079 if (Available.size() == 1)
2080 return *Available.begin();
2085 // This is useful information to dump after bumpNode.
2086 // Note that the Queue contents are more useful before pickNodeFromQueue.
2087 void SchedBoundary::dumpScheduledState() {
2090 if (ZoneCritResIdx) {
2091 ResFactor = SchedModel->getResourceFactor(ZoneCritResIdx);
2092 ResCount = getResourceCount(ZoneCritResIdx);
2095 ResFactor = SchedModel->getMicroOpFactor();
2096 ResCount = RetiredMOps * SchedModel->getMicroOpFactor();
2098 unsigned LFactor = SchedModel->getLatencyFactor();
2099 dbgs() << Available.getName() << " @" << CurrCycle << "c\n"
2100 << " Retired: " << RetiredMOps;
2101 dbgs() << "\n Executed: " << getExecutedCount() / LFactor << "c";
2102 dbgs() << "\n Critical: " << ResCount / LFactor << "c, "
2103 << ResCount / ResFactor << " "
2104 << SchedModel->getResourceName(ZoneCritResIdx)
2105 << "\n ExpectedLatency: " << ExpectedLatency << "c\n"
2106 << (IsResourceLimited ? " - Resource" : " - Latency")
2111 //===----------------------------------------------------------------------===//
2112 // GenericScheduler - Generic implementation of MachineSchedStrategy.
2113 //===----------------------------------------------------------------------===//
2115 void GenericSchedulerBase::SchedCandidate::
2116 initResourceDelta(const ScheduleDAGMI *DAG,
2117 const TargetSchedModel *SchedModel) {
2118 if (!Policy.ReduceResIdx && !Policy.DemandResIdx)
2121 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
2122 for (TargetSchedModel::ProcResIter
2123 PI = SchedModel->getWriteProcResBegin(SC),
2124 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
2125 if (PI->ProcResourceIdx == Policy.ReduceResIdx)
2126 ResDelta.CritResources += PI->Cycles;
2127 if (PI->ProcResourceIdx == Policy.DemandResIdx)
2128 ResDelta.DemandedResources += PI->Cycles;
2132 /// Set the CandPolicy given a scheduling zone given the current resources and
2133 /// latencies inside and outside the zone.
2134 void GenericSchedulerBase::setPolicy(CandPolicy &Policy,
2136 SchedBoundary &CurrZone,
2137 SchedBoundary *OtherZone) {
2138 // Apply preemptive heuristics based on the the total latency and resources
2139 // inside and outside this zone. Potential stalls should be considered before
2140 // following this policy.
2142 // Compute remaining latency. We need this both to determine whether the
2143 // overall schedule has become latency-limited and whether the instructions
2144 // outside this zone are resource or latency limited.
2146 // The "dependent" latency is updated incrementally during scheduling as the
2147 // max height/depth of scheduled nodes minus the cycles since it was
2149 // DLat = max (N.depth - (CurrCycle - N.ReadyCycle) for N in Zone
2151 // The "independent" latency is the max ready queue depth:
2152 // ILat = max N.depth for N in Available|Pending
2154 // RemainingLatency is the greater of independent and dependent latency.
2155 unsigned RemLatency = CurrZone.getDependentLatency();
2156 RemLatency = std::max(RemLatency,
2157 CurrZone.findMaxLatency(CurrZone.Available.elements()));
2158 RemLatency = std::max(RemLatency,
2159 CurrZone.findMaxLatency(CurrZone.Pending.elements()));
2161 // Compute the critical resource outside the zone.
2162 unsigned OtherCritIdx = 0;
2163 unsigned OtherCount =
2164 OtherZone ? OtherZone->getOtherResourceCount(OtherCritIdx) : 0;
2166 bool OtherResLimited = false;
2167 if (SchedModel->hasInstrSchedModel()) {
2168 unsigned LFactor = SchedModel->getLatencyFactor();
2169 OtherResLimited = (int)(OtherCount - (RemLatency * LFactor)) > (int)LFactor;
2171 // Schedule aggressively for latency in PostRA mode. We don't check for
2172 // acyclic latency during PostRA, and highly out-of-order processors will
2173 // skip PostRA scheduling.
2174 if (!OtherResLimited) {
2175 if (IsPostRA || (RemLatency + CurrZone.getCurrCycle() > Rem.CriticalPath)) {
2176 Policy.ReduceLatency |= true;
2177 DEBUG(dbgs() << " " << CurrZone.Available.getName()
2178 << " RemainingLatency " << RemLatency << " + "
2179 << CurrZone.getCurrCycle() << "c > CritPath "
2180 << Rem.CriticalPath << "\n");
2183 // If the same resource is limiting inside and outside the zone, do nothing.
2184 if (CurrZone.getZoneCritResIdx() == OtherCritIdx)
2188 if (CurrZone.isResourceLimited()) {
2189 dbgs() << " " << CurrZone.Available.getName() << " ResourceLimited: "
2190 << SchedModel->getResourceName(CurrZone.getZoneCritResIdx())
2193 if (OtherResLimited)
2194 dbgs() << " RemainingLimit: "
2195 << SchedModel->getResourceName(OtherCritIdx) << "\n";
2196 if (!CurrZone.isResourceLimited() && !OtherResLimited)
2197 dbgs() << " Latency limited both directions.\n");
2199 if (CurrZone.isResourceLimited() && !Policy.ReduceResIdx)
2200 Policy.ReduceResIdx = CurrZone.getZoneCritResIdx();
2202 if (OtherResLimited)
2203 Policy.DemandResIdx = OtherCritIdx;
2207 const char *GenericSchedulerBase::getReasonStr(
2208 GenericSchedulerBase::CandReason Reason) {
2210 case NoCand: return "NOCAND ";
2211 case PhysRegCopy: return "PREG-COPY";
2212 case RegExcess: return "REG-EXCESS";
2213 case RegCritical: return "REG-CRIT ";
2214 case Stall: return "STALL ";
2215 case Cluster: return "CLUSTER ";
2216 case Weak: return "WEAK ";
2217 case RegMax: return "REG-MAX ";
2218 case ResourceReduce: return "RES-REDUCE";
2219 case ResourceDemand: return "RES-DEMAND";
2220 case TopDepthReduce: return "TOP-DEPTH ";
2221 case TopPathReduce: return "TOP-PATH ";
2222 case BotHeightReduce:return "BOT-HEIGHT";
2223 case BotPathReduce: return "BOT-PATH ";
2224 case NextDefUse: return "DEF-USE ";
2225 case NodeOrder: return "ORDER ";
2227 llvm_unreachable("Unknown reason!");
2230 void GenericSchedulerBase::traceCandidate(const SchedCandidate &Cand) {
2232 unsigned ResIdx = 0;
2233 unsigned Latency = 0;
2234 switch (Cand.Reason) {
2238 P = Cand.RPDelta.Excess;
2241 P = Cand.RPDelta.CriticalMax;
2244 P = Cand.RPDelta.CurrentMax;
2246 case ResourceReduce:
2247 ResIdx = Cand.Policy.ReduceResIdx;
2249 case ResourceDemand:
2250 ResIdx = Cand.Policy.DemandResIdx;
2252 case TopDepthReduce:
2253 Latency = Cand.SU->getDepth();
2256 Latency = Cand.SU->getHeight();
2258 case BotHeightReduce:
2259 Latency = Cand.SU->getHeight();
2262 Latency = Cand.SU->getDepth();
2265 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason);
2267 dbgs() << " " << TRI->getRegPressureSetName(P.getPSet())
2268 << ":" << P.getUnitInc() << " ";
2272 dbgs() << " " << SchedModel->getProcResource(ResIdx)->Name << " ";
2276 dbgs() << " " << Latency << " cycles ";
2283 /// Return true if this heuristic determines order.
2284 static bool tryLess(int TryVal, int CandVal,
2285 GenericSchedulerBase::SchedCandidate &TryCand,
2286 GenericSchedulerBase::SchedCandidate &Cand,
2287 GenericSchedulerBase::CandReason Reason) {
2288 if (TryVal < CandVal) {
2289 TryCand.Reason = Reason;
2292 if (TryVal > CandVal) {
2293 if (Cand.Reason > Reason)
2294 Cand.Reason = Reason;
2297 Cand.setRepeat(Reason);
2301 static bool tryGreater(int TryVal, int CandVal,
2302 GenericSchedulerBase::SchedCandidate &TryCand,
2303 GenericSchedulerBase::SchedCandidate &Cand,
2304 GenericSchedulerBase::CandReason Reason) {
2305 if (TryVal > CandVal) {
2306 TryCand.Reason = Reason;
2309 if (TryVal < CandVal) {
2310 if (Cand.Reason > Reason)
2311 Cand.Reason = Reason;
2314 Cand.setRepeat(Reason);
2318 static bool tryLatency(GenericSchedulerBase::SchedCandidate &TryCand,
2319 GenericSchedulerBase::SchedCandidate &Cand,
2320 SchedBoundary &Zone) {
2322 if (Cand.SU->getDepth() > Zone.getScheduledLatency()) {
2323 if (tryLess(TryCand.SU->getDepth(), Cand.SU->getDepth(),
2324 TryCand, Cand, GenericSchedulerBase::TopDepthReduce))
2327 if (tryGreater(TryCand.SU->getHeight(), Cand.SU->getHeight(),
2328 TryCand, Cand, GenericSchedulerBase::TopPathReduce))
2332 if (Cand.SU->getHeight() > Zone.getScheduledLatency()) {
2333 if (tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(),
2334 TryCand, Cand, GenericSchedulerBase::BotHeightReduce))
2337 if (tryGreater(TryCand.SU->getDepth(), Cand.SU->getDepth(),
2338 TryCand, Cand, GenericSchedulerBase::BotPathReduce))
2344 static void tracePick(const GenericSchedulerBase::SchedCandidate &Cand,
2346 DEBUG(dbgs() << "Pick " << (IsTop ? "Top " : "Bot ")
2347 << GenericSchedulerBase::getReasonStr(Cand.Reason) << '\n');
2350 void GenericScheduler::initialize(ScheduleDAGMI *dag) {
2351 assert(dag->hasVRegLiveness() &&
2352 "(PreRA)GenericScheduler needs vreg liveness");
2353 DAG = static_cast<ScheduleDAGMILive*>(dag);
2354 SchedModel = DAG->getSchedModel();
2357 Rem.init(DAG, SchedModel);
2358 Top.init(DAG, SchedModel, &Rem);
2359 Bot.init(DAG, SchedModel, &Rem);
2361 // Initialize resource counts.
2363 // Initialize the HazardRecognizers. If itineraries don't exist, are empty, or
2364 // are disabled, then these HazardRecs will be disabled.
2365 const InstrItineraryData *Itin = SchedModel->getInstrItineraries();
2366 if (!Top.HazardRec) {
2368 DAG->MF.getSubtarget().getInstrInfo()->CreateTargetMIHazardRecognizer(
2371 if (!Bot.HazardRec) {
2373 DAG->MF.getSubtarget().getInstrInfo()->CreateTargetMIHazardRecognizer(
2378 /// Initialize the per-region scheduling policy.
2379 void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
2380 MachineBasicBlock::iterator End,
2381 unsigned NumRegionInstrs) {
2382 const MachineFunction &MF = *Begin->getParent()->getParent();
2383 const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
2385 // Avoid setting up the register pressure tracker for small regions to save
2386 // compile time. As a rough heuristic, only track pressure when the number of
2387 // schedulable instructions exceeds half the integer register file.
2388 RegionPolicy.ShouldTrackPressure = true;
2389 for (unsigned VT = MVT::i32; VT > (unsigned)MVT::i1; --VT) {
2390 MVT::SimpleValueType LegalIntVT = (MVT::SimpleValueType)VT;
2391 if (TLI->isTypeLegal(LegalIntVT)) {
2392 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs(
2393 TLI->getRegClassFor(LegalIntVT));
2394 RegionPolicy.ShouldTrackPressure = NumRegionInstrs > (NIntRegs / 2);
2398 // For generic targets, we default to bottom-up, because it's simpler and more
2399 // compile-time optimizations have been implemented in that direction.
2400 RegionPolicy.OnlyBottomUp = true;
2402 // Allow the subtarget to override default policy.
2403 MF.getSubtarget().overrideSchedPolicy(RegionPolicy, Begin, End,
2406 // After subtarget overrides, apply command line options.
2407 if (!EnableRegPressure)
2408 RegionPolicy.ShouldTrackPressure = false;
2410 // Check -misched-topdown/bottomup can force or unforce scheduling direction.
2411 // e.g. -misched-bottomup=false allows scheduling in both directions.
2412 assert((!ForceTopDown || !ForceBottomUp) &&
2413 "-misched-topdown incompatible with -misched-bottomup");
2414 if (ForceBottomUp.getNumOccurrences() > 0) {
2415 RegionPolicy.OnlyBottomUp = ForceBottomUp;
2416 if (RegionPolicy.OnlyBottomUp)
2417 RegionPolicy.OnlyTopDown = false;
2419 if (ForceTopDown.getNumOccurrences() > 0) {
2420 RegionPolicy.OnlyTopDown = ForceTopDown;
2421 if (RegionPolicy.OnlyTopDown)
2422 RegionPolicy.OnlyBottomUp = false;
2426 /// Set IsAcyclicLatencyLimited if the acyclic path is longer than the cyclic
2427 /// critical path by more cycles than it takes to drain the instruction buffer.
2428 /// We estimate an upper bounds on in-flight instructions as:
2430 /// CyclesPerIteration = max( CyclicPath, Loop-Resource-Height )
2431 /// InFlightIterations = AcyclicPath / CyclesPerIteration
2432 /// InFlightResources = InFlightIterations * LoopResources
2434 /// TODO: Check execution resources in addition to IssueCount.
2435 void GenericScheduler::checkAcyclicLatency() {
2436 if (Rem.CyclicCritPath == 0 || Rem.CyclicCritPath >= Rem.CriticalPath)
2439 // Scaled number of cycles per loop iteration.
2440 unsigned IterCount =
2441 std::max(Rem.CyclicCritPath * SchedModel->getLatencyFactor(),
2443 // Scaled acyclic critical path.
2444 unsigned AcyclicCount = Rem.CriticalPath * SchedModel->getLatencyFactor();
2445 // InFlightCount = (AcyclicPath / IterCycles) * InstrPerLoop
2446 unsigned InFlightCount =
2447 (AcyclicCount * Rem.RemIssueCount + IterCount-1) / IterCount;
2448 unsigned BufferLimit =
2449 SchedModel->getMicroOpBufferSize() * SchedModel->getMicroOpFactor();
2451 Rem.IsAcyclicLatencyLimited = InFlightCount > BufferLimit;
2453 DEBUG(dbgs() << "IssueCycles="
2454 << Rem.RemIssueCount / SchedModel->getLatencyFactor() << "c "
2455 << "IterCycles=" << IterCount / SchedModel->getLatencyFactor()
2456 << "c NumIters=" << (AcyclicCount + IterCount-1) / IterCount
2457 << " InFlight=" << InFlightCount / SchedModel->getMicroOpFactor()
2458 << "m BufferLim=" << SchedModel->getMicroOpBufferSize() << "m\n";
2459 if (Rem.IsAcyclicLatencyLimited)
2460 dbgs() << " ACYCLIC LATENCY LIMIT\n");
2463 void GenericScheduler::registerRoots() {
2464 Rem.CriticalPath = DAG->ExitSU.getDepth();
2466 // Some roots may not feed into ExitSU. Check all of them in case.
2467 for (std::vector<SUnit*>::const_iterator
2468 I = Bot.Available.begin(), E = Bot.Available.end(); I != E; ++I) {
2469 if ((*I)->getDepth() > Rem.CriticalPath)
2470 Rem.CriticalPath = (*I)->getDepth();
2472 DEBUG(dbgs() << "Critical Path(GS-RR ): " << Rem.CriticalPath << '\n');
2473 if (DumpCriticalPathLength) {
2474 errs() << "Critical Path(GS-RR ): " << Rem.CriticalPath << " \n";
2477 if (EnableCyclicPath) {
2478 Rem.CyclicCritPath = DAG->computeCyclicCriticalPath();
2479 checkAcyclicLatency();
2483 static bool tryPressure(const PressureChange &TryP,
2484 const PressureChange &CandP,
2485 GenericSchedulerBase::SchedCandidate &TryCand,
2486 GenericSchedulerBase::SchedCandidate &Cand,
2487 GenericSchedulerBase::CandReason Reason) {
2488 int TryRank = TryP.getPSetOrMax();
2489 int CandRank = CandP.getPSetOrMax();
2490 // If both candidates affect the same set, go with the smallest increase.
2491 if (TryRank == CandRank) {
2492 return tryLess(TryP.getUnitInc(), CandP.getUnitInc(), TryCand, Cand,
2495 // If one candidate decreases and the other increases, go with it.
2496 // Invalid candidates have UnitInc==0.
2497 if (tryGreater(TryP.getUnitInc() < 0, CandP.getUnitInc() < 0, TryCand, Cand,
2501 // If the candidates are decreasing pressure, reverse priority.
2502 if (TryP.getUnitInc() < 0)
2503 std::swap(TryRank, CandRank);
2504 return tryGreater(TryRank, CandRank, TryCand, Cand, Reason);
2507 static unsigned getWeakLeft(const SUnit *SU, bool isTop) {
2508 return (isTop) ? SU->WeakPredsLeft : SU->WeakSuccsLeft;
2511 /// Minimize physical register live ranges. Regalloc wants them adjacent to
2512 /// their physreg def/use.
2514 /// FIXME: This is an unnecessary check on the critical path. Most are root/leaf
2515 /// copies which can be prescheduled. The rest (e.g. x86 MUL) could be bundled
2516 /// with the operation that produces or consumes the physreg. We'll do this when
2517 /// regalloc has support for parallel copies.
2518 static int biasPhysRegCopy(const SUnit *SU, bool isTop) {
2519 const MachineInstr *MI = SU->getInstr();
2523 unsigned ScheduledOper = isTop ? 1 : 0;
2524 unsigned UnscheduledOper = isTop ? 0 : 1;
2525 // If we have already scheduled the physreg produce/consumer, immediately
2526 // schedule the copy.
2527 if (TargetRegisterInfo::isPhysicalRegister(
2528 MI->getOperand(ScheduledOper).getReg()))
2530 // If the physreg is at the boundary, defer it. Otherwise schedule it
2531 // immediately to free the dependent. We can hoist the copy later.
2532 bool AtBoundary = isTop ? !SU->NumSuccsLeft : !SU->NumPredsLeft;
2533 if (TargetRegisterInfo::isPhysicalRegister(
2534 MI->getOperand(UnscheduledOper).getReg()))
2535 return AtBoundary ? -1 : 1;
2539 /// Apply a set of heursitics to a new candidate. Heuristics are currently
2540 /// hierarchical. This may be more efficient than a graduated cost model because
2541 /// we don't need to evaluate all aspects of the model for each node in the
2542 /// queue. But it's really done to make the heuristics easier to debug and
2543 /// statistically analyze.
2545 /// \param Cand provides the policy and current best candidate.
2546 /// \param TryCand refers to the next SUnit candidate, otherwise uninitialized.
2547 /// \param Zone describes the scheduled zone that we are extending.
2548 /// \param RPTracker describes reg pressure within the scheduled zone.
2549 /// \param TempTracker is a scratch pressure tracker to reuse in queries.
2550 void GenericScheduler::tryCandidate(SchedCandidate &Cand,
2551 SchedCandidate &TryCand,
2552 SchedBoundary &Zone,
2553 const RegPressureTracker &RPTracker,
2554 RegPressureTracker &TempTracker) {
2556 if (DAG->isTrackingPressure()) {
2557 // Always initialize TryCand's RPDelta.
2559 TempTracker.getMaxDownwardPressureDelta(
2560 TryCand.SU->getInstr(),
2562 DAG->getRegionCriticalPSets(),
2563 DAG->getRegPressure().MaxSetPressure);
2566 if (VerifyScheduling) {
2567 TempTracker.getMaxUpwardPressureDelta(
2568 TryCand.SU->getInstr(),
2569 &DAG->getPressureDiff(TryCand.SU),
2571 DAG->getRegionCriticalPSets(),
2572 DAG->getRegPressure().MaxSetPressure);
2575 RPTracker.getUpwardPressureDelta(
2576 TryCand.SU->getInstr(),
2577 DAG->getPressureDiff(TryCand.SU),
2579 DAG->getRegionCriticalPSets(),
2580 DAG->getRegPressure().MaxSetPressure);
2584 DEBUG(if (TryCand.RPDelta.Excess.isValid())
2585 dbgs() << " SU(" << TryCand.SU->NodeNum << ") "
2586 << TRI->getRegPressureSetName(TryCand.RPDelta.Excess.getPSet())
2587 << ":" << TryCand.RPDelta.Excess.getUnitInc() << "\n");
2589 // Initialize the candidate if needed.
2590 if (!Cand.isValid()) {
2591 TryCand.Reason = NodeOrder;
2595 if (tryGreater(biasPhysRegCopy(TryCand.SU, Zone.isTop()),
2596 biasPhysRegCopy(Cand.SU, Zone.isTop()),
2597 TryCand, Cand, PhysRegCopy))
2600 // Avoid exceeding the target's limit. If signed PSetID is negative, it is
2601 // invalid; convert it to INT_MAX to give it lowest priority.
2602 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.Excess,
2603 Cand.RPDelta.Excess,
2604 TryCand, Cand, RegExcess))
2607 // Avoid increasing the max critical pressure in the scheduled region.
2608 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.CriticalMax,
2609 Cand.RPDelta.CriticalMax,
2610 TryCand, Cand, RegCritical))
2613 // For loops that are acyclic path limited, aggressively schedule for latency.
2614 // This can result in very long dependence chains scheduled in sequence, so
2615 // once every cycle (when CurrMOps == 0), switch to normal heuristics.
2616 if (Rem.IsAcyclicLatencyLimited && !Zone.getCurrMOps()
2617 && tryLatency(TryCand, Cand, Zone))
2620 // Prioritize instructions that read unbuffered resources by stall cycles.
2621 if (tryLess(Zone.getLatencyStallCycles(TryCand.SU),
2622 Zone.getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall))
2625 // Keep clustered nodes together to encourage downstream peephole
2626 // optimizations which may reduce resource requirements.
2628 // This is a best effort to set things up for a post-RA pass. Optimizations
2629 // like generating loads of multiple registers should ideally be done within
2630 // the scheduler pass by combining the loads during DAG postprocessing.
2631 const SUnit *NextClusterSU =
2632 Zone.isTop() ? DAG->getNextClusterSucc() : DAG->getNextClusterPred();
2633 if (tryGreater(TryCand.SU == NextClusterSU, Cand.SU == NextClusterSU,
2634 TryCand, Cand, Cluster))
2637 // Weak edges are for clustering and other constraints.
2638 if (tryLess(getWeakLeft(TryCand.SU, Zone.isTop()),
2639 getWeakLeft(Cand.SU, Zone.isTop()),
2640 TryCand, Cand, Weak)) {
2643 // Avoid increasing the max pressure of the entire region.
2644 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.CurrentMax,
2645 Cand.RPDelta.CurrentMax,
2646 TryCand, Cand, RegMax))
2649 // Avoid critical resource consumption and balance the schedule.
2650 TryCand.initResourceDelta(DAG, SchedModel);
2651 if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
2652 TryCand, Cand, ResourceReduce))
2654 if (tryGreater(TryCand.ResDelta.DemandedResources,
2655 Cand.ResDelta.DemandedResources,
2656 TryCand, Cand, ResourceDemand))
2659 // Avoid serializing long latency dependence chains.
2660 // For acyclic path limited loops, latency was already checked above.
2661 if (Cand.Policy.ReduceLatency && !Rem.IsAcyclicLatencyLimited
2662 && tryLatency(TryCand, Cand, Zone)) {
2666 // Prefer immediate defs/users of the last scheduled instruction. This is a
2667 // local pressure avoidance strategy that also makes the machine code
2669 if (tryGreater(Zone.isNextSU(TryCand.SU), Zone.isNextSU(Cand.SU),
2670 TryCand, Cand, NextDefUse))
2673 // Fall through to original instruction order.
2674 if ((Zone.isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum)
2675 || (!Zone.isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) {
2676 TryCand.Reason = NodeOrder;
2680 /// Pick the best candidate from the queue.
2682 /// TODO: getMaxPressureDelta results can be mostly cached for each SUnit during
2683 /// DAG building. To adjust for the current scheduling location we need to
2684 /// maintain the number of vreg uses remaining to be top-scheduled.
2685 void GenericScheduler::pickNodeFromQueue(SchedBoundary &Zone,
2686 const RegPressureTracker &RPTracker,
2687 SchedCandidate &Cand) {
2688 ReadyQueue &Q = Zone.Available;
2692 // getMaxPressureDelta temporarily modifies the tracker.
2693 RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker);
2695 for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
2697 SchedCandidate TryCand(Cand.Policy);
2699 tryCandidate(Cand, TryCand, Zone, RPTracker, TempTracker);
2700 if (TryCand.Reason != NoCand) {
2701 // Initialize resource delta if needed in case future heuristics query it.
2702 if (TryCand.ResDelta == SchedResourceDelta())
2703 TryCand.initResourceDelta(DAG, SchedModel);
2704 Cand.setBest(TryCand);
2705 DEBUG(traceCandidate(Cand));
2710 /// Pick the best candidate node from either the top or bottom queue.
2711 SUnit *GenericScheduler::pickNodeBidirectional(bool &IsTopNode) {
2712 // Schedule as far as possible in the direction of no choice. This is most
2713 // efficient, but also provides the best heuristics for CriticalPSets.
2714 if (SUnit *SU = Bot.pickOnlyChoice()) {
2716 DEBUG(dbgs() << "Pick Bot NOCAND\n");
2719 if (SUnit *SU = Top.pickOnlyChoice()) {
2721 DEBUG(dbgs() << "Pick Top NOCAND\n");
2724 CandPolicy NoPolicy;
2725 SchedCandidate BotCand(NoPolicy);
2726 SchedCandidate TopCand(NoPolicy);
2727 // Set the bottom-up policy based on the state of the current bottom zone and
2728 // the instructions outside the zone, including the top zone.
2729 setPolicy(BotCand.Policy, /*IsPostRA=*/false, Bot, &Top);
2730 // Set the top-down policy based on the state of the current top zone and
2731 // the instructions outside the zone, including the bottom zone.
2732 setPolicy(TopCand.Policy, /*IsPostRA=*/false, Top, &Bot);
2734 // Prefer bottom scheduling when heuristics are silent.
2735 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2736 assert(BotCand.Reason != NoCand && "failed to find the first candidate");
2738 // If either Q has a single candidate that provides the least increase in
2739 // Excess pressure, we can immediately schedule from that Q.
2741 // RegionCriticalPSets summarizes the pressure within the scheduled region and
2742 // affects picking from either Q. If scheduling in one direction must
2743 // increase pressure for one of the excess PSets, then schedule in that
2744 // direction first to provide more freedom in the other direction.
2745 if ((BotCand.Reason == RegExcess && !BotCand.isRepeat(RegExcess))
2746 || (BotCand.Reason == RegCritical
2747 && !BotCand.isRepeat(RegCritical)))
2750 tracePick(BotCand, IsTopNode);
2753 // Check if the top Q has a better candidate.
2754 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2755 assert(TopCand.Reason != NoCand && "failed to find the first candidate");
2757 // Choose the queue with the most important (lowest enum) reason.
2758 if (TopCand.Reason < BotCand.Reason) {
2760 tracePick(TopCand, IsTopNode);
2763 // Otherwise prefer the bottom candidate, in node order if all else failed.
2765 tracePick(BotCand, IsTopNode);
2769 /// Pick the best node to balance the schedule. Implements MachineSchedStrategy.
2770 SUnit *GenericScheduler::pickNode(bool &IsTopNode) {
2771 if (DAG->top() == DAG->bottom()) {
2772 assert(Top.Available.empty() && Top.Pending.empty() &&
2773 Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage");
2778 if (RegionPolicy.OnlyTopDown) {
2779 SU = Top.pickOnlyChoice();
2781 CandPolicy NoPolicy;
2782 SchedCandidate TopCand(NoPolicy);
2783 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2784 assert(TopCand.Reason != NoCand && "failed to find a candidate");
2785 tracePick(TopCand, true);
2790 else if (RegionPolicy.OnlyBottomUp) {
2791 SU = Bot.pickOnlyChoice();
2793 CandPolicy NoPolicy;
2794 SchedCandidate BotCand(NoPolicy);
2795 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2796 assert(BotCand.Reason != NoCand && "failed to find a candidate");
2797 tracePick(BotCand, false);
2803 SU = pickNodeBidirectional(IsTopNode);
2805 } while (SU->isScheduled);
2807 if (SU->isTopReady())
2808 Top.removeReady(SU);
2809 if (SU->isBottomReady())
2810 Bot.removeReady(SU);
2812 DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr());
2816 void GenericScheduler::reschedulePhysRegCopies(SUnit *SU, bool isTop) {
2818 MachineBasicBlock::iterator InsertPos = SU->getInstr();
2821 SmallVectorImpl<SDep> &Deps = isTop ? SU->Preds : SU->Succs;
2823 // Find already scheduled copies with a single physreg dependence and move
2824 // them just above the scheduled instruction.
2825 for (SmallVectorImpl<SDep>::iterator I = Deps.begin(), E = Deps.end();
2827 if (I->getKind() != SDep::Data || !TRI->isPhysicalRegister(I->getReg()))
2829 SUnit *DepSU = I->getSUnit();
2830 if (isTop ? DepSU->Succs.size() > 1 : DepSU->Preds.size() > 1)
2832 MachineInstr *Copy = DepSU->getInstr();
2833 if (!Copy->isCopy())
2835 DEBUG(dbgs() << " Rescheduling physreg copy ";
2836 I->getSUnit()->dump(DAG));
2837 DAG->moveInstruction(Copy, InsertPos);
2841 /// Update the scheduler's state after scheduling a node. This is the same node
2842 /// that was just returned by pickNode(). However, ScheduleDAGMILive needs to
2843 /// update it's state based on the current cycle before MachineSchedStrategy
2846 /// FIXME: Eventually, we may bundle physreg copies rather than rescheduling
2847 /// them here. See comments in biasPhysRegCopy.
2848 void GenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
2850 SU->TopReadyCycle = std::max(SU->TopReadyCycle, Top.getCurrCycle());
2852 if (SU->hasPhysRegUses)
2853 reschedulePhysRegCopies(SU, true);
2856 SU->BotReadyCycle = std::max(SU->BotReadyCycle, Bot.getCurrCycle());
2858 if (SU->hasPhysRegDefs)
2859 reschedulePhysRegCopies(SU, false);
2863 /// Create the standard converging machine scheduler. This will be used as the
2864 /// default scheduler if the target does not set a default.
2865 static ScheduleDAGInstrs *createGenericSchedLive(MachineSchedContext *C) {
2866 ScheduleDAGMILive *DAG = new ScheduleDAGMILive(C, make_unique<GenericScheduler>(C));
2867 // Register DAG post-processors.
2869 // FIXME: extend the mutation API to allow earlier mutations to instantiate
2870 // data and pass it to later mutations. Have a single mutation that gathers
2871 // the interesting nodes in one pass.
2872 DAG->addMutation(make_unique<CopyConstrain>(DAG->TII, DAG->TRI));
2873 if (EnableLoadCluster && DAG->TII->enableClusterLoads())
2874 DAG->addMutation(make_unique<LoadClusterMutation>(DAG->TII, DAG->TRI));
2875 if (EnableMacroFusion)
2876 DAG->addMutation(make_unique<MacroFusion>(DAG->TII));
2880 static MachineSchedRegistry
2881 GenericSchedRegistry("converge", "Standard converging scheduler.",
2882 createGenericSchedLive);
2884 //===----------------------------------------------------------------------===//
2885 // PostGenericScheduler - Generic PostRA implementation of MachineSchedStrategy.
2886 //===----------------------------------------------------------------------===//
2888 void PostGenericScheduler::initialize(ScheduleDAGMI *Dag) {
2890 SchedModel = DAG->getSchedModel();
2893 Rem.init(DAG, SchedModel);
2894 Top.init(DAG, SchedModel, &Rem);
2897 // Initialize the HazardRecognizers. If itineraries don't exist, are empty,
2898 // or are disabled, then these HazardRecs will be disabled.
2899 const InstrItineraryData *Itin = SchedModel->getInstrItineraries();
2900 if (!Top.HazardRec) {
2902 DAG->MF.getSubtarget().getInstrInfo()->CreateTargetMIHazardRecognizer(
2908 void PostGenericScheduler::registerRoots() {
2909 Rem.CriticalPath = DAG->ExitSU.getDepth();
2911 // Some roots may not feed into ExitSU. Check all of them in case.
2912 for (SmallVectorImpl<SUnit*>::const_iterator
2913 I = BotRoots.begin(), E = BotRoots.end(); I != E; ++I) {
2914 if ((*I)->getDepth() > Rem.CriticalPath)
2915 Rem.CriticalPath = (*I)->getDepth();
2917 DEBUG(dbgs() << "Critical Path: (PGS-RR) " << Rem.CriticalPath << '\n');
2918 if (DumpCriticalPathLength) {
2919 errs() << "Critical Path(PGS-RR ): " << Rem.CriticalPath << " \n";
2923 /// Apply a set of heursitics to a new candidate for PostRA scheduling.
2925 /// \param Cand provides the policy and current best candidate.
2926 /// \param TryCand refers to the next SUnit candidate, otherwise uninitialized.
2927 void PostGenericScheduler::tryCandidate(SchedCandidate &Cand,
2928 SchedCandidate &TryCand) {
2930 // Initialize the candidate if needed.
2931 if (!Cand.isValid()) {
2932 TryCand.Reason = NodeOrder;
2936 // Prioritize instructions that read unbuffered resources by stall cycles.
2937 if (tryLess(Top.getLatencyStallCycles(TryCand.SU),
2938 Top.getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall))
2941 // Avoid critical resource consumption and balance the schedule.
2942 if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
2943 TryCand, Cand, ResourceReduce))
2945 if (tryGreater(TryCand.ResDelta.DemandedResources,
2946 Cand.ResDelta.DemandedResources,
2947 TryCand, Cand, ResourceDemand))
2950 // Avoid serializing long latency dependence chains.
2951 if (Cand.Policy.ReduceLatency && tryLatency(TryCand, Cand, Top)) {
2955 // Fall through to original instruction order.
2956 if (TryCand.SU->NodeNum < Cand.SU->NodeNum)
2957 TryCand.Reason = NodeOrder;
2960 void PostGenericScheduler::pickNodeFromQueue(SchedCandidate &Cand) {
2961 ReadyQueue &Q = Top.Available;
2965 for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
2966 SchedCandidate TryCand(Cand.Policy);
2968 TryCand.initResourceDelta(DAG, SchedModel);
2969 tryCandidate(Cand, TryCand);
2970 if (TryCand.Reason != NoCand) {
2971 Cand.setBest(TryCand);
2972 DEBUG(traceCandidate(Cand));
2977 /// Pick the next node to schedule.
2978 SUnit *PostGenericScheduler::pickNode(bool &IsTopNode) {
2979 if (DAG->top() == DAG->bottom()) {
2980 assert(Top.Available.empty() && Top.Pending.empty() && "ReadyQ garbage");
2985 SU = Top.pickOnlyChoice();
2987 CandPolicy NoPolicy;
2988 SchedCandidate TopCand(NoPolicy);
2989 // Set the top-down policy based on the state of the current top zone and
2990 // the instructions outside the zone, including the bottom zone.
2991 setPolicy(TopCand.Policy, /*IsPostRA=*/true, Top, nullptr);
2992 pickNodeFromQueue(TopCand);
2993 assert(TopCand.Reason != NoCand && "failed to find a candidate");
2994 tracePick(TopCand, true);
2997 } while (SU->isScheduled);
3000 Top.removeReady(SU);
3002 DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr());
3006 /// Called after ScheduleDAGMI has scheduled an instruction and updated
3007 /// scheduled/remaining flags in the DAG nodes.
3008 void PostGenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
3009 SU->TopReadyCycle = std::max(SU->TopReadyCycle, Top.getCurrCycle());
3013 /// Create a generic scheduler with no vreg liveness or DAG mutation passes.
3014 static ScheduleDAGInstrs *createGenericSchedPostRA(MachineSchedContext *C) {
3015 return new ScheduleDAGMI(C, make_unique<PostGenericScheduler>(C), /*IsPostRA=*/true);
3018 //===----------------------------------------------------------------------===//
3019 // ILP Scheduler. Currently for experimental analysis of heuristics.
3020 //===----------------------------------------------------------------------===//
3023 /// \brief Order nodes by the ILP metric.
3025 const SchedDFSResult *DFSResult;
3026 const BitVector *ScheduledTrees;
3029 ILPOrder(bool MaxILP)
3030 : DFSResult(nullptr), ScheduledTrees(nullptr), MaximizeILP(MaxILP) {}
3032 /// \brief Apply a less-than relation on node priority.
3034 /// (Return true if A comes after B in the Q.)
3035 bool operator()(const SUnit *A, const SUnit *B) const {
3036 unsigned SchedTreeA = DFSResult->getSubtreeID(A);
3037 unsigned SchedTreeB = DFSResult->getSubtreeID(B);
3038 if (SchedTreeA != SchedTreeB) {
3039 // Unscheduled trees have lower priority.
3040 if (ScheduledTrees->test(SchedTreeA) != ScheduledTrees->test(SchedTreeB))
3041 return ScheduledTrees->test(SchedTreeB);
3043 // Trees with shallower connections have have lower priority.
3044 if (DFSResult->getSubtreeLevel(SchedTreeA)
3045 != DFSResult->getSubtreeLevel(SchedTreeB)) {
3046 return DFSResult->getSubtreeLevel(SchedTreeA)
3047 < DFSResult->getSubtreeLevel(SchedTreeB);
3051 return DFSResult->getILP(A) < DFSResult->getILP(B);
3053 return DFSResult->getILP(A) > DFSResult->getILP(B);
3057 /// \brief Schedule based on the ILP metric.
3058 class ILPScheduler : public MachineSchedStrategy {
3059 ScheduleDAGMILive *DAG;
3062 std::vector<SUnit*> ReadyQ;
3064 ILPScheduler(bool MaximizeILP): DAG(nullptr), Cmp(MaximizeILP) {}
3066 void initialize(ScheduleDAGMI *dag) override {
3067 assert(dag->hasVRegLiveness() && "ILPScheduler needs vreg liveness");
3068 DAG = static_cast<ScheduleDAGMILive*>(dag);
3069 DAG->computeDFSResult();
3070 Cmp.DFSResult = DAG->getDFSResult();
3071 Cmp.ScheduledTrees = &DAG->getScheduledTrees();
3075 void registerRoots() override {
3076 // Restore the heap in ReadyQ with the updated DFS results.
3077 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3080 /// Implement MachineSchedStrategy interface.
3081 /// -----------------------------------------
3083 /// Callback to select the highest priority node from the ready Q.
3084 SUnit *pickNode(bool &IsTopNode) override {
3085 if (ReadyQ.empty()) return nullptr;
3086 std::pop_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3087 SUnit *SU = ReadyQ.back();
3090 DEBUG(dbgs() << "Pick node " << "SU(" << SU->NodeNum << ") "
3091 << " ILP: " << DAG->getDFSResult()->getILP(SU)
3092 << " Tree: " << DAG->getDFSResult()->getSubtreeID(SU) << " @"
3093 << DAG->getDFSResult()->getSubtreeLevel(
3094 DAG->getDFSResult()->getSubtreeID(SU)) << '\n'
3095 << "Scheduling " << *SU->getInstr());
3099 /// \brief Scheduler callback to notify that a new subtree is scheduled.
3100 void scheduleTree(unsigned SubtreeID) override {
3101 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3104 /// Callback after a node is scheduled. Mark a newly scheduled tree, notify
3105 /// DFSResults, and resort the priority Q.
3106 void schedNode(SUnit *SU, bool IsTopNode) override {
3107 assert(!IsTopNode && "SchedDFSResult needs bottom-up");
3110 void releaseTopNode(SUnit *) override { /*only called for top roots*/ }
3112 void releaseBottomNode(SUnit *SU) override {
3113 ReadyQ.push_back(SU);
3114 std::push_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3119 static ScheduleDAGInstrs *createILPMaxScheduler(MachineSchedContext *C) {
3120 return new ScheduleDAGMILive(C, make_unique<ILPScheduler>(true));
3122 static ScheduleDAGInstrs *createILPMinScheduler(MachineSchedContext *C) {
3123 return new ScheduleDAGMILive(C, make_unique<ILPScheduler>(false));
3125 static MachineSchedRegistry ILPMaxRegistry(
3126 "ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler);
3127 static MachineSchedRegistry ILPMinRegistry(
3128 "ilpmin", "Schedule bottom-up for min ILP", createILPMinScheduler);
3130 //===----------------------------------------------------------------------===//
3131 // Machine Instruction Shuffler for Correctness Testing
3132 //===----------------------------------------------------------------------===//
3136 /// Apply a less-than relation on the node order, which corresponds to the
3137 /// instruction order prior to scheduling. IsReverse implements greater-than.
3138 template<bool IsReverse>
3140 bool operator()(SUnit *A, SUnit *B) const {
3142 return A->NodeNum > B->NodeNum;
3144 return A->NodeNum < B->NodeNum;
3148 /// Reorder instructions as much as possible.
3149 class InstructionShuffler : public MachineSchedStrategy {
3153 // Using a less-than relation (SUnitOrder<false>) for the TopQ priority
3154 // gives nodes with a higher number higher priority causing the latest
3155 // instructions to be scheduled first.
3156 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false> >
3158 // When scheduling bottom-up, use greater-than as the queue priority.
3159 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true> >
3162 InstructionShuffler(bool alternate, bool topdown)
3163 : IsAlternating(alternate), IsTopDown(topdown) {}
3165 void initialize(ScheduleDAGMI*) override {
3170 /// Implement MachineSchedStrategy interface.
3171 /// -----------------------------------------
3173 SUnit *pickNode(bool &IsTopNode) override {
3177 if (TopQ.empty()) return nullptr;
3180 } while (SU->isScheduled);
3185 if (BottomQ.empty()) return nullptr;
3188 } while (SU->isScheduled);
3192 IsTopDown = !IsTopDown;
3196 void schedNode(SUnit *SU, bool IsTopNode) override {}
3198 void releaseTopNode(SUnit *SU) override {
3201 void releaseBottomNode(SUnit *SU) override {
3207 static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
3208 bool Alternate = !ForceTopDown && !ForceBottomUp;
3209 bool TopDown = !ForceBottomUp;
3210 assert((TopDown || !ForceTopDown) &&
3211 "-misched-topdown incompatible with -misched-bottomup");
3212 return new ScheduleDAGMILive(C, make_unique<InstructionShuffler>(Alternate, TopDown));
3214 static MachineSchedRegistry ShufflerRegistry(
3215 "shuffle", "Shuffle machine instructions alternating directions",
3216 createInstructionShuffler);
3219 //===----------------------------------------------------------------------===//
3220 // GraphWriter support for ScheduleDAGMILive.
3221 //===----------------------------------------------------------------------===//
3226 template<> struct GraphTraits<
3227 ScheduleDAGMI*> : public GraphTraits<ScheduleDAG*> {};
3230 struct DOTGraphTraits<ScheduleDAGMI*> : public DefaultDOTGraphTraits {
3232 DOTGraphTraits (bool isSimple=false) : DefaultDOTGraphTraits(isSimple) {}
3234 static std::string getGraphName(const ScheduleDAG *G) {
3235 return G->MF.getName();
3238 static bool renderGraphFromBottomUp() {
3242 static bool isNodeHidden(const SUnit *Node) {
3243 return (Node->Preds.size() > 10 || Node->Succs.size() > 10);
3246 static bool hasNodeAddressLabel(const SUnit *Node,
3247 const ScheduleDAG *Graph) {
3251 /// If you want to override the dot attributes printed for a particular
3252 /// edge, override this method.
3253 static std::string getEdgeAttributes(const SUnit *Node,
3255 const ScheduleDAG *Graph) {
3256 if (EI.isArtificialDep())
3257 return "color=cyan,style=dashed";
3259 return "color=blue,style=dashed";
3263 static std::string getNodeLabel(const SUnit *SU, const ScheduleDAG *G) {
3265 raw_string_ostream SS(Str);
3266 const ScheduleDAGMI *DAG = static_cast<const ScheduleDAGMI*>(G);
3267 const SchedDFSResult *DFS = DAG->hasVRegLiveness() ?
3268 static_cast<const ScheduleDAGMILive*>(G)->getDFSResult() : nullptr;
3269 SS << "SU:" << SU->NodeNum;
3271 SS << " I:" << DFS->getNumInstrs(SU);
3274 static std::string getNodeDescription(const SUnit *SU, const ScheduleDAG *G) {
3275 return G->getGraphNodeLabel(SU);
3278 static std::string getNodeAttributes(const SUnit *N, const ScheduleDAG *G) {
3279 std::string Str("shape=Mrecord");
3280 const ScheduleDAGMI *DAG = static_cast<const ScheduleDAGMI*>(G);
3281 const SchedDFSResult *DFS = DAG->hasVRegLiveness() ?
3282 static_cast<const ScheduleDAGMILive*>(G)->getDFSResult() : nullptr;
3284 Str += ",style=filled,fillcolor=\"#";
3285 Str += DOT::getColorString(DFS->getSubtreeID(N));
3294 /// viewGraph - Pop up a ghostview window with the reachable parts of the DAG
3295 /// rendered using 'dot'.
3297 void ScheduleDAGMI::viewGraph(const Twine &Name, const Twine &Title) {
3299 ViewGraph(this, Name, false, Title);
3301 errs() << "ScheduleDAGMI::viewGraph is only available in debug builds on "
3302 << "systems with Graphviz or gv!\n";
3306 /// Out-of-line implementation with no arguments is handy for gdb.
3307 void ScheduleDAGMI::viewGraph() {
3308 viewGraph(getDAGName(), "Scheduling-Units Graph for " + getDAGName());