1 //===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MachineScheduler schedules machine instructions after phi elimination. It
11 // preserves LiveIntervals so it can be invoked before register allocation.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "misched"
17 #include "llvm/CodeGen/MachineScheduler.h"
18 #include "llvm/ADT/OwningPtr.h"
19 #include "llvm/ADT/PriorityQueue.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegisterClassInfo.h"
27 #include "llvm/CodeGen/ScheduleDFS.h"
28 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/GraphWriter.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetInstrInfo.h"
40 cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
41 cl::desc("Force top-down list scheduling"));
42 cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
43 cl::desc("Force bottom-up list scheduling"));
47 static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden,
48 cl::desc("Pop up a window to show MISched dags after they are processed"));
50 static cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden,
51 cl::desc("Stop scheduling after N instructions"), cl::init(~0U));
53 static bool ViewMISchedDAGs = false;
56 static cl::opt<bool> EnableRegPressure("misched-regpressure", cl::Hidden,
57 cl::desc("Enable register pressure scheduling."), cl::init(true));
59 static cl::opt<bool> EnableCyclicPath("misched-cyclicpath", cl::Hidden,
60 cl::desc("Enable cyclic critical path analysis."), cl::init(false));
62 static cl::opt<bool> EnableLoadCluster("misched-cluster", cl::Hidden,
63 cl::desc("Enable load clustering."), cl::init(true));
65 // Experimental heuristics
66 static cl::opt<bool> EnableMacroFusion("misched-fusion", cl::Hidden,
67 cl::desc("Enable scheduling for macro fusion."), cl::init(true));
69 static cl::opt<bool> VerifyScheduling("verify-misched", cl::Hidden,
70 cl::desc("Verify machine instrs before and after machine scheduling"));
72 // DAG subtrees must have at least this many nodes.
73 static const unsigned MinSubtreeSize = 8;
75 //===----------------------------------------------------------------------===//
76 // Machine Instruction Scheduling Pass and Registry
77 //===----------------------------------------------------------------------===//
79 MachineSchedContext::MachineSchedContext():
80 MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {
81 RegClassInfo = new RegisterClassInfo();
84 MachineSchedContext::~MachineSchedContext() {
89 /// MachineScheduler runs after coalescing and before register allocation.
90 class MachineScheduler : public MachineSchedContext,
91 public MachineFunctionPass {
95 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
97 virtual void releaseMemory() {}
99 virtual bool runOnMachineFunction(MachineFunction&);
101 virtual void print(raw_ostream &O, const Module* = 0) const;
103 static char ID; // Class identification, replacement for typeinfo
107 char MachineScheduler::ID = 0;
109 char &llvm::MachineSchedulerID = MachineScheduler::ID;
111 INITIALIZE_PASS_BEGIN(MachineScheduler, "misched",
112 "Machine Instruction Scheduler", false, false)
113 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
114 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
115 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
116 INITIALIZE_PASS_END(MachineScheduler, "misched",
117 "Machine Instruction Scheduler", false, false)
119 MachineScheduler::MachineScheduler()
120 : MachineFunctionPass(ID) {
121 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
124 void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
125 AU.setPreservesCFG();
126 AU.addRequiredID(MachineDominatorsID);
127 AU.addRequired<MachineLoopInfo>();
128 AU.addRequired<AliasAnalysis>();
129 AU.addRequired<TargetPassConfig>();
130 AU.addRequired<SlotIndexes>();
131 AU.addPreserved<SlotIndexes>();
132 AU.addRequired<LiveIntervals>();
133 AU.addPreserved<LiveIntervals>();
134 MachineFunctionPass::getAnalysisUsage(AU);
137 MachinePassRegistry MachineSchedRegistry::Registry;
139 /// A dummy default scheduler factory indicates whether the scheduler
140 /// is overridden on the command line.
141 static ScheduleDAGInstrs *useDefaultMachineSched(MachineSchedContext *C) {
145 /// MachineSchedOpt allows command line selection of the scheduler.
146 static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
147 RegisterPassParser<MachineSchedRegistry> >
148 MachineSchedOpt("misched",
149 cl::init(&useDefaultMachineSched), cl::Hidden,
150 cl::desc("Machine instruction scheduler to use"));
152 static MachineSchedRegistry
153 DefaultSchedRegistry("default", "Use the target's default scheduler choice.",
154 useDefaultMachineSched);
156 /// Forward declare the standard machine scheduler. This will be used as the
157 /// default scheduler if the target does not set a default.
158 static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C);
161 /// Decrement this iterator until reaching the top or a non-debug instr.
162 static MachineBasicBlock::const_iterator
163 priorNonDebug(MachineBasicBlock::const_iterator I,
164 MachineBasicBlock::const_iterator Beg) {
165 assert(I != Beg && "reached the top of the region, cannot decrement");
167 if (!I->isDebugValue())
173 /// Non-const version.
174 static MachineBasicBlock::iterator
175 priorNonDebug(MachineBasicBlock::iterator I,
176 MachineBasicBlock::const_iterator Beg) {
177 return const_cast<MachineInstr*>(
178 &*priorNonDebug(MachineBasicBlock::const_iterator(I), Beg));
181 /// If this iterator is a debug value, increment until reaching the End or a
182 /// non-debug instruction.
183 static MachineBasicBlock::const_iterator
184 nextIfDebug(MachineBasicBlock::const_iterator I,
185 MachineBasicBlock::const_iterator End) {
186 for(; I != End; ++I) {
187 if (!I->isDebugValue())
193 /// Non-const version.
194 static MachineBasicBlock::iterator
195 nextIfDebug(MachineBasicBlock::iterator I,
196 MachineBasicBlock::const_iterator End) {
197 // Cast the return value to nonconst MachineInstr, then cast to an
198 // instr_iterator, which does not check for null, finally return a
200 return MachineBasicBlock::instr_iterator(
201 const_cast<MachineInstr*>(
202 &*nextIfDebug(MachineBasicBlock::const_iterator(I), End)));
205 /// Top-level MachineScheduler pass driver.
207 /// Visit blocks in function order. Divide each block into scheduling regions
208 /// and visit them bottom-up. Visiting regions bottom-up is not required, but is
209 /// consistent with the DAG builder, which traverses the interior of the
210 /// scheduling regions bottom-up.
212 /// This design avoids exposing scheduling boundaries to the DAG builder,
213 /// simplifying the DAG builder's support for "special" target instructions.
214 /// At the same time the design allows target schedulers to operate across
215 /// scheduling boundaries, for example to bundle the boudary instructions
216 /// without reordering them. This creates complexity, because the target
217 /// scheduler must update the RegionBegin and RegionEnd positions cached by
218 /// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler
219 /// design would be to split blocks at scheduling boundaries, but LLVM has a
220 /// general bias against block splitting purely for implementation simplicity.
221 bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
222 DEBUG(dbgs() << "Before MISsched:\n"; mf.print(dbgs()));
224 // Initialize the context of the pass.
226 MLI = &getAnalysis<MachineLoopInfo>();
227 MDT = &getAnalysis<MachineDominatorTree>();
228 PassConfig = &getAnalysis<TargetPassConfig>();
229 AA = &getAnalysis<AliasAnalysis>();
231 LIS = &getAnalysis<LiveIntervals>();
232 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
234 if (VerifyScheduling) {
236 MF->verify(this, "Before machine scheduling.");
238 RegClassInfo->runOnMachineFunction(*MF);
240 // Select the scheduler, or set the default.
241 MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
242 if (Ctor == useDefaultMachineSched) {
243 // Get the default scheduler set by the target.
244 Ctor = MachineSchedRegistry::getDefault();
246 Ctor = createConvergingSched;
247 MachineSchedRegistry::setDefault(Ctor);
250 // Instantiate the selected scheduler.
251 OwningPtr<ScheduleDAGInstrs> Scheduler(Ctor(this));
253 // Visit all machine basic blocks.
255 // TODO: Visit blocks in global postorder or postorder within the bottom-up
256 // loop tree. Then we can optionally compute global RegPressure.
257 for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
258 MBB != MBBEnd; ++MBB) {
260 Scheduler->startBlock(MBB);
262 // Break the block into scheduling regions [I, RegionEnd), and schedule each
263 // region as soon as it is discovered. RegionEnd points the scheduling
264 // boundary at the bottom of the region. The DAG does not include RegionEnd,
265 // but the region does (i.e. the next RegionEnd is above the previous
266 // RegionBegin). If the current block has no terminator then RegionEnd ==
267 // MBB->end() for the bottom region.
269 // The Scheduler may insert instructions during either schedule() or
270 // exitRegion(), even for empty regions. So the local iterators 'I' and
271 // 'RegionEnd' are invalid across these calls.
272 unsigned RemainingInstrs = MBB->size();
273 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
274 RegionEnd != MBB->begin(); RegionEnd = Scheduler->begin()) {
276 // Avoid decrementing RegionEnd for blocks with no terminator.
277 if (RegionEnd != MBB->end()
278 || TII->isSchedulingBoundary(llvm::prior(RegionEnd), MBB, *MF)) {
280 // Count the boundary instruction.
284 // The next region starts above the previous region. Look backward in the
285 // instruction stream until we find the nearest boundary.
286 unsigned NumRegionInstrs = 0;
287 MachineBasicBlock::iterator I = RegionEnd;
288 for(;I != MBB->begin(); --I, --RemainingInstrs, ++NumRegionInstrs) {
289 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, *MF))
292 // Notify the scheduler of the region, even if we may skip scheduling
293 // it. Perhaps it still needs to be bundled.
294 Scheduler->enterRegion(MBB, I, RegionEnd, NumRegionInstrs);
296 // Skip empty scheduling regions (0 or 1 schedulable instructions).
297 if (I == RegionEnd || I == llvm::prior(RegionEnd)) {
298 // Close the current region. Bundle the terminator if needed.
299 // This invalidates 'RegionEnd' and 'I'.
300 Scheduler->exitRegion();
303 DEBUG(dbgs() << "********** MI Scheduling **********\n");
304 DEBUG(dbgs() << MF->getName()
305 << ":BB#" << MBB->getNumber() << " " << MBB->getName()
306 << "\n From: " << *I << " To: ";
307 if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
308 else dbgs() << "End";
309 dbgs() << " RegionInstrs: " << NumRegionInstrs
310 << " Remaining: " << RemainingInstrs << "\n");
312 // Schedule a region: possibly reorder instructions.
313 // This invalidates 'RegionEnd' and 'I'.
314 Scheduler->schedule();
316 // Close the current region.
317 Scheduler->exitRegion();
319 // Scheduling has invalidated the current iterator 'I'. Ask the
320 // scheduler for the top of it's scheduled region.
321 RegionEnd = Scheduler->begin();
323 assert(RemainingInstrs == 0 && "Instruction count mismatch!");
324 Scheduler->finishBlock();
326 Scheduler->finalizeSchedule();
328 if (VerifyScheduling)
329 MF->verify(this, "After machine scheduling.");
333 void MachineScheduler::print(raw_ostream &O, const Module* m) const {
337 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
338 void ReadyQueue::dump() {
339 dbgs() << Name << ": ";
340 for (unsigned i = 0, e = Queue.size(); i < e; ++i)
341 dbgs() << Queue[i]->NodeNum << " ";
346 //===----------------------------------------------------------------------===//
347 // ScheduleDAGMI - Base class for MachineInstr scheduling with LiveIntervals
349 //===----------------------------------------------------------------------===//
351 ScheduleDAGMI::~ScheduleDAGMI() {
353 DeleteContainerPointers(Mutations);
357 bool ScheduleDAGMI::canAddEdge(SUnit *SuccSU, SUnit *PredSU) {
358 return SuccSU == &ExitSU || !Topo.IsReachable(PredSU, SuccSU);
361 bool ScheduleDAGMI::addEdge(SUnit *SuccSU, const SDep &PredDep) {
362 if (SuccSU != &ExitSU) {
363 // Do not use WillCreateCycle, it assumes SD scheduling.
364 // If Pred is reachable from Succ, then the edge creates a cycle.
365 if (Topo.IsReachable(PredDep.getSUnit(), SuccSU))
367 Topo.AddPred(SuccSU, PredDep.getSUnit());
369 SuccSU->addPred(PredDep, /*Required=*/!PredDep.isArtificial());
370 // Return true regardless of whether a new edge needed to be inserted.
374 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
375 /// NumPredsLeft reaches zero, release the successor node.
377 /// FIXME: Adjust SuccSU height based on MinLatency.
378 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
379 SUnit *SuccSU = SuccEdge->getSUnit();
381 if (SuccEdge->isWeak()) {
382 --SuccSU->WeakPredsLeft;
383 if (SuccEdge->isCluster())
384 NextClusterSucc = SuccSU;
388 if (SuccSU->NumPredsLeft == 0) {
389 dbgs() << "*** Scheduling failed! ***\n";
391 dbgs() << " has been released too many times!\n";
395 --SuccSU->NumPredsLeft;
396 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
397 SchedImpl->releaseTopNode(SuccSU);
400 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
401 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
402 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
404 releaseSucc(SU, &*I);
408 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. When
409 /// NumSuccsLeft reaches zero, release the predecessor node.
411 /// FIXME: Adjust PredSU height based on MinLatency.
412 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
413 SUnit *PredSU = PredEdge->getSUnit();
415 if (PredEdge->isWeak()) {
416 --PredSU->WeakSuccsLeft;
417 if (PredEdge->isCluster())
418 NextClusterPred = PredSU;
422 if (PredSU->NumSuccsLeft == 0) {
423 dbgs() << "*** Scheduling failed! ***\n";
425 dbgs() << " has been released too many times!\n";
429 --PredSU->NumSuccsLeft;
430 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU)
431 SchedImpl->releaseBottomNode(PredSU);
434 /// releasePredecessors - Call releasePred on each of SU's predecessors.
435 void ScheduleDAGMI::releasePredecessors(SUnit *SU) {
436 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
438 releasePred(SU, &*I);
442 /// This is normally called from the main scheduler loop but may also be invoked
443 /// by the scheduling strategy to perform additional code motion.
444 void ScheduleDAGMI::moveInstruction(MachineInstr *MI,
445 MachineBasicBlock::iterator InsertPos) {
446 // Advance RegionBegin if the first instruction moves down.
447 if (&*RegionBegin == MI)
450 // Update the instruction stream.
451 BB->splice(InsertPos, BB, MI);
453 // Update LiveIntervals
454 LIS->handleMove(MI, /*UpdateFlags=*/true);
456 // Recede RegionBegin if an instruction moves above the first.
457 if (RegionBegin == InsertPos)
461 bool ScheduleDAGMI::checkSchedLimit() {
463 if (NumInstrsScheduled == MISchedCutoff && MISchedCutoff != ~0U) {
464 CurrentTop = CurrentBottom;
467 ++NumInstrsScheduled;
472 /// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
473 /// crossing a scheduling boundary. [begin, end) includes all instructions in
474 /// the region, including the boundary itself and single-instruction regions
475 /// that don't get scheduled.
476 void ScheduleDAGMI::enterRegion(MachineBasicBlock *bb,
477 MachineBasicBlock::iterator begin,
478 MachineBasicBlock::iterator end,
479 unsigned regioninstrs)
481 ScheduleDAGInstrs::enterRegion(bb, begin, end, regioninstrs);
483 // For convenience remember the end of the liveness region.
485 (RegionEnd == bb->end()) ? RegionEnd : llvm::next(RegionEnd);
487 SchedImpl->initPolicy(begin, end, regioninstrs);
489 ShouldTrackPressure = SchedImpl->shouldTrackPressure();
492 // Setup the register pressure trackers for the top scheduled top and bottom
493 // scheduled regions.
494 void ScheduleDAGMI::initRegPressure() {
495 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin);
496 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
498 // Close the RPTracker to finalize live ins.
499 RPTracker.closeRegion();
501 DEBUG(RPTracker.dump());
503 // Initialize the live ins and live outs.
504 TopRPTracker.addLiveRegs(RPTracker.getPressure().LiveInRegs);
505 BotRPTracker.addLiveRegs(RPTracker.getPressure().LiveOutRegs);
507 // Close one end of the tracker so we can call
508 // getMaxUpward/DownwardPressureDelta before advancing across any
509 // instructions. This converts currently live regs into live ins/outs.
510 TopRPTracker.closeTop();
511 BotRPTracker.closeBottom();
513 BotRPTracker.initLiveThru(RPTracker);
514 if (!BotRPTracker.getLiveThru().empty()) {
515 TopRPTracker.initLiveThru(BotRPTracker.getLiveThru());
516 DEBUG(dbgs() << "Live Thru: ";
517 dumpRegSetPressure(BotRPTracker.getLiveThru(), TRI));
520 // For each live out vreg reduce the pressure change associated with other
521 // uses of the same vreg below the live-out reaching def.
522 updatePressureDiffs(RPTracker.getPressure().LiveOutRegs);
524 // Account for liveness generated by the region boundary.
525 if (LiveRegionEnd != RegionEnd) {
526 SmallVector<unsigned, 8> LiveUses;
527 BotRPTracker.recede(&LiveUses);
528 updatePressureDiffs(LiveUses);
531 assert(BotRPTracker.getPos() == RegionEnd && "Can't find the region bottom");
533 // Cache the list of excess pressure sets in this region. This will also track
534 // the max pressure in the scheduled code for these sets.
535 RegionCriticalPSets.clear();
536 const std::vector<unsigned> &RegionPressure =
537 RPTracker.getPressure().MaxSetPressure;
538 for (unsigned i = 0, e = RegionPressure.size(); i < e; ++i) {
539 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i);
540 if (RegionPressure[i] > Limit) {
541 DEBUG(dbgs() << TRI->getRegPressureSetName(i)
542 << " Limit " << Limit
543 << " Actual " << RegionPressure[i] << "\n");
544 RegionCriticalPSets.push_back(PressureChange(i));
547 DEBUG(dbgs() << "Excess PSets: ";
548 for (unsigned i = 0, e = RegionCriticalPSets.size(); i != e; ++i)
549 dbgs() << TRI->getRegPressureSetName(
550 RegionCriticalPSets[i].getPSet()) << " ";
554 // FIXME: When the pressure tracker deals in pressure differences then we won't
555 // iterate over all RegionCriticalPSets[i].
557 updateScheduledPressure(const std::vector<unsigned> &NewMaxPressure) {
558 for (unsigned i = 0, e = RegionCriticalPSets.size(); i < e; ++i) {
559 unsigned ID = RegionCriticalPSets[i].getPSet();
560 if ((int)NewMaxPressure[ID] > RegionCriticalPSets[i].getUnitInc()
561 && NewMaxPressure[ID] <= INT16_MAX)
562 RegionCriticalPSets[i].setUnitInc(NewMaxPressure[ID]);
565 for (unsigned i = 0, e = NewMaxPressure.size(); i < e; ++i) {
566 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i);
567 if (NewMaxPressure[i] > Limit ) {
568 dbgs() << " " << TRI->getRegPressureSetName(i) << ": "
569 << NewMaxPressure[i] << " > " << Limit << "\n";
574 /// Update the PressureDiff array for liveness after scheduling this
576 void ScheduleDAGMI::updatePressureDiffs(ArrayRef<unsigned> LiveUses) {
577 for (unsigned LUIdx = 0, LUEnd = LiveUses.size(); LUIdx != LUEnd; ++LUIdx) {
578 /// FIXME: Currently assuming single-use physregs.
579 unsigned Reg = LiveUses[LUIdx];
580 if (!TRI->isVirtualRegister(Reg))
582 // This may be called before CurrentBottom has been initialized. However,
583 // BotRPTracker must have a valid position. We want the value live into the
584 // instruction or live out of the block, so ask for the previous
585 // instruction's live-out.
586 const LiveInterval &LI = LIS->getInterval(Reg);
588 MachineBasicBlock::const_iterator I =
589 nextIfDebug(BotRPTracker.getPos(), BB->end());
591 VNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
593 LiveRangeQuery LRQ(LI, LIS->getInstructionIndex(I));
596 // RegisterPressureTracker guarantees that readsReg is true for LiveUses.
597 assert(VNI && "No live value at use.");
598 for (VReg2UseMap::iterator
599 UI = VRegUses.find(Reg); UI != VRegUses.end(); ++UI) {
601 // If this use comes before the reaching def, it cannot be a last use, so
602 // descrease its pressure change.
603 if (!SU->isScheduled && SU != &ExitSU) {
604 LiveRangeQuery LRQ(LI, LIS->getInstructionIndex(SU->getInstr()));
605 if (LRQ.valueIn() == VNI)
606 getPressureDiff(SU).addPressureChange(Reg, true, &MRI);
612 /// schedule - Called back from MachineScheduler::runOnMachineFunction
613 /// after setting up the current scheduling region. [RegionBegin, RegionEnd)
614 /// only includes instructions that have DAG nodes, not scheduling boundaries.
616 /// This is a skeletal driver, with all the functionality pushed into helpers,
617 /// so that it can be easilly extended by experimental schedulers. Generally,
618 /// implementing MachineSchedStrategy should be sufficient to implement a new
619 /// scheduling algorithm. However, if a scheduler further subclasses
620 /// ScheduleDAGMI then it will want to override this virtual method in order to
621 /// update any specialized state.
622 void ScheduleDAGMI::schedule() {
623 buildDAGWithRegPressure();
625 Topo.InitDAGTopologicalSorting();
629 SmallVector<SUnit*, 8> TopRoots, BotRoots;
630 findRootsAndBiasEdges(TopRoots, BotRoots);
632 // Initialize the strategy before modifying the DAG.
633 // This may initialize a DFSResult to be used for queue priority.
634 SchedImpl->initialize(this);
636 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
637 SUnits[su].dumpAll(this));
638 if (ViewMISchedDAGs) viewGraph();
640 // Initialize ready queues now that the DAG and priority data are finalized.
641 initQueues(TopRoots, BotRoots);
643 bool IsTopNode = false;
644 while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) {
645 assert(!SU->isScheduled && "Node already scheduled");
646 if (!checkSchedLimit())
649 scheduleMI(SU, IsTopNode);
651 updateQueues(SU, IsTopNode);
653 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
658 unsigned BBNum = begin()->getParent()->getNumber();
659 dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
665 /// Build the DAG and setup three register pressure trackers.
666 void ScheduleDAGMI::buildDAGWithRegPressure() {
667 if (!ShouldTrackPressure) {
669 RegionCriticalPSets.clear();
674 // Initialize the register pressure tracker used by buildSchedGraph.
675 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd,
676 /*TrackUntiedDefs=*/true);
678 // Account for liveness generate by the region boundary.
679 if (LiveRegionEnd != RegionEnd)
682 // Build the DAG, and compute current register pressure.
683 buildSchedGraph(AA, &RPTracker, &SUPressureDiffs);
685 // Initialize top/bottom trackers after computing region pressure.
689 /// Apply each ScheduleDAGMutation step in order.
690 void ScheduleDAGMI::postprocessDAG() {
691 for (unsigned i = 0, e = Mutations.size(); i < e; ++i) {
692 Mutations[i]->apply(this);
696 void ScheduleDAGMI::computeDFSResult() {
698 DFSResult = new SchedDFSResult(/*BottomU*/true, MinSubtreeSize);
700 ScheduledTrees.clear();
701 DFSResult->resize(SUnits.size());
702 DFSResult->compute(SUnits);
703 ScheduledTrees.resize(DFSResult->getNumSubtrees());
706 void ScheduleDAGMI::findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots,
707 SmallVectorImpl<SUnit*> &BotRoots) {
708 for (std::vector<SUnit>::iterator
709 I = SUnits.begin(), E = SUnits.end(); I != E; ++I) {
711 assert(!SU->isBoundaryNode() && "Boundary node should not be in SUnits");
713 // Order predecessors so DFSResult follows the critical path.
714 SU->biasCriticalPath();
716 // A SUnit is ready to top schedule if it has no predecessors.
717 if (!I->NumPredsLeft)
718 TopRoots.push_back(SU);
719 // A SUnit is ready to bottom schedule if it has no successors.
720 if (!I->NumSuccsLeft)
721 BotRoots.push_back(SU);
723 ExitSU.biasCriticalPath();
726 /// Compute the max cyclic critical path through the DAG. The scheduling DAG
727 /// only provides the critical path for single block loops. To handle loops that
728 /// span blocks, we could use the vreg path latencies provided by
729 /// MachineTraceMetrics instead. However, MachineTraceMetrics is not currently
730 /// available for use in the scheduler.
732 /// The cyclic path estimation identifies a def-use pair that crosses the back
733 /// edge and considers the depth and height of the nodes. For example, consider
734 /// the following instruction sequence where each instruction has unit latency
735 /// and defines an epomymous virtual register:
737 /// a->b(a,c)->c(b)->d(c)->exit
739 /// The cyclic critical path is a two cycles: b->c->b
740 /// The acyclic critical path is four cycles: a->b->c->d->exit
741 /// LiveOutHeight = height(c) = len(c->d->exit) = 2
742 /// LiveOutDepth = depth(c) + 1 = len(a->b->c) + 1 = 3
743 /// LiveInHeight = height(b) + 1 = len(b->c->d->exit) + 1 = 4
744 /// LiveInDepth = depth(b) = len(a->b) = 1
746 /// LiveOutDepth - LiveInDepth = 3 - 1 = 2
747 /// LiveInHeight - LiveOutHeight = 4 - 2 = 2
748 /// CyclicCriticalPath = min(2, 2) = 2
749 unsigned ScheduleDAGMI::computeCyclicCriticalPath() {
750 // This only applies to single block loop.
751 if (!BB->isSuccessor(BB))
754 unsigned MaxCyclicLatency = 0;
755 // Visit each live out vreg def to find def/use pairs that cross iterations.
756 ArrayRef<unsigned> LiveOuts = RPTracker.getPressure().LiveOutRegs;
757 for (ArrayRef<unsigned>::iterator RI = LiveOuts.begin(), RE = LiveOuts.end();
760 if (!TRI->isVirtualRegister(Reg))
762 const LiveInterval &LI = LIS->getInterval(Reg);
763 const VNInfo *DefVNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
767 MachineInstr *DefMI = LIS->getInstructionFromIndex(DefVNI->def);
768 const SUnit *DefSU = getSUnit(DefMI);
772 unsigned LiveOutHeight = DefSU->getHeight();
773 unsigned LiveOutDepth = DefSU->getDepth() + DefSU->Latency;
774 // Visit all local users of the vreg def.
775 for (VReg2UseMap::iterator
776 UI = VRegUses.find(Reg); UI != VRegUses.end(); ++UI) {
777 if (UI->SU == &ExitSU)
780 // Only consider uses of the phi.
781 LiveRangeQuery LRQ(LI, LIS->getInstructionIndex(UI->SU->getInstr()));
782 if (!LRQ.valueIn()->isPHIDef())
785 // Assume that a path spanning two iterations is a cycle, which could
786 // overestimate in strange cases. This allows cyclic latency to be
787 // estimated as the minimum slack of the vreg's depth or height.
788 unsigned CyclicLatency = 0;
789 if (LiveOutDepth > UI->SU->getDepth())
790 CyclicLatency = LiveOutDepth - UI->SU->getDepth();
792 unsigned LiveInHeight = UI->SU->getHeight() + DefSU->Latency;
793 if (LiveInHeight > LiveOutHeight) {
794 if (LiveInHeight - LiveOutHeight < CyclicLatency)
795 CyclicLatency = LiveInHeight - LiveOutHeight;
800 DEBUG(dbgs() << "Cyclic Path: SU(" << DefSU->NodeNum << ") -> SU("
801 << UI->SU->NodeNum << ") = " << CyclicLatency << "c\n");
802 if (CyclicLatency > MaxCyclicLatency)
803 MaxCyclicLatency = CyclicLatency;
806 DEBUG(dbgs() << "Cyclic Critical Path: " << MaxCyclicLatency << "c\n");
807 return MaxCyclicLatency;
810 /// Identify DAG roots and setup scheduler queues.
811 void ScheduleDAGMI::initQueues(ArrayRef<SUnit*> TopRoots,
812 ArrayRef<SUnit*> BotRoots) {
813 NextClusterSucc = NULL;
814 NextClusterPred = NULL;
816 // Release all DAG roots for scheduling, not including EntrySU/ExitSU.
818 // Nodes with unreleased weak edges can still be roots.
819 // Release top roots in forward order.
820 for (SmallVectorImpl<SUnit*>::const_iterator
821 I = TopRoots.begin(), E = TopRoots.end(); I != E; ++I) {
822 SchedImpl->releaseTopNode(*I);
824 // Release bottom roots in reverse order so the higher priority nodes appear
825 // first. This is more natural and slightly more efficient.
826 for (SmallVectorImpl<SUnit*>::const_reverse_iterator
827 I = BotRoots.rbegin(), E = BotRoots.rend(); I != E; ++I) {
828 SchedImpl->releaseBottomNode(*I);
831 releaseSuccessors(&EntrySU);
832 releasePredecessors(&ExitSU);
834 SchedImpl->registerRoots();
836 // Advance past initial DebugValues.
837 CurrentTop = nextIfDebug(RegionBegin, RegionEnd);
838 CurrentBottom = RegionEnd;
840 if (ShouldTrackPressure) {
841 assert(TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker");
842 TopRPTracker.setPos(CurrentTop);
846 /// Move an instruction and update register pressure.
847 void ScheduleDAGMI::scheduleMI(SUnit *SU, bool IsTopNode) {
848 // Move the instruction to its new location in the instruction stream.
849 MachineInstr *MI = SU->getInstr();
852 assert(SU->isTopReady() && "node still has unscheduled dependencies");
853 if (&*CurrentTop == MI)
854 CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);
856 moveInstruction(MI, CurrentTop);
857 TopRPTracker.setPos(MI);
860 if (ShouldTrackPressure) {
861 // Update top scheduled pressure.
862 TopRPTracker.advance();
863 assert(TopRPTracker.getPos() == CurrentTop && "out of sync");
864 updateScheduledPressure(TopRPTracker.getPressure().MaxSetPressure);
868 assert(SU->isBottomReady() && "node still has unscheduled dependencies");
869 MachineBasicBlock::iterator priorII =
870 priorNonDebug(CurrentBottom, CurrentTop);
872 CurrentBottom = priorII;
874 if (&*CurrentTop == MI) {
875 CurrentTop = nextIfDebug(++CurrentTop, priorII);
876 TopRPTracker.setPos(CurrentTop);
878 moveInstruction(MI, CurrentBottom);
881 if (ShouldTrackPressure) {
882 // Update bottom scheduled pressure.
883 SmallVector<unsigned, 8> LiveUses;
884 BotRPTracker.recede(&LiveUses);
885 assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
886 updatePressureDiffs(LiveUses);
887 updateScheduledPressure(BotRPTracker.getPressure().MaxSetPressure);
892 /// Update scheduler queues after scheduling an instruction.
893 void ScheduleDAGMI::updateQueues(SUnit *SU, bool IsTopNode) {
894 // Release dependent instructions for scheduling.
896 releaseSuccessors(SU);
898 releasePredecessors(SU);
900 SU->isScheduled = true;
903 unsigned SubtreeID = DFSResult->getSubtreeID(SU);
904 if (!ScheduledTrees.test(SubtreeID)) {
905 ScheduledTrees.set(SubtreeID);
906 DFSResult->scheduleTree(SubtreeID);
907 SchedImpl->scheduleTree(SubtreeID);
911 // Notify the scheduling strategy after updating the DAG.
912 SchedImpl->schedNode(SU, IsTopNode);
915 /// Reinsert any remaining debug_values, just like the PostRA scheduler.
916 void ScheduleDAGMI::placeDebugValues() {
917 // If first instruction was a DBG_VALUE then put it back.
919 BB->splice(RegionBegin, BB, FirstDbgValue);
920 RegionBegin = FirstDbgValue;
923 for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
924 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
925 std::pair<MachineInstr *, MachineInstr *> P = *prior(DI);
926 MachineInstr *DbgValue = P.first;
927 MachineBasicBlock::iterator OrigPrevMI = P.second;
928 if (&*RegionBegin == DbgValue)
930 BB->splice(++OrigPrevMI, BB, DbgValue);
931 if (OrigPrevMI == llvm::prior(RegionEnd))
932 RegionEnd = DbgValue;
935 FirstDbgValue = NULL;
938 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
939 void ScheduleDAGMI::dumpSchedule() const {
940 for (MachineBasicBlock::iterator MI = begin(), ME = end(); MI != ME; ++MI) {
941 if (SUnit *SU = getSUnit(&(*MI)))
944 dbgs() << "Missing SUnit\n";
949 //===----------------------------------------------------------------------===//
950 // LoadClusterMutation - DAG post-processing to cluster loads.
951 //===----------------------------------------------------------------------===//
954 /// \brief Post-process the DAG to create cluster edges between neighboring
956 class LoadClusterMutation : public ScheduleDAGMutation {
961 LoadInfo(SUnit *su, unsigned reg, unsigned ofs)
962 : SU(su), BaseReg(reg), Offset(ofs) {}
964 static bool LoadInfoLess(const LoadClusterMutation::LoadInfo &LHS,
965 const LoadClusterMutation::LoadInfo &RHS);
967 const TargetInstrInfo *TII;
968 const TargetRegisterInfo *TRI;
970 LoadClusterMutation(const TargetInstrInfo *tii,
971 const TargetRegisterInfo *tri)
972 : TII(tii), TRI(tri) {}
974 virtual void apply(ScheduleDAGMI *DAG);
976 void clusterNeighboringLoads(ArrayRef<SUnit*> Loads, ScheduleDAGMI *DAG);
980 bool LoadClusterMutation::LoadInfoLess(
981 const LoadClusterMutation::LoadInfo &LHS,
982 const LoadClusterMutation::LoadInfo &RHS) {
983 if (LHS.BaseReg != RHS.BaseReg)
984 return LHS.BaseReg < RHS.BaseReg;
985 return LHS.Offset < RHS.Offset;
988 void LoadClusterMutation::clusterNeighboringLoads(ArrayRef<SUnit*> Loads,
989 ScheduleDAGMI *DAG) {
990 SmallVector<LoadClusterMutation::LoadInfo,32> LoadRecords;
991 for (unsigned Idx = 0, End = Loads.size(); Idx != End; ++Idx) {
992 SUnit *SU = Loads[Idx];
995 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
996 LoadRecords.push_back(LoadInfo(SU, BaseReg, Offset));
998 if (LoadRecords.size() < 2)
1000 std::sort(LoadRecords.begin(), LoadRecords.end(), LoadInfoLess);
1001 unsigned ClusterLength = 1;
1002 for (unsigned Idx = 0, End = LoadRecords.size(); Idx < (End - 1); ++Idx) {
1003 if (LoadRecords[Idx].BaseReg != LoadRecords[Idx+1].BaseReg) {
1008 SUnit *SUa = LoadRecords[Idx].SU;
1009 SUnit *SUb = LoadRecords[Idx+1].SU;
1010 if (TII->shouldClusterLoads(SUa->getInstr(), SUb->getInstr(), ClusterLength)
1011 && DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
1013 DEBUG(dbgs() << "Cluster loads SU(" << SUa->NodeNum << ") - SU("
1014 << SUb->NodeNum << ")\n");
1015 // Copy successor edges from SUa to SUb. Interleaving computation
1016 // dependent on SUa can prevent load combining due to register reuse.
1017 // Predecessor edges do not need to be copied from SUb to SUa since nearby
1018 // loads should have effectively the same inputs.
1019 for (SUnit::const_succ_iterator
1020 SI = SUa->Succs.begin(), SE = SUa->Succs.end(); SI != SE; ++SI) {
1021 if (SI->getSUnit() == SUb)
1023 DEBUG(dbgs() << " Copy Succ SU(" << SI->getSUnit()->NodeNum << ")\n");
1024 DAG->addEdge(SI->getSUnit(), SDep(SUb, SDep::Artificial));
1033 /// \brief Callback from DAG postProcessing to create cluster edges for loads.
1034 void LoadClusterMutation::apply(ScheduleDAGMI *DAG) {
1035 // Map DAG NodeNum to store chain ID.
1036 DenseMap<unsigned, unsigned> StoreChainIDs;
1037 // Map each store chain to a set of dependent loads.
1038 SmallVector<SmallVector<SUnit*,4>, 32> StoreChainDependents;
1039 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
1040 SUnit *SU = &DAG->SUnits[Idx];
1041 if (!SU->getInstr()->mayLoad())
1043 unsigned ChainPredID = DAG->SUnits.size();
1044 for (SUnit::const_pred_iterator
1045 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) {
1047 ChainPredID = PI->getSUnit()->NodeNum;
1051 // Check if this chain-like pred has been seen
1052 // before. ChainPredID==MaxNodeID for loads at the top of the schedule.
1053 unsigned NumChains = StoreChainDependents.size();
1054 std::pair<DenseMap<unsigned, unsigned>::iterator, bool> Result =
1055 StoreChainIDs.insert(std::make_pair(ChainPredID, NumChains));
1057 StoreChainDependents.resize(NumChains + 1);
1058 StoreChainDependents[Result.first->second].push_back(SU);
1060 // Iterate over the store chains.
1061 for (unsigned Idx = 0, End = StoreChainDependents.size(); Idx != End; ++Idx)
1062 clusterNeighboringLoads(StoreChainDependents[Idx], DAG);
1065 //===----------------------------------------------------------------------===//
1066 // MacroFusion - DAG post-processing to encourage fusion of macro ops.
1067 //===----------------------------------------------------------------------===//
1070 /// \brief Post-process the DAG to create cluster edges between instructions
1071 /// that may be fused by the processor into a single operation.
1072 class MacroFusion : public ScheduleDAGMutation {
1073 const TargetInstrInfo *TII;
1075 MacroFusion(const TargetInstrInfo *tii): TII(tii) {}
1077 virtual void apply(ScheduleDAGMI *DAG);
1081 /// \brief Callback from DAG postProcessing to create cluster edges to encourage
1082 /// fused operations.
1083 void MacroFusion::apply(ScheduleDAGMI *DAG) {
1084 // For now, assume targets can only fuse with the branch.
1085 MachineInstr *Branch = DAG->ExitSU.getInstr();
1089 for (unsigned Idx = DAG->SUnits.size(); Idx > 0;) {
1090 SUnit *SU = &DAG->SUnits[--Idx];
1091 if (!TII->shouldScheduleAdjacent(SU->getInstr(), Branch))
1094 // Create a single weak edge from SU to ExitSU. The only effect is to cause
1095 // bottom-up scheduling to heavily prioritize the clustered SU. There is no
1096 // need to copy predecessor edges from ExitSU to SU, since top-down
1097 // scheduling cannot prioritize ExitSU anyway. To defer top-down scheduling
1098 // of SU, we could create an artificial edge from the deepest root, but it
1099 // hasn't been needed yet.
1100 bool Success = DAG->addEdge(&DAG->ExitSU, SDep(SU, SDep::Cluster));
1102 assert(Success && "No DAG nodes should be reachable from ExitSU");
1104 DEBUG(dbgs() << "Macro Fuse SU(" << SU->NodeNum << ")\n");
1109 //===----------------------------------------------------------------------===//
1110 // CopyConstrain - DAG post-processing to encourage copy elimination.
1111 //===----------------------------------------------------------------------===//
1114 /// \brief Post-process the DAG to create weak edges from all uses of a copy to
1115 /// the one use that defines the copy's source vreg, most likely an induction
1116 /// variable increment.
1117 class CopyConstrain : public ScheduleDAGMutation {
1119 SlotIndex RegionBeginIdx;
1120 // RegionEndIdx is the slot index of the last non-debug instruction in the
1121 // scheduling region. So we may have RegionBeginIdx == RegionEndIdx.
1122 SlotIndex RegionEndIdx;
1124 CopyConstrain(const TargetInstrInfo *, const TargetRegisterInfo *) {}
1126 virtual void apply(ScheduleDAGMI *DAG);
1129 void constrainLocalCopy(SUnit *CopySU, ScheduleDAGMI *DAG);
1133 /// constrainLocalCopy handles two possibilities:
1138 /// I3: dst = src (copy)
1139 /// (create pred->succ edges I0->I1, I2->I1)
1142 /// I0: dst = src (copy)
1146 /// (create pred->succ edges I1->I2, I3->I2)
1148 /// Although the MachineScheduler is currently constrained to single blocks,
1149 /// this algorithm should handle extended blocks. An EBB is a set of
1150 /// contiguously numbered blocks such that the previous block in the EBB is
1151 /// always the single predecessor.
1152 void CopyConstrain::constrainLocalCopy(SUnit *CopySU, ScheduleDAGMI *DAG) {
1153 LiveIntervals *LIS = DAG->getLIS();
1154 MachineInstr *Copy = CopySU->getInstr();
1156 // Check for pure vreg copies.
1157 unsigned SrcReg = Copy->getOperand(1).getReg();
1158 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
1161 unsigned DstReg = Copy->getOperand(0).getReg();
1162 if (!TargetRegisterInfo::isVirtualRegister(DstReg))
1165 // Check if either the dest or source is local. If it's live across a back
1166 // edge, it's not local. Note that if both vregs are live across the back
1167 // edge, we cannot successfully contrain the copy without cyclic scheduling.
1168 unsigned LocalReg = DstReg;
1169 unsigned GlobalReg = SrcReg;
1170 LiveInterval *LocalLI = &LIS->getInterval(LocalReg);
1171 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx)) {
1174 LocalLI = &LIS->getInterval(LocalReg);
1175 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx))
1178 LiveInterval *GlobalLI = &LIS->getInterval(GlobalReg);
1180 // Find the global segment after the start of the local LI.
1181 LiveInterval::iterator GlobalSegment = GlobalLI->find(LocalLI->beginIndex());
1182 // If GlobalLI does not overlap LocalLI->start, then a copy directly feeds a
1183 // local live range. We could create edges from other global uses to the local
1184 // start, but the coalescer should have already eliminated these cases, so
1185 // don't bother dealing with it.
1186 if (GlobalSegment == GlobalLI->end())
1189 // If GlobalSegment is killed at the LocalLI->start, the call to find()
1190 // returned the next global segment. But if GlobalSegment overlaps with
1191 // LocalLI->start, then advance to the next segement. If a hole in GlobalLI
1192 // exists in LocalLI's vicinity, GlobalSegment will be the end of the hole.
1193 if (GlobalSegment->contains(LocalLI->beginIndex()))
1196 if (GlobalSegment == GlobalLI->end())
1199 // Check if GlobalLI contains a hole in the vicinity of LocalLI.
1200 if (GlobalSegment != GlobalLI->begin()) {
1201 // Two address defs have no hole.
1202 if (SlotIndex::isSameInstr(llvm::prior(GlobalSegment)->end,
1203 GlobalSegment->start)) {
1206 // If the prior global segment may be defined by the same two-address
1207 // instruction that also defines LocalLI, then can't make a hole here.
1208 if (SlotIndex::isSameInstr(llvm::prior(GlobalSegment)->start,
1209 LocalLI->beginIndex())) {
1212 // If GlobalLI has a prior segment, it must be live into the EBB. Otherwise
1213 // it would be a disconnected component in the live range.
1214 assert(llvm::prior(GlobalSegment)->start < LocalLI->beginIndex() &&
1215 "Disconnected LRG within the scheduling region.");
1217 MachineInstr *GlobalDef = LIS->getInstructionFromIndex(GlobalSegment->start);
1221 SUnit *GlobalSU = DAG->getSUnit(GlobalDef);
1225 // GlobalDef is the bottom of the GlobalLI hole. Open the hole by
1226 // constraining the uses of the last local def to precede GlobalDef.
1227 SmallVector<SUnit*,8> LocalUses;
1228 const VNInfo *LastLocalVN = LocalLI->getVNInfoBefore(LocalLI->endIndex());
1229 MachineInstr *LastLocalDef = LIS->getInstructionFromIndex(LastLocalVN->def);
1230 SUnit *LastLocalSU = DAG->getSUnit(LastLocalDef);
1231 for (SUnit::const_succ_iterator
1232 I = LastLocalSU->Succs.begin(), E = LastLocalSU->Succs.end();
1234 if (I->getKind() != SDep::Data || I->getReg() != LocalReg)
1236 if (I->getSUnit() == GlobalSU)
1238 if (!DAG->canAddEdge(GlobalSU, I->getSUnit()))
1240 LocalUses.push_back(I->getSUnit());
1242 // Open the top of the GlobalLI hole by constraining any earlier global uses
1243 // to precede the start of LocalLI.
1244 SmallVector<SUnit*,8> GlobalUses;
1245 MachineInstr *FirstLocalDef =
1246 LIS->getInstructionFromIndex(LocalLI->beginIndex());
1247 SUnit *FirstLocalSU = DAG->getSUnit(FirstLocalDef);
1248 for (SUnit::const_pred_iterator
1249 I = GlobalSU->Preds.begin(), E = GlobalSU->Preds.end(); I != E; ++I) {
1250 if (I->getKind() != SDep::Anti || I->getReg() != GlobalReg)
1252 if (I->getSUnit() == FirstLocalSU)
1254 if (!DAG->canAddEdge(FirstLocalSU, I->getSUnit()))
1256 GlobalUses.push_back(I->getSUnit());
1258 DEBUG(dbgs() << "Constraining copy SU(" << CopySU->NodeNum << ")\n");
1259 // Add the weak edges.
1260 for (SmallVectorImpl<SUnit*>::const_iterator
1261 I = LocalUses.begin(), E = LocalUses.end(); I != E; ++I) {
1262 DEBUG(dbgs() << " Local use SU(" << (*I)->NodeNum << ") -> SU("
1263 << GlobalSU->NodeNum << ")\n");
1264 DAG->addEdge(GlobalSU, SDep(*I, SDep::Weak));
1266 for (SmallVectorImpl<SUnit*>::const_iterator
1267 I = GlobalUses.begin(), E = GlobalUses.end(); I != E; ++I) {
1268 DEBUG(dbgs() << " Global use SU(" << (*I)->NodeNum << ") -> SU("
1269 << FirstLocalSU->NodeNum << ")\n");
1270 DAG->addEdge(FirstLocalSU, SDep(*I, SDep::Weak));
1274 /// \brief Callback from DAG postProcessing to create weak edges to encourage
1275 /// copy elimination.
1276 void CopyConstrain::apply(ScheduleDAGMI *DAG) {
1277 MachineBasicBlock::iterator FirstPos = nextIfDebug(DAG->begin(), DAG->end());
1278 if (FirstPos == DAG->end())
1280 RegionBeginIdx = DAG->getLIS()->getInstructionIndex(&*FirstPos);
1281 RegionEndIdx = DAG->getLIS()->getInstructionIndex(
1282 &*priorNonDebug(DAG->end(), DAG->begin()));
1284 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
1285 SUnit *SU = &DAG->SUnits[Idx];
1286 if (!SU->getInstr()->isCopy())
1289 constrainLocalCopy(SU, DAG);
1293 //===----------------------------------------------------------------------===//
1294 // ConvergingScheduler - Implementation of the generic MachineSchedStrategy.
1295 //===----------------------------------------------------------------------===//
1298 /// ConvergingScheduler shrinks the unscheduled zone using heuristics to balance
1300 class ConvergingScheduler : public MachineSchedStrategy {
1302 /// Represent the type of SchedCandidate found within a single queue.
1303 /// pickNodeBidirectional depends on these listed by decreasing priority.
1305 NoCand, PhysRegCopy, RegExcess, RegCritical, Cluster, Weak, RegMax,
1306 ResourceReduce, ResourceDemand, BotHeightReduce, BotPathReduce,
1307 TopDepthReduce, TopPathReduce, NextDefUse, NodeOrder};
1310 static const char *getReasonStr(ConvergingScheduler::CandReason Reason);
1313 /// Policy for scheduling the next instruction in the candidate's zone.
1316 unsigned ReduceResIdx;
1317 unsigned DemandResIdx;
1319 CandPolicy(): ReduceLatency(false), ReduceResIdx(0), DemandResIdx(0) {}
1322 /// Status of an instruction's critical resource consumption.
1323 struct SchedResourceDelta {
1324 // Count critical resources in the scheduled region required by SU.
1325 unsigned CritResources;
1327 // Count critical resources from another region consumed by SU.
1328 unsigned DemandedResources;
1330 SchedResourceDelta(): CritResources(0), DemandedResources(0) {}
1332 bool operator==(const SchedResourceDelta &RHS) const {
1333 return CritResources == RHS.CritResources
1334 && DemandedResources == RHS.DemandedResources;
1336 bool operator!=(const SchedResourceDelta &RHS) const {
1337 return !operator==(RHS);
1341 /// Store the state used by ConvergingScheduler heuristics, required for the
1342 /// lifetime of one invocation of pickNode().
1343 struct SchedCandidate {
1346 // The best SUnit candidate.
1349 // The reason for this candidate.
1352 // Set of reasons that apply to multiple candidates.
1353 uint32_t RepeatReasonSet;
1355 // Register pressure values for the best candidate.
1356 RegPressureDelta RPDelta;
1358 // Critical resource consumption of the best candidate.
1359 SchedResourceDelta ResDelta;
1361 SchedCandidate(const CandPolicy &policy)
1362 : Policy(policy), SU(NULL), Reason(NoCand), RepeatReasonSet(0) {}
1364 bool isValid() const { return SU; }
1366 // Copy the status of another candidate without changing policy.
1367 void setBest(SchedCandidate &Best) {
1368 assert(Best.Reason != NoCand && "uninitialized Sched candidate");
1370 Reason = Best.Reason;
1371 RPDelta = Best.RPDelta;
1372 ResDelta = Best.ResDelta;
1375 bool isRepeat(CandReason R) { return RepeatReasonSet & (1 << R); }
1376 void setRepeat(CandReason R) { RepeatReasonSet |= (1 << R); }
1378 void initResourceDelta(const ScheduleDAGMI *DAG,
1379 const TargetSchedModel *SchedModel);
1382 /// Summarize the unscheduled region.
1383 struct SchedRemainder {
1384 // Critical path through the DAG in expected latency.
1385 unsigned CriticalPath;
1386 unsigned CyclicCritPath;
1388 // Scaled count of micro-ops left to schedule.
1389 unsigned RemIssueCount;
1391 bool IsAcyclicLatencyLimited;
1393 // Unscheduled resources
1394 SmallVector<unsigned, 16> RemainingCounts;
1400 IsAcyclicLatencyLimited = false;
1401 RemainingCounts.clear();
1404 SchedRemainder() { reset(); }
1406 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
1409 /// Each Scheduling boundary is associated with ready queues. It tracks the
1410 /// current cycle in the direction of movement, and maintains the state
1411 /// of "hazards" and other interlocks at the current cycle.
1412 struct SchedBoundary {
1414 const TargetSchedModel *SchedModel;
1415 SchedRemainder *Rem;
1417 ReadyQueue Available;
1421 // For heuristics, keep a list of the nodes that immediately depend on the
1422 // most recently scheduled node.
1423 SmallPtrSet<const SUnit*, 8> NextSUs;
1425 ScheduleHazardRecognizer *HazardRec;
1427 /// Number of cycles it takes to issue the instructions scheduled in this
1428 /// zone. It is defined as: scheduled-micro-ops / issue-width + stalls.
1429 /// See getStalls().
1432 /// Micro-ops issued in the current cycle
1435 /// MinReadyCycle - Cycle of the soonest available instruction.
1436 unsigned MinReadyCycle;
1438 // The expected latency of the critical path in this scheduled zone.
1439 unsigned ExpectedLatency;
1441 // The latency of dependence chains leading into this zone.
1442 // For each node scheduled bottom-up: DLat = max DLat, N.Depth.
1443 // For each cycle scheduled: DLat -= 1.
1444 unsigned DependentLatency;
1446 /// Count the scheduled (issued) micro-ops that can be retired by
1447 /// time=CurrCycle assuming the first scheduled instr is retired at time=0.
1448 unsigned RetiredMOps;
1450 // Count scheduled resources that have been executed. Resources are
1451 // considered executed if they become ready in the time that it takes to
1452 // saturate any resource including the one in question. Counts are scaled
1453 // for direct comparison with other resources. Counts can be compared with
1454 // MOps * getMicroOpFactor and Latency * getLatencyFactor.
1455 SmallVector<unsigned, 16> ExecutedResCounts;
1457 /// Cache the max count for a single resource.
1458 unsigned MaxExecutedResCount;
1460 // Cache the critical resources ID in this scheduled zone.
1461 unsigned ZoneCritResIdx;
1463 // Is the scheduled region resource limited vs. latency limited.
1464 bool IsResourceLimited;
1467 // Remember the greatest operand latency as an upper bound on the number of
1468 // times we should retry the pending queue because of a hazard.
1469 unsigned MaxObservedLatency;
1473 // A new HazardRec is created for each DAG and owned by SchedBoundary.
1474 // Destroying and reconstructing it is very expensive though. So keep
1475 // invalid, placeholder HazardRecs.
1476 if (HazardRec && HazardRec->isEnabled()) {
1482 CheckPending = false;
1486 MinReadyCycle = UINT_MAX;
1487 ExpectedLatency = 0;
1488 DependentLatency = 0;
1490 MaxExecutedResCount = 0;
1492 IsResourceLimited = false;
1494 MaxObservedLatency = 0;
1496 // Reserve a zero-count for invalid CritResIdx.
1497 ExecutedResCounts.resize(1);
1498 assert(!ExecutedResCounts[0] && "nonzero count for bad resource");
1501 /// Pending queues extend the ready queues with the same ID and the
1502 /// PendingFlag set.
1503 SchedBoundary(unsigned ID, const Twine &Name):
1504 DAG(0), SchedModel(0), Rem(0), Available(ID, Name+".A"),
1505 Pending(ID << ConvergingScheduler::LogMaxQID, Name+".P"),
1510 ~SchedBoundary() { delete HazardRec; }
1512 void init(ScheduleDAGMI *dag, const TargetSchedModel *smodel,
1513 SchedRemainder *rem);
1515 bool isTop() const {
1516 return Available.getID() == ConvergingScheduler::TopQID;
1520 const char *getResourceName(unsigned PIdx) {
1523 return SchedModel->getProcResource(PIdx)->Name;
1527 /// Get the number of latency cycles "covered" by the scheduled
1528 /// instructions. This is the larger of the critical path within the zone
1529 /// and the number of cycles required to issue the instructions.
1530 unsigned getScheduledLatency() const {
1531 return std::max(ExpectedLatency, CurrCycle);
1534 unsigned getUnscheduledLatency(SUnit *SU) const {
1535 return isTop() ? SU->getHeight() : SU->getDepth();
1538 unsigned getResourceCount(unsigned ResIdx) const {
1539 return ExecutedResCounts[ResIdx];
1542 /// Get the scaled count of scheduled micro-ops and resources, including
1543 /// executed resources.
1544 unsigned getCriticalCount() const {
1545 if (!ZoneCritResIdx)
1546 return RetiredMOps * SchedModel->getMicroOpFactor();
1547 return getResourceCount(ZoneCritResIdx);
1550 /// Get a scaled count for the minimum execution time of the scheduled
1551 /// micro-ops that are ready to execute by getExecutedCount. Notice the
1553 unsigned getExecutedCount() const {
1554 return std::max(CurrCycle * SchedModel->getLatencyFactor(),
1555 MaxExecutedResCount);
1558 bool checkHazard(SUnit *SU);
1560 unsigned findMaxLatency(ArrayRef<SUnit*> ReadySUs);
1562 unsigned getOtherResourceCount(unsigned &OtherCritIdx);
1564 void setPolicy(CandPolicy &Policy, SchedBoundary &OtherZone);
1566 void releaseNode(SUnit *SU, unsigned ReadyCycle);
1568 void bumpCycle(unsigned NextCycle);
1570 void incExecutedResources(unsigned PIdx, unsigned Count);
1572 unsigned countResource(unsigned PIdx, unsigned Cycles, unsigned ReadyCycle);
1574 void bumpNode(SUnit *SU);
1576 void releasePending();
1578 void removeReady(SUnit *SU);
1580 SUnit *pickOnlyChoice();
1583 void dumpScheduledState();
1588 const MachineSchedContext *Context;
1590 const TargetSchedModel *SchedModel;
1591 const TargetRegisterInfo *TRI;
1593 // State of the top and bottom scheduled instruction boundaries.
1598 MachineSchedPolicy RegionPolicy;
1600 /// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both)
1607 ConvergingScheduler(const MachineSchedContext *C):
1608 Context(C), DAG(0), SchedModel(0), TRI(0),
1609 Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
1611 virtual void initPolicy(MachineBasicBlock::iterator Begin,
1612 MachineBasicBlock::iterator End,
1613 unsigned NumRegionInstrs);
1615 bool shouldTrackPressure() const { return RegionPolicy.ShouldTrackPressure; }
1617 virtual void initialize(ScheduleDAGMI *dag);
1619 virtual SUnit *pickNode(bool &IsTopNode);
1621 virtual void schedNode(SUnit *SU, bool IsTopNode);
1623 virtual void releaseTopNode(SUnit *SU);
1625 virtual void releaseBottomNode(SUnit *SU);
1627 virtual void registerRoots();
1630 void checkAcyclicLatency();
1632 void tryCandidate(SchedCandidate &Cand,
1633 SchedCandidate &TryCand,
1634 SchedBoundary &Zone,
1635 const RegPressureTracker &RPTracker,
1636 RegPressureTracker &TempTracker);
1638 SUnit *pickNodeBidirectional(bool &IsTopNode);
1640 void pickNodeFromQueue(SchedBoundary &Zone,
1641 const RegPressureTracker &RPTracker,
1642 SchedCandidate &Candidate);
1644 void reschedulePhysRegCopies(SUnit *SU, bool isTop);
1647 void traceCandidate(const SchedCandidate &Cand);
1652 void ConvergingScheduler::SchedRemainder::
1653 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) {
1655 if (!SchedModel->hasInstrSchedModel())
1657 RemainingCounts.resize(SchedModel->getNumProcResourceKinds());
1658 for (std::vector<SUnit>::iterator
1659 I = DAG->SUnits.begin(), E = DAG->SUnits.end(); I != E; ++I) {
1660 const MCSchedClassDesc *SC = DAG->getSchedClass(&*I);
1661 RemIssueCount += SchedModel->getNumMicroOps(I->getInstr(), SC)
1662 * SchedModel->getMicroOpFactor();
1663 for (TargetSchedModel::ProcResIter
1664 PI = SchedModel->getWriteProcResBegin(SC),
1665 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1666 unsigned PIdx = PI->ProcResourceIdx;
1667 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1668 RemainingCounts[PIdx] += (Factor * PI->Cycles);
1673 void ConvergingScheduler::SchedBoundary::
1674 init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem) {
1677 SchedModel = smodel;
1679 if (SchedModel->hasInstrSchedModel())
1680 ExecutedResCounts.resize(SchedModel->getNumProcResourceKinds());
1683 /// Initialize the per-region scheduling policy.
1684 void ConvergingScheduler::initPolicy(MachineBasicBlock::iterator Begin,
1685 MachineBasicBlock::iterator End,
1686 unsigned NumRegionInstrs) {
1687 const TargetMachine &TM = Context->MF->getTarget();
1689 // Avoid setting up the register pressure tracker for small regions to save
1690 // compile time. As a rough heuristic, only track pressure when the number of
1691 // schedulable instructions exceeds half the integer register file.
1692 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs(
1693 TM.getTargetLowering()->getRegClassFor(MVT::i32));
1695 RegionPolicy.ShouldTrackPressure = NumRegionInstrs > (NIntRegs / 2);
1697 // For generic targets, we default to bottom-up, because it's simpler and more
1698 // compile-time optimizations have been implemented in that direction.
1699 RegionPolicy.OnlyBottomUp = true;
1701 // Allow the subtarget to override default policy.
1702 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
1703 ST.overrideSchedPolicy(RegionPolicy, Begin, End, NumRegionInstrs);
1705 // After subtarget overrides, apply command line options.
1706 if (!EnableRegPressure)
1707 RegionPolicy.ShouldTrackPressure = false;
1709 // Check -misched-topdown/bottomup can force or unforce scheduling direction.
1710 // e.g. -misched-bottomup=false allows scheduling in both directions.
1711 assert((!ForceTopDown || !ForceBottomUp) &&
1712 "-misched-topdown incompatible with -misched-bottomup");
1713 if (ForceBottomUp.getNumOccurrences() > 0) {
1714 RegionPolicy.OnlyBottomUp = ForceBottomUp;
1715 if (RegionPolicy.OnlyBottomUp)
1716 RegionPolicy.OnlyTopDown = false;
1718 if (ForceTopDown.getNumOccurrences() > 0) {
1719 RegionPolicy.OnlyTopDown = ForceTopDown;
1720 if (RegionPolicy.OnlyTopDown)
1721 RegionPolicy.OnlyBottomUp = false;
1725 void ConvergingScheduler::initialize(ScheduleDAGMI *dag) {
1727 SchedModel = DAG->getSchedModel();
1730 Rem.init(DAG, SchedModel);
1731 Top.init(DAG, SchedModel, &Rem);
1732 Bot.init(DAG, SchedModel, &Rem);
1734 // Initialize resource counts.
1736 // Initialize the HazardRecognizers. If itineraries don't exist, are empty, or
1737 // are disabled, then these HazardRecs will be disabled.
1738 const InstrItineraryData *Itin = SchedModel->getInstrItineraries();
1739 const TargetMachine &TM = DAG->MF.getTarget();
1740 if (!Top.HazardRec) {
1742 TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
1744 if (!Bot.HazardRec) {
1746 TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
1750 void ConvergingScheduler::releaseTopNode(SUnit *SU) {
1751 if (SU->isScheduled)
1754 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1758 unsigned PredReadyCycle = I->getSUnit()->TopReadyCycle;
1759 unsigned Latency = I->getLatency();
1761 Top.MaxObservedLatency = std::max(Latency, Top.MaxObservedLatency);
1763 if (SU->TopReadyCycle < PredReadyCycle + Latency)
1764 SU->TopReadyCycle = PredReadyCycle + Latency;
1766 Top.releaseNode(SU, SU->TopReadyCycle);
1769 void ConvergingScheduler::releaseBottomNode(SUnit *SU) {
1770 if (SU->isScheduled)
1773 assert(SU->getInstr() && "Scheduled SUnit must have instr");
1775 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1779 unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle;
1780 unsigned Latency = I->getLatency();
1782 Bot.MaxObservedLatency = std::max(Latency, Bot.MaxObservedLatency);
1784 if (SU->BotReadyCycle < SuccReadyCycle + Latency)
1785 SU->BotReadyCycle = SuccReadyCycle + Latency;
1787 Bot.releaseNode(SU, SU->BotReadyCycle);
1790 /// Set IsAcyclicLatencyLimited if the acyclic path is longer than the cyclic
1791 /// critical path by more cycles than it takes to drain the instruction buffer.
1792 /// We estimate an upper bounds on in-flight instructions as:
1794 /// CyclesPerIteration = max( CyclicPath, Loop-Resource-Height )
1795 /// InFlightIterations = AcyclicPath / CyclesPerIteration
1796 /// InFlightResources = InFlightIterations * LoopResources
1798 /// TODO: Check execution resources in addition to IssueCount.
1799 void ConvergingScheduler::checkAcyclicLatency() {
1800 if (Rem.CyclicCritPath == 0 || Rem.CyclicCritPath >= Rem.CriticalPath)
1803 // Scaled number of cycles per loop iteration.
1804 unsigned IterCount =
1805 std::max(Rem.CyclicCritPath * SchedModel->getLatencyFactor(),
1807 // Scaled acyclic critical path.
1808 unsigned AcyclicCount = Rem.CriticalPath * SchedModel->getLatencyFactor();
1809 // InFlightCount = (AcyclicPath / IterCycles) * InstrPerLoop
1810 unsigned InFlightCount =
1811 (AcyclicCount * Rem.RemIssueCount + IterCount-1) / IterCount;
1812 unsigned BufferLimit =
1813 SchedModel->getMicroOpBufferSize() * SchedModel->getMicroOpFactor();
1815 Rem.IsAcyclicLatencyLimited = InFlightCount > BufferLimit;
1817 DEBUG(dbgs() << "IssueCycles="
1818 << Rem.RemIssueCount / SchedModel->getLatencyFactor() << "c "
1819 << "IterCycles=" << IterCount / SchedModel->getLatencyFactor()
1820 << "c NumIters=" << (AcyclicCount + IterCount-1) / IterCount
1821 << " InFlight=" << InFlightCount / SchedModel->getMicroOpFactor()
1822 << "m BufferLim=" << SchedModel->getMicroOpBufferSize() << "m\n";
1823 if (Rem.IsAcyclicLatencyLimited)
1824 dbgs() << " ACYCLIC LATENCY LIMIT\n");
1827 void ConvergingScheduler::registerRoots() {
1828 Rem.CriticalPath = DAG->ExitSU.getDepth();
1830 // Some roots may not feed into ExitSU. Check all of them in case.
1831 for (std::vector<SUnit*>::const_iterator
1832 I = Bot.Available.begin(), E = Bot.Available.end(); I != E; ++I) {
1833 if ((*I)->getDepth() > Rem.CriticalPath)
1834 Rem.CriticalPath = (*I)->getDepth();
1836 DEBUG(dbgs() << "Critical Path: " << Rem.CriticalPath << '\n');
1838 if (EnableCyclicPath) {
1839 Rem.CyclicCritPath = DAG->computeCyclicCriticalPath();
1840 checkAcyclicLatency();
1844 /// Does this SU have a hazard within the current instruction group.
1846 /// The scheduler supports two modes of hazard recognition. The first is the
1847 /// ScheduleHazardRecognizer API. It is a fully general hazard recognizer that
1848 /// supports highly complicated in-order reservation tables
1849 /// (ScoreboardHazardRecognizer) and arbitraty target-specific logic.
1851 /// The second is a streamlined mechanism that checks for hazards based on
1852 /// simple counters that the scheduler itself maintains. It explicitly checks
1853 /// for instruction dispatch limitations, including the number of micro-ops that
1854 /// can dispatch per cycle.
1856 /// TODO: Also check whether the SU must start a new group.
1857 bool ConvergingScheduler::SchedBoundary::checkHazard(SUnit *SU) {
1858 if (HazardRec->isEnabled())
1859 return HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard;
1861 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
1862 if ((CurrMOps > 0) && (CurrMOps + uops > SchedModel->getIssueWidth())) {
1863 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") uops="
1864 << SchedModel->getNumMicroOps(SU->getInstr()) << '\n');
1870 // Find the unscheduled node in ReadySUs with the highest latency.
1871 unsigned ConvergingScheduler::SchedBoundary::
1872 findMaxLatency(ArrayRef<SUnit*> ReadySUs) {
1874 unsigned RemLatency = 0;
1875 for (ArrayRef<SUnit*>::iterator I = ReadySUs.begin(), E = ReadySUs.end();
1877 unsigned L = getUnscheduledLatency(*I);
1878 if (L > RemLatency) {
1884 DEBUG(dbgs() << Available.getName() << " RemLatency SU("
1885 << LateSU->NodeNum << ") " << RemLatency << "c\n");
1890 // Count resources in this zone and the remaining unscheduled
1891 // instruction. Return the max count, scaled. Set OtherCritIdx to the critical
1892 // resource index, or zero if the zone is issue limited.
1893 unsigned ConvergingScheduler::SchedBoundary::
1894 getOtherResourceCount(unsigned &OtherCritIdx) {
1896 if (!SchedModel->hasInstrSchedModel())
1899 unsigned OtherCritCount = Rem->RemIssueCount
1900 + (RetiredMOps * SchedModel->getMicroOpFactor());
1901 DEBUG(dbgs() << " " << Available.getName() << " + Remain MOps: "
1902 << OtherCritCount / SchedModel->getMicroOpFactor() << '\n');
1903 for (unsigned PIdx = 1, PEnd = SchedModel->getNumProcResourceKinds();
1904 PIdx != PEnd; ++PIdx) {
1905 unsigned OtherCount = getResourceCount(PIdx) + Rem->RemainingCounts[PIdx];
1906 if (OtherCount > OtherCritCount) {
1907 OtherCritCount = OtherCount;
1908 OtherCritIdx = PIdx;
1912 DEBUG(dbgs() << " " << Available.getName() << " + Remain CritRes: "
1913 << OtherCritCount / SchedModel->getResourceFactor(OtherCritIdx)
1914 << " " << getResourceName(OtherCritIdx) << "\n");
1916 return OtherCritCount;
1919 /// Set the CandPolicy for this zone given the current resources and latencies
1920 /// inside and outside the zone.
1921 void ConvergingScheduler::SchedBoundary::setPolicy(CandPolicy &Policy,
1922 SchedBoundary &OtherZone) {
1923 // Now that potential stalls have been considered, apply preemptive heuristics
1924 // based on the the total latency and resources inside and outside this
1927 // Compute remaining latency. We need this both to determine whether the
1928 // overall schedule has become latency-limited and whether the instructions
1929 // outside this zone are resource or latency limited.
1931 // The "dependent" latency is updated incrementally during scheduling as the
1932 // max height/depth of scheduled nodes minus the cycles since it was
1934 // DLat = max (N.depth - (CurrCycle - N.ReadyCycle) for N in Zone
1936 // The "independent" latency is the max ready queue depth:
1937 // ILat = max N.depth for N in Available|Pending
1939 // RemainingLatency is the greater of independent and dependent latency.
1940 unsigned RemLatency = DependentLatency;
1941 RemLatency = std::max(RemLatency, findMaxLatency(Available.elements()));
1942 RemLatency = std::max(RemLatency, findMaxLatency(Pending.elements()));
1944 // Compute the critical resource outside the zone.
1945 unsigned OtherCritIdx;
1946 unsigned OtherCount = OtherZone.getOtherResourceCount(OtherCritIdx);
1948 bool OtherResLimited = false;
1949 if (SchedModel->hasInstrSchedModel()) {
1950 unsigned LFactor = SchedModel->getLatencyFactor();
1951 OtherResLimited = (int)(OtherCount - (RemLatency * LFactor)) > (int)LFactor;
1953 if (!OtherResLimited && (RemLatency + CurrCycle > Rem->CriticalPath)) {
1954 Policy.ReduceLatency |= true;
1955 DEBUG(dbgs() << " " << Available.getName() << " RemainingLatency "
1956 << RemLatency << " + " << CurrCycle << "c > CritPath "
1957 << Rem->CriticalPath << "\n");
1959 // If the same resource is limiting inside and outside the zone, do nothing.
1960 if (ZoneCritResIdx == OtherCritIdx)
1964 if (IsResourceLimited) {
1965 dbgs() << " " << Available.getName() << " ResourceLimited: "
1966 << getResourceName(ZoneCritResIdx) << "\n";
1968 if (OtherResLimited)
1969 dbgs() << " RemainingLimit: " << getResourceName(OtherCritIdx) << "\n";
1970 if (!IsResourceLimited && !OtherResLimited)
1971 dbgs() << " Latency limited both directions.\n");
1973 if (IsResourceLimited && !Policy.ReduceResIdx)
1974 Policy.ReduceResIdx = ZoneCritResIdx;
1976 if (OtherResLimited)
1977 Policy.DemandResIdx = OtherCritIdx;
1980 void ConvergingScheduler::SchedBoundary::releaseNode(SUnit *SU,
1981 unsigned ReadyCycle) {
1982 if (ReadyCycle < MinReadyCycle)
1983 MinReadyCycle = ReadyCycle;
1985 // Check for interlocks first. For the purpose of other heuristics, an
1986 // instruction that cannot issue appears as if it's not in the ReadyQueue.
1987 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
1988 if ((!IsBuffered && ReadyCycle > CurrCycle) || checkHazard(SU))
1993 // Record this node as an immediate dependent of the scheduled node.
1997 /// Move the boundary of scheduled code by one cycle.
1998 void ConvergingScheduler::SchedBoundary::bumpCycle(unsigned NextCycle) {
1999 if (SchedModel->getMicroOpBufferSize() == 0) {
2000 assert(MinReadyCycle < UINT_MAX && "MinReadyCycle uninitialized");
2001 if (MinReadyCycle > NextCycle)
2002 NextCycle = MinReadyCycle;
2004 // Update the current micro-ops, which will issue in the next cycle.
2005 unsigned DecMOps = SchedModel->getIssueWidth() * (NextCycle - CurrCycle);
2006 CurrMOps = (CurrMOps <= DecMOps) ? 0 : CurrMOps - DecMOps;
2008 // Decrement DependentLatency based on the next cycle.
2009 if ((NextCycle - CurrCycle) > DependentLatency)
2010 DependentLatency = 0;
2012 DependentLatency -= (NextCycle - CurrCycle);
2014 if (!HazardRec->isEnabled()) {
2015 // Bypass HazardRec virtual calls.
2016 CurrCycle = NextCycle;
2019 // Bypass getHazardType calls in case of long latency.
2020 for (; CurrCycle != NextCycle; ++CurrCycle) {
2022 HazardRec->AdvanceCycle();
2024 HazardRec->RecedeCycle();
2027 CheckPending = true;
2028 unsigned LFactor = SchedModel->getLatencyFactor();
2030 (int)(getCriticalCount() - (getScheduledLatency() * LFactor))
2033 DEBUG(dbgs() << "Cycle: " << CurrCycle << ' ' << Available.getName() << '\n');
2036 void ConvergingScheduler::SchedBoundary::incExecutedResources(unsigned PIdx,
2038 ExecutedResCounts[PIdx] += Count;
2039 if (ExecutedResCounts[PIdx] > MaxExecutedResCount)
2040 MaxExecutedResCount = ExecutedResCounts[PIdx];
2043 /// Add the given processor resource to this scheduled zone.
2045 /// \param Cycles indicates the number of consecutive (non-pipelined) cycles
2046 /// during which this resource is consumed.
2048 /// \return the next cycle at which the instruction may execute without
2049 /// oversubscribing resources.
2050 unsigned ConvergingScheduler::SchedBoundary::
2051 countResource(unsigned PIdx, unsigned Cycles, unsigned ReadyCycle) {
2052 unsigned Factor = SchedModel->getResourceFactor(PIdx);
2053 unsigned Count = Factor * Cycles;
2054 DEBUG(dbgs() << " " << getResourceName(PIdx)
2055 << " +" << Cycles << "x" << Factor << "u\n");
2057 // Update Executed resources counts.
2058 incExecutedResources(PIdx, Count);
2059 assert(Rem->RemainingCounts[PIdx] >= Count && "resource double counted");
2060 Rem->RemainingCounts[PIdx] -= Count;
2062 // Check if this resource exceeds the current critical resource. If so, it
2063 // becomes the critical resource.
2064 if (ZoneCritResIdx != PIdx && (getResourceCount(PIdx) > getCriticalCount())) {
2065 ZoneCritResIdx = PIdx;
2066 DEBUG(dbgs() << " *** Critical resource "
2067 << getResourceName(PIdx) << ": "
2068 << getResourceCount(PIdx) / SchedModel->getLatencyFactor() << "c\n");
2070 // TODO: We don't yet model reserved resources. It's not hard though.
2074 /// Move the boundary of scheduled code by one SUnit.
2075 void ConvergingScheduler::SchedBoundary::bumpNode(SUnit *SU) {
2076 // Update the reservation table.
2077 if (HazardRec->isEnabled()) {
2078 if (!isTop() && SU->isCall) {
2079 // Calls are scheduled with their preceding instructions. For bottom-up
2080 // scheduling, clear the pipeline state before emitting.
2083 HazardRec->EmitInstruction(SU);
2085 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
2086 unsigned IncMOps = SchedModel->getNumMicroOps(SU->getInstr());
2087 CurrMOps += IncMOps;
2088 // checkHazard prevents scheduling multiple instructions per cycle that exceed
2089 // issue width. However, we commonly reach the maximum. In this case
2090 // opportunistically bump the cycle to avoid uselessly checking everything in
2091 // the readyQ. Furthermore, a single instruction may produce more than one
2092 // cycle's worth of micro-ops.
2094 // TODO: Also check if this SU must end a dispatch group.
2095 unsigned NextCycle = CurrCycle;
2096 if (CurrMOps >= SchedModel->getIssueWidth()) {
2098 DEBUG(dbgs() << " *** Max MOps " << CurrMOps
2099 << " at cycle " << CurrCycle << '\n');
2101 unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle);
2102 DEBUG(dbgs() << " Ready @" << ReadyCycle << "c\n");
2104 switch (SchedModel->getMicroOpBufferSize()) {
2106 assert(ReadyCycle <= CurrCycle && "Broken PendingQueue");
2109 if (ReadyCycle > NextCycle) {
2110 NextCycle = ReadyCycle;
2111 DEBUG(dbgs() << " *** Stall until: " << ReadyCycle << "\n");
2115 // We don't currently model the OOO reorder buffer, so consider all
2116 // scheduled MOps to be "retired".
2119 RetiredMOps += IncMOps;
2121 // Update resource counts and critical resource.
2122 if (SchedModel->hasInstrSchedModel()) {
2123 unsigned DecRemIssue = IncMOps * SchedModel->getMicroOpFactor();
2124 assert(Rem->RemIssueCount >= DecRemIssue && "MOps double counted");
2125 Rem->RemIssueCount -= DecRemIssue;
2126 if (ZoneCritResIdx) {
2127 // Scale scheduled micro-ops for comparing with the critical resource.
2128 unsigned ScaledMOps =
2129 RetiredMOps * SchedModel->getMicroOpFactor();
2131 // If scaled micro-ops are now more than the previous critical resource by
2132 // a full cycle, then micro-ops issue becomes critical.
2133 if ((int)(ScaledMOps - getResourceCount(ZoneCritResIdx))
2134 >= (int)SchedModel->getLatencyFactor()) {
2136 DEBUG(dbgs() << " *** Critical resource NumMicroOps: "
2137 << ScaledMOps / SchedModel->getLatencyFactor() << "c\n");
2140 for (TargetSchedModel::ProcResIter
2141 PI = SchedModel->getWriteProcResBegin(SC),
2142 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
2144 countResource(PI->ProcResourceIdx, PI->Cycles, ReadyCycle);
2145 if (RCycle > NextCycle)
2149 // Update ExpectedLatency and DependentLatency.
2150 unsigned &TopLatency = isTop() ? ExpectedLatency : DependentLatency;
2151 unsigned &BotLatency = isTop() ? DependentLatency : ExpectedLatency;
2152 if (SU->getDepth() > TopLatency) {
2153 TopLatency = SU->getDepth();
2154 DEBUG(dbgs() << " " << Available.getName()
2155 << " TopLatency SU(" << SU->NodeNum << ") " << TopLatency << "c\n");
2157 if (SU->getHeight() > BotLatency) {
2158 BotLatency = SU->getHeight();
2159 DEBUG(dbgs() << " " << Available.getName()
2160 << " BotLatency SU(" << SU->NodeNum << ") " << BotLatency << "c\n");
2162 // If we stall for any reason, bump the cycle.
2163 if (NextCycle > CurrCycle) {
2164 bumpCycle(NextCycle);
2167 // After updating ZoneCritResIdx and ExpectedLatency, check if we're
2168 // resource limited. If a stall occured, bumpCycle does this.
2169 unsigned LFactor = SchedModel->getLatencyFactor();
2171 (int)(getCriticalCount() - (getScheduledLatency() * LFactor))
2174 DEBUG(dumpScheduledState());
2177 /// Release pending ready nodes in to the available queue. This makes them
2178 /// visible to heuristics.
2179 void ConvergingScheduler::SchedBoundary::releasePending() {
2180 // If the available queue is empty, it is safe to reset MinReadyCycle.
2181 if (Available.empty())
2182 MinReadyCycle = UINT_MAX;
2184 // Check to see if any of the pending instructions are ready to issue. If
2185 // so, add them to the available queue.
2186 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
2187 for (unsigned i = 0, e = Pending.size(); i != e; ++i) {
2188 SUnit *SU = *(Pending.begin()+i);
2189 unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle;
2191 if (ReadyCycle < MinReadyCycle)
2192 MinReadyCycle = ReadyCycle;
2194 if (!IsBuffered && ReadyCycle > CurrCycle)
2197 if (checkHazard(SU))
2201 Pending.remove(Pending.begin()+i);
2204 DEBUG(if (!Pending.empty()) Pending.dump());
2205 CheckPending = false;
2208 /// Remove SU from the ready set for this boundary.
2209 void ConvergingScheduler::SchedBoundary::removeReady(SUnit *SU) {
2210 if (Available.isInQueue(SU))
2211 Available.remove(Available.find(SU));
2213 assert(Pending.isInQueue(SU) && "bad ready count");
2214 Pending.remove(Pending.find(SU));
2218 /// If this queue only has one ready candidate, return it. As a side effect,
2219 /// defer any nodes that now hit a hazard, and advance the cycle until at least
2220 /// one node is ready. If multiple instructions are ready, return NULL.
2221 SUnit *ConvergingScheduler::SchedBoundary::pickOnlyChoice() {
2226 // Defer any ready instrs that now have a hazard.
2227 for (ReadyQueue::iterator I = Available.begin(); I != Available.end();) {
2228 if (checkHazard(*I)) {
2230 I = Available.remove(I);
2236 for (unsigned i = 0; Available.empty(); ++i) {
2237 assert(i <= (HazardRec->getMaxLookAhead() + MaxObservedLatency) &&
2238 "permanent hazard"); (void)i;
2239 bumpCycle(CurrCycle + 1);
2242 if (Available.size() == 1)
2243 return *Available.begin();
2248 // This is useful information to dump after bumpNode.
2249 // Note that the Queue contents are more useful before pickNodeFromQueue.
2250 void ConvergingScheduler::SchedBoundary::dumpScheduledState() {
2253 if (ZoneCritResIdx) {
2254 ResFactor = SchedModel->getResourceFactor(ZoneCritResIdx);
2255 ResCount = getResourceCount(ZoneCritResIdx);
2258 ResFactor = SchedModel->getMicroOpFactor();
2259 ResCount = RetiredMOps * SchedModel->getMicroOpFactor();
2261 unsigned LFactor = SchedModel->getLatencyFactor();
2262 dbgs() << Available.getName() << " @" << CurrCycle << "c\n"
2263 << " Retired: " << RetiredMOps;
2264 dbgs() << "\n Executed: " << getExecutedCount() / LFactor << "c";
2265 dbgs() << "\n Critical: " << ResCount / LFactor << "c, "
2266 << ResCount / ResFactor << " " << getResourceName(ZoneCritResIdx)
2267 << "\n ExpectedLatency: " << ExpectedLatency << "c\n"
2268 << (IsResourceLimited ? " - Resource" : " - Latency")
2273 void ConvergingScheduler::SchedCandidate::
2274 initResourceDelta(const ScheduleDAGMI *DAG,
2275 const TargetSchedModel *SchedModel) {
2276 if (!Policy.ReduceResIdx && !Policy.DemandResIdx)
2279 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
2280 for (TargetSchedModel::ProcResIter
2281 PI = SchedModel->getWriteProcResBegin(SC),
2282 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
2283 if (PI->ProcResourceIdx == Policy.ReduceResIdx)
2284 ResDelta.CritResources += PI->Cycles;
2285 if (PI->ProcResourceIdx == Policy.DemandResIdx)
2286 ResDelta.DemandedResources += PI->Cycles;
2291 /// Return true if this heuristic determines order.
2292 static bool tryLess(int TryVal, int CandVal,
2293 ConvergingScheduler::SchedCandidate &TryCand,
2294 ConvergingScheduler::SchedCandidate &Cand,
2295 ConvergingScheduler::CandReason Reason) {
2296 if (TryVal < CandVal) {
2297 TryCand.Reason = Reason;
2300 if (TryVal > CandVal) {
2301 if (Cand.Reason > Reason)
2302 Cand.Reason = Reason;
2305 Cand.setRepeat(Reason);
2309 static bool tryGreater(int TryVal, int CandVal,
2310 ConvergingScheduler::SchedCandidate &TryCand,
2311 ConvergingScheduler::SchedCandidate &Cand,
2312 ConvergingScheduler::CandReason Reason) {
2313 if (TryVal > CandVal) {
2314 TryCand.Reason = Reason;
2317 if (TryVal < CandVal) {
2318 if (Cand.Reason > Reason)
2319 Cand.Reason = Reason;
2322 Cand.setRepeat(Reason);
2326 static bool tryPressure(const PressureChange &TryP,
2327 const PressureChange &CandP,
2328 ConvergingScheduler::SchedCandidate &TryCand,
2329 ConvergingScheduler::SchedCandidate &Cand,
2330 ConvergingScheduler::CandReason Reason) {
2331 int TryRank = TryP.getPSetOrMax();
2332 int CandRank = CandP.getPSetOrMax();
2333 // If both candidates affect the same set, go with the smallest increase.
2334 if (TryRank == CandRank) {
2335 return tryLess(TryP.getUnitInc(), CandP.getUnitInc(), TryCand, Cand,
2338 // If one candidate decreases and the other increases, go with it.
2339 // Invalid candidates have UnitInc==0.
2340 if (tryLess(TryP.getUnitInc() < 0, CandP.getUnitInc() < 0, TryCand, Cand,
2344 // If the candidates are decreasing pressure, reverse priority.
2345 if (TryP.getUnitInc() < 0)
2346 std::swap(TryRank, CandRank);
2347 return tryGreater(TryRank, CandRank, TryCand, Cand, Reason);
2350 static unsigned getWeakLeft(const SUnit *SU, bool isTop) {
2351 return (isTop) ? SU->WeakPredsLeft : SU->WeakSuccsLeft;
2354 /// Minimize physical register live ranges. Regalloc wants them adjacent to
2355 /// their physreg def/use.
2357 /// FIXME: This is an unnecessary check on the critical path. Most are root/leaf
2358 /// copies which can be prescheduled. The rest (e.g. x86 MUL) could be bundled
2359 /// with the operation that produces or consumes the physreg. We'll do this when
2360 /// regalloc has support for parallel copies.
2361 static int biasPhysRegCopy(const SUnit *SU, bool isTop) {
2362 const MachineInstr *MI = SU->getInstr();
2366 unsigned ScheduledOper = isTop ? 1 : 0;
2367 unsigned UnscheduledOper = isTop ? 0 : 1;
2368 // If we have already scheduled the physreg produce/consumer, immediately
2369 // schedule the copy.
2370 if (TargetRegisterInfo::isPhysicalRegister(
2371 MI->getOperand(ScheduledOper).getReg()))
2373 // If the physreg is at the boundary, defer it. Otherwise schedule it
2374 // immediately to free the dependent. We can hoist the copy later.
2375 bool AtBoundary = isTop ? !SU->NumSuccsLeft : !SU->NumPredsLeft;
2376 if (TargetRegisterInfo::isPhysicalRegister(
2377 MI->getOperand(UnscheduledOper).getReg()))
2378 return AtBoundary ? -1 : 1;
2382 static bool tryLatency(ConvergingScheduler::SchedCandidate &TryCand,
2383 ConvergingScheduler::SchedCandidate &Cand,
2384 ConvergingScheduler::SchedBoundary &Zone) {
2386 if (Cand.SU->getDepth() > Zone.getScheduledLatency()) {
2387 if (tryLess(TryCand.SU->getDepth(), Cand.SU->getDepth(),
2388 TryCand, Cand, ConvergingScheduler::TopDepthReduce))
2391 if (tryGreater(TryCand.SU->getHeight(), Cand.SU->getHeight(),
2392 TryCand, Cand, ConvergingScheduler::TopPathReduce))
2396 if (Cand.SU->getHeight() > Zone.getScheduledLatency()) {
2397 if (tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(),
2398 TryCand, Cand, ConvergingScheduler::BotHeightReduce))
2401 if (tryGreater(TryCand.SU->getDepth(), Cand.SU->getDepth(),
2402 TryCand, Cand, ConvergingScheduler::BotPathReduce))
2408 /// Apply a set of heursitics to a new candidate. Heuristics are currently
2409 /// hierarchical. This may be more efficient than a graduated cost model because
2410 /// we don't need to evaluate all aspects of the model for each node in the
2411 /// queue. But it's really done to make the heuristics easier to debug and
2412 /// statistically analyze.
2414 /// \param Cand provides the policy and current best candidate.
2415 /// \param TryCand refers to the next SUnit candidate, otherwise uninitialized.
2416 /// \param Zone describes the scheduled zone that we are extending.
2417 /// \param RPTracker describes reg pressure within the scheduled zone.
2418 /// \param TempTracker is a scratch pressure tracker to reuse in queries.
2419 void ConvergingScheduler::tryCandidate(SchedCandidate &Cand,
2420 SchedCandidate &TryCand,
2421 SchedBoundary &Zone,
2422 const RegPressureTracker &RPTracker,
2423 RegPressureTracker &TempTracker) {
2425 if (DAG->isTrackingPressure()) {
2426 // Always initialize TryCand's RPDelta.
2428 TempTracker.getMaxDownwardPressureDelta(
2429 TryCand.SU->getInstr(),
2431 DAG->getRegionCriticalPSets(),
2432 DAG->getRegPressure().MaxSetPressure);
2435 if (VerifyScheduling) {
2436 TempTracker.getMaxUpwardPressureDelta(
2437 TryCand.SU->getInstr(),
2438 &DAG->getPressureDiff(TryCand.SU),
2440 DAG->getRegionCriticalPSets(),
2441 DAG->getRegPressure().MaxSetPressure);
2444 RPTracker.getUpwardPressureDelta(
2445 TryCand.SU->getInstr(),
2446 DAG->getPressureDiff(TryCand.SU),
2448 DAG->getRegionCriticalPSets(),
2449 DAG->getRegPressure().MaxSetPressure);
2454 // Initialize the candidate if needed.
2455 if (!Cand.isValid()) {
2456 TryCand.Reason = NodeOrder;
2460 if (tryGreater(biasPhysRegCopy(TryCand.SU, Zone.isTop()),
2461 biasPhysRegCopy(Cand.SU, Zone.isTop()),
2462 TryCand, Cand, PhysRegCopy))
2465 // Avoid exceeding the target's limit. If signed PSetID is negative, it is
2466 // invalid; convert it to INT_MAX to give it lowest priority.
2467 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.Excess,
2468 Cand.RPDelta.Excess,
2469 TryCand, Cand, RegExcess))
2472 // Avoid increasing the max critical pressure in the scheduled region.
2473 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.CriticalMax,
2474 Cand.RPDelta.CriticalMax,
2475 TryCand, Cand, RegCritical))
2478 // For loops that are acyclic path limited, aggressively schedule for latency.
2479 if (Rem.IsAcyclicLatencyLimited && tryLatency(TryCand, Cand, Zone))
2482 // Keep clustered nodes together to encourage downstream peephole
2483 // optimizations which may reduce resource requirements.
2485 // This is a best effort to set things up for a post-RA pass. Optimizations
2486 // like generating loads of multiple registers should ideally be done within
2487 // the scheduler pass by combining the loads during DAG postprocessing.
2488 const SUnit *NextClusterSU =
2489 Zone.isTop() ? DAG->getNextClusterSucc() : DAG->getNextClusterPred();
2490 if (tryGreater(TryCand.SU == NextClusterSU, Cand.SU == NextClusterSU,
2491 TryCand, Cand, Cluster))
2494 // Weak edges are for clustering and other constraints.
2495 if (tryLess(getWeakLeft(TryCand.SU, Zone.isTop()),
2496 getWeakLeft(Cand.SU, Zone.isTop()),
2497 TryCand, Cand, Weak)) {
2500 // Avoid increasing the max pressure of the entire region.
2501 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.CurrentMax,
2502 Cand.RPDelta.CurrentMax,
2503 TryCand, Cand, RegMax))
2506 // Avoid critical resource consumption and balance the schedule.
2507 TryCand.initResourceDelta(DAG, SchedModel);
2508 if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
2509 TryCand, Cand, ResourceReduce))
2511 if (tryGreater(TryCand.ResDelta.DemandedResources,
2512 Cand.ResDelta.DemandedResources,
2513 TryCand, Cand, ResourceDemand))
2516 // Avoid serializing long latency dependence chains.
2517 // For acyclic path limited loops, latency was already checked above.
2518 if (Cand.Policy.ReduceLatency && !Rem.IsAcyclicLatencyLimited
2519 && tryLatency(TryCand, Cand, Zone)) {
2523 // Prefer immediate defs/users of the last scheduled instruction. This is a
2524 // local pressure avoidance strategy that also makes the machine code
2526 if (tryGreater(Zone.NextSUs.count(TryCand.SU), Zone.NextSUs.count(Cand.SU),
2527 TryCand, Cand, NextDefUse))
2530 // Fall through to original instruction order.
2531 if ((Zone.isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum)
2532 || (!Zone.isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) {
2533 TryCand.Reason = NodeOrder;
2538 const char *ConvergingScheduler::getReasonStr(
2539 ConvergingScheduler::CandReason Reason) {
2541 case NoCand: return "NOCAND ";
2542 case PhysRegCopy: return "PREG-COPY";
2543 case RegExcess: return "REG-EXCESS";
2544 case RegCritical: return "REG-CRIT ";
2545 case Cluster: return "CLUSTER ";
2546 case Weak: return "WEAK ";
2547 case RegMax: return "REG-MAX ";
2548 case ResourceReduce: return "RES-REDUCE";
2549 case ResourceDemand: return "RES-DEMAND";
2550 case TopDepthReduce: return "TOP-DEPTH ";
2551 case TopPathReduce: return "TOP-PATH ";
2552 case BotHeightReduce:return "BOT-HEIGHT";
2553 case BotPathReduce: return "BOT-PATH ";
2554 case NextDefUse: return "DEF-USE ";
2555 case NodeOrder: return "ORDER ";
2557 llvm_unreachable("Unknown reason!");
2560 void ConvergingScheduler::traceCandidate(const SchedCandidate &Cand) {
2562 unsigned ResIdx = 0;
2563 unsigned Latency = 0;
2564 switch (Cand.Reason) {
2568 P = Cand.RPDelta.Excess;
2571 P = Cand.RPDelta.CriticalMax;
2574 P = Cand.RPDelta.CurrentMax;
2576 case ResourceReduce:
2577 ResIdx = Cand.Policy.ReduceResIdx;
2579 case ResourceDemand:
2580 ResIdx = Cand.Policy.DemandResIdx;
2582 case TopDepthReduce:
2583 Latency = Cand.SU->getDepth();
2586 Latency = Cand.SU->getHeight();
2588 case BotHeightReduce:
2589 Latency = Cand.SU->getHeight();
2592 Latency = Cand.SU->getDepth();
2595 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason);
2597 dbgs() << " " << TRI->getRegPressureSetName(P.getPSet())
2598 << ":" << P.getUnitInc() << " ";
2602 dbgs() << " " << SchedModel->getProcResource(ResIdx)->Name << " ";
2606 dbgs() << " " << Latency << " cycles ";
2613 /// Pick the best candidate from the top queue.
2615 /// TODO: getMaxPressureDelta results can be mostly cached for each SUnit during
2616 /// DAG building. To adjust for the current scheduling location we need to
2617 /// maintain the number of vreg uses remaining to be top-scheduled.
2618 void ConvergingScheduler::pickNodeFromQueue(SchedBoundary &Zone,
2619 const RegPressureTracker &RPTracker,
2620 SchedCandidate &Cand) {
2621 ReadyQueue &Q = Zone.Available;
2625 // getMaxPressureDelta temporarily modifies the tracker.
2626 RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker);
2628 for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
2630 SchedCandidate TryCand(Cand.Policy);
2632 tryCandidate(Cand, TryCand, Zone, RPTracker, TempTracker);
2633 if (TryCand.Reason != NoCand) {
2634 // Initialize resource delta if needed in case future heuristics query it.
2635 if (TryCand.ResDelta == SchedResourceDelta())
2636 TryCand.initResourceDelta(DAG, SchedModel);
2637 Cand.setBest(TryCand);
2638 DEBUG(traceCandidate(Cand));
2643 static void tracePick(const ConvergingScheduler::SchedCandidate &Cand,
2645 DEBUG(dbgs() << "Pick " << (IsTop ? "Top " : "Bot ")
2646 << ConvergingScheduler::getReasonStr(Cand.Reason) << '\n');
2649 /// Pick the best candidate node from either the top or bottom queue.
2650 SUnit *ConvergingScheduler::pickNodeBidirectional(bool &IsTopNode) {
2651 // Schedule as far as possible in the direction of no choice. This is most
2652 // efficient, but also provides the best heuristics for CriticalPSets.
2653 if (SUnit *SU = Bot.pickOnlyChoice()) {
2655 DEBUG(dbgs() << "Pick Bot NOCAND\n");
2658 if (SUnit *SU = Top.pickOnlyChoice()) {
2660 DEBUG(dbgs() << "Pick Top NOCAND\n");
2663 CandPolicy NoPolicy;
2664 SchedCandidate BotCand(NoPolicy);
2665 SchedCandidate TopCand(NoPolicy);
2666 Bot.setPolicy(BotCand.Policy, Top);
2667 Top.setPolicy(TopCand.Policy, Bot);
2669 // Prefer bottom scheduling when heuristics are silent.
2670 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2671 assert(BotCand.Reason != NoCand && "failed to find the first candidate");
2673 // If either Q has a single candidate that provides the least increase in
2674 // Excess pressure, we can immediately schedule from that Q.
2676 // RegionCriticalPSets summarizes the pressure within the scheduled region and
2677 // affects picking from either Q. If scheduling in one direction must
2678 // increase pressure for one of the excess PSets, then schedule in that
2679 // direction first to provide more freedom in the other direction.
2680 if ((BotCand.Reason == RegExcess && !BotCand.isRepeat(RegExcess))
2681 || (BotCand.Reason == RegCritical
2682 && !BotCand.isRepeat(RegCritical)))
2685 tracePick(BotCand, IsTopNode);
2688 // Check if the top Q has a better candidate.
2689 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2690 assert(TopCand.Reason != NoCand && "failed to find the first candidate");
2692 // Choose the queue with the most important (lowest enum) reason.
2693 if (TopCand.Reason < BotCand.Reason) {
2695 tracePick(TopCand, IsTopNode);
2698 // Otherwise prefer the bottom candidate, in node order if all else failed.
2700 tracePick(BotCand, IsTopNode);
2704 /// Pick the best node to balance the schedule. Implements MachineSchedStrategy.
2705 SUnit *ConvergingScheduler::pickNode(bool &IsTopNode) {
2706 if (DAG->top() == DAG->bottom()) {
2707 assert(Top.Available.empty() && Top.Pending.empty() &&
2708 Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage");
2713 if (RegionPolicy.OnlyTopDown) {
2714 SU = Top.pickOnlyChoice();
2716 CandPolicy NoPolicy;
2717 SchedCandidate TopCand(NoPolicy);
2718 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2719 assert(TopCand.Reason != NoCand && "failed to find a candidate");
2720 tracePick(TopCand, true);
2725 else if (RegionPolicy.OnlyBottomUp) {
2726 SU = Bot.pickOnlyChoice();
2728 CandPolicy NoPolicy;
2729 SchedCandidate BotCand(NoPolicy);
2730 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2731 assert(BotCand.Reason != NoCand && "failed to find a candidate");
2732 tracePick(BotCand, false);
2738 SU = pickNodeBidirectional(IsTopNode);
2740 } while (SU->isScheduled);
2742 if (SU->isTopReady())
2743 Top.removeReady(SU);
2744 if (SU->isBottomReady())
2745 Bot.removeReady(SU);
2747 DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr());
2751 void ConvergingScheduler::reschedulePhysRegCopies(SUnit *SU, bool isTop) {
2753 MachineBasicBlock::iterator InsertPos = SU->getInstr();
2756 SmallVectorImpl<SDep> &Deps = isTop ? SU->Preds : SU->Succs;
2758 // Find already scheduled copies with a single physreg dependence and move
2759 // them just above the scheduled instruction.
2760 for (SmallVectorImpl<SDep>::iterator I = Deps.begin(), E = Deps.end();
2762 if (I->getKind() != SDep::Data || !TRI->isPhysicalRegister(I->getReg()))
2764 SUnit *DepSU = I->getSUnit();
2765 if (isTop ? DepSU->Succs.size() > 1 : DepSU->Preds.size() > 1)
2767 MachineInstr *Copy = DepSU->getInstr();
2768 if (!Copy->isCopy())
2770 DEBUG(dbgs() << " Rescheduling physreg copy ";
2771 I->getSUnit()->dump(DAG));
2772 DAG->moveInstruction(Copy, InsertPos);
2776 /// Update the scheduler's state after scheduling a node. This is the same node
2777 /// that was just returned by pickNode(). However, ScheduleDAGMI needs to update
2778 /// it's state based on the current cycle before MachineSchedStrategy does.
2780 /// FIXME: Eventually, we may bundle physreg copies rather than rescheduling
2781 /// them here. See comments in biasPhysRegCopy.
2782 void ConvergingScheduler::schedNode(SUnit *SU, bool IsTopNode) {
2784 SU->TopReadyCycle = std::max(SU->TopReadyCycle, Top.CurrCycle);
2786 if (SU->hasPhysRegUses)
2787 reschedulePhysRegCopies(SU, true);
2790 SU->BotReadyCycle = std::max(SU->BotReadyCycle, Bot.CurrCycle);
2792 if (SU->hasPhysRegDefs)
2793 reschedulePhysRegCopies(SU, false);
2797 /// Create the standard converging machine scheduler. This will be used as the
2798 /// default scheduler if the target does not set a default.
2799 static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C) {
2800 ScheduleDAGMI *DAG = new ScheduleDAGMI(C, new ConvergingScheduler(C));
2801 // Register DAG post-processors.
2803 // FIXME: extend the mutation API to allow earlier mutations to instantiate
2804 // data and pass it to later mutations. Have a single mutation that gathers
2805 // the interesting nodes in one pass.
2806 DAG->addMutation(new CopyConstrain(DAG->TII, DAG->TRI));
2807 if (EnableLoadCluster && DAG->TII->enableClusterLoads())
2808 DAG->addMutation(new LoadClusterMutation(DAG->TII, DAG->TRI));
2809 if (EnableMacroFusion)
2810 DAG->addMutation(new MacroFusion(DAG->TII));
2813 static MachineSchedRegistry
2814 ConvergingSchedRegistry("converge", "Standard converging scheduler.",
2815 createConvergingSched);
2817 //===----------------------------------------------------------------------===//
2818 // ILP Scheduler. Currently for experimental analysis of heuristics.
2819 //===----------------------------------------------------------------------===//
2822 /// \brief Order nodes by the ILP metric.
2824 const SchedDFSResult *DFSResult;
2825 const BitVector *ScheduledTrees;
2828 ILPOrder(bool MaxILP): DFSResult(0), ScheduledTrees(0), MaximizeILP(MaxILP) {}
2830 /// \brief Apply a less-than relation on node priority.
2832 /// (Return true if A comes after B in the Q.)
2833 bool operator()(const SUnit *A, const SUnit *B) const {
2834 unsigned SchedTreeA = DFSResult->getSubtreeID(A);
2835 unsigned SchedTreeB = DFSResult->getSubtreeID(B);
2836 if (SchedTreeA != SchedTreeB) {
2837 // Unscheduled trees have lower priority.
2838 if (ScheduledTrees->test(SchedTreeA) != ScheduledTrees->test(SchedTreeB))
2839 return ScheduledTrees->test(SchedTreeB);
2841 // Trees with shallower connections have have lower priority.
2842 if (DFSResult->getSubtreeLevel(SchedTreeA)
2843 != DFSResult->getSubtreeLevel(SchedTreeB)) {
2844 return DFSResult->getSubtreeLevel(SchedTreeA)
2845 < DFSResult->getSubtreeLevel(SchedTreeB);
2849 return DFSResult->getILP(A) < DFSResult->getILP(B);
2851 return DFSResult->getILP(A) > DFSResult->getILP(B);
2855 /// \brief Schedule based on the ILP metric.
2856 class ILPScheduler : public MachineSchedStrategy {
2860 std::vector<SUnit*> ReadyQ;
2862 ILPScheduler(bool MaximizeILP): DAG(0), Cmp(MaximizeILP) {}
2864 virtual void initialize(ScheduleDAGMI *dag) {
2866 DAG->computeDFSResult();
2867 Cmp.DFSResult = DAG->getDFSResult();
2868 Cmp.ScheduledTrees = &DAG->getScheduledTrees();
2872 virtual void registerRoots() {
2873 // Restore the heap in ReadyQ with the updated DFS results.
2874 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
2877 /// Implement MachineSchedStrategy interface.
2878 /// -----------------------------------------
2880 /// Callback to select the highest priority node from the ready Q.
2881 virtual SUnit *pickNode(bool &IsTopNode) {
2882 if (ReadyQ.empty()) return NULL;
2883 std::pop_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
2884 SUnit *SU = ReadyQ.back();
2887 DEBUG(dbgs() << "Pick node " << "SU(" << SU->NodeNum << ") "
2888 << " ILP: " << DAG->getDFSResult()->getILP(SU)
2889 << " Tree: " << DAG->getDFSResult()->getSubtreeID(SU) << " @"
2890 << DAG->getDFSResult()->getSubtreeLevel(
2891 DAG->getDFSResult()->getSubtreeID(SU)) << '\n'
2892 << "Scheduling " << *SU->getInstr());
2896 /// \brief Scheduler callback to notify that a new subtree is scheduled.
2897 virtual void scheduleTree(unsigned SubtreeID) {
2898 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
2901 /// Callback after a node is scheduled. Mark a newly scheduled tree, notify
2902 /// DFSResults, and resort the priority Q.
2903 virtual void schedNode(SUnit *SU, bool IsTopNode) {
2904 assert(!IsTopNode && "SchedDFSResult needs bottom-up");
2907 virtual void releaseTopNode(SUnit *) { /*only called for top roots*/ }
2909 virtual void releaseBottomNode(SUnit *SU) {
2910 ReadyQ.push_back(SU);
2911 std::push_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
2916 static ScheduleDAGInstrs *createILPMaxScheduler(MachineSchedContext *C) {
2917 return new ScheduleDAGMI(C, new ILPScheduler(true));
2919 static ScheduleDAGInstrs *createILPMinScheduler(MachineSchedContext *C) {
2920 return new ScheduleDAGMI(C, new ILPScheduler(false));
2922 static MachineSchedRegistry ILPMaxRegistry(
2923 "ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler);
2924 static MachineSchedRegistry ILPMinRegistry(
2925 "ilpmin", "Schedule bottom-up for min ILP", createILPMinScheduler);
2927 //===----------------------------------------------------------------------===//
2928 // Machine Instruction Shuffler for Correctness Testing
2929 //===----------------------------------------------------------------------===//
2933 /// Apply a less-than relation on the node order, which corresponds to the
2934 /// instruction order prior to scheduling. IsReverse implements greater-than.
2935 template<bool IsReverse>
2937 bool operator()(SUnit *A, SUnit *B) const {
2939 return A->NodeNum > B->NodeNum;
2941 return A->NodeNum < B->NodeNum;
2945 /// Reorder instructions as much as possible.
2946 class InstructionShuffler : public MachineSchedStrategy {
2950 // Using a less-than relation (SUnitOrder<false>) for the TopQ priority
2951 // gives nodes with a higher number higher priority causing the latest
2952 // instructions to be scheduled first.
2953 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false> >
2955 // When scheduling bottom-up, use greater-than as the queue priority.
2956 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true> >
2959 InstructionShuffler(bool alternate, bool topdown)
2960 : IsAlternating(alternate), IsTopDown(topdown) {}
2962 virtual void initialize(ScheduleDAGMI *) {
2967 /// Implement MachineSchedStrategy interface.
2968 /// -----------------------------------------
2970 virtual SUnit *pickNode(bool &IsTopNode) {
2974 if (TopQ.empty()) return NULL;
2977 } while (SU->isScheduled);
2982 if (BottomQ.empty()) return NULL;
2985 } while (SU->isScheduled);
2989 IsTopDown = !IsTopDown;
2993 virtual void schedNode(SUnit *SU, bool IsTopNode) {}
2995 virtual void releaseTopNode(SUnit *SU) {
2998 virtual void releaseBottomNode(SUnit *SU) {
3004 static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
3005 bool Alternate = !ForceTopDown && !ForceBottomUp;
3006 bool TopDown = !ForceBottomUp;
3007 assert((TopDown || !ForceTopDown) &&
3008 "-misched-topdown incompatible with -misched-bottomup");
3009 return new ScheduleDAGMI(C, new InstructionShuffler(Alternate, TopDown));
3011 static MachineSchedRegistry ShufflerRegistry(
3012 "shuffle", "Shuffle machine instructions alternating directions",
3013 createInstructionShuffler);
3016 //===----------------------------------------------------------------------===//
3017 // GraphWriter support for ScheduleDAGMI.
3018 //===----------------------------------------------------------------------===//
3023 template<> struct GraphTraits<
3024 ScheduleDAGMI*> : public GraphTraits<ScheduleDAG*> {};
3027 struct DOTGraphTraits<ScheduleDAGMI*> : public DefaultDOTGraphTraits {
3029 DOTGraphTraits (bool isSimple=false) : DefaultDOTGraphTraits(isSimple) {}
3031 static std::string getGraphName(const ScheduleDAG *G) {
3032 return G->MF.getName();
3035 static bool renderGraphFromBottomUp() {
3039 static bool isNodeHidden(const SUnit *Node) {
3040 return (Node->Preds.size() > 10 || Node->Succs.size() > 10);
3043 static bool hasNodeAddressLabel(const SUnit *Node,
3044 const ScheduleDAG *Graph) {
3048 /// If you want to override the dot attributes printed for a particular
3049 /// edge, override this method.
3050 static std::string getEdgeAttributes(const SUnit *Node,
3052 const ScheduleDAG *Graph) {
3053 if (EI.isArtificialDep())
3054 return "color=cyan,style=dashed";
3056 return "color=blue,style=dashed";
3060 static std::string getNodeLabel(const SUnit *SU, const ScheduleDAG *G) {
3062 raw_string_ostream SS(Str);
3063 SS << "SU(" << SU->NodeNum << ')';
3066 static std::string getNodeDescription(const SUnit *SU, const ScheduleDAG *G) {
3067 return G->getGraphNodeLabel(SU);
3070 static std::string getNodeAttributes(const SUnit *N,
3071 const ScheduleDAG *Graph) {
3072 std::string Str("shape=Mrecord");
3073 const SchedDFSResult *DFS =
3074 static_cast<const ScheduleDAGMI*>(Graph)->getDFSResult();
3076 Str += ",style=filled,fillcolor=\"#";
3077 Str += DOT::getColorString(DFS->getSubtreeID(N));
3086 /// viewGraph - Pop up a ghostview window with the reachable parts of the DAG
3087 /// rendered using 'dot'.
3089 void ScheduleDAGMI::viewGraph(const Twine &Name, const Twine &Title) {
3091 ViewGraph(this, Name, false, Title);
3093 errs() << "ScheduleDAGMI::viewGraph is only available in debug builds on "
3094 << "systems with Graphviz or gv!\n";
3098 /// Out-of-line implementation with no arguments is handy for gdb.
3099 void ScheduleDAGMI::viewGraph() {
3100 viewGraph(getDAGName(), "Scheduling-Units Graph for " + getDAGName());