1 //===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MachineScheduler schedules machine instructions after phi elimination. It
11 // preserves LiveIntervals so it can be invoked before register allocation.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "misched"
17 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
18 #include "llvm/CodeGen/MachineScheduler.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/ADT/OwningPtr.h"
34 static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden,
35 cl::desc("Pop up a window to show MISched dags after they are processed"));
37 static bool ViewMISchedDAGs = false;
40 //===----------------------------------------------------------------------===//
41 // Machine Instruction Scheduling Pass and Registry
42 //===----------------------------------------------------------------------===//
45 /// MachineScheduler runs after coalescing and before register allocation.
46 class MachineScheduler : public MachineSchedContext,
47 public MachineFunctionPass {
51 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
53 virtual void releaseMemory() {}
55 virtual bool runOnMachineFunction(MachineFunction&);
57 virtual void print(raw_ostream &O, const Module* = 0) const;
59 static char ID; // Class identification, replacement for typeinfo
63 char MachineScheduler::ID = 0;
65 char &llvm::MachineSchedulerID = MachineScheduler::ID;
67 INITIALIZE_PASS_BEGIN(MachineScheduler, "misched",
68 "Machine Instruction Scheduler", false, false)
69 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
70 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
71 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
72 INITIALIZE_PASS_END(MachineScheduler, "misched",
73 "Machine Instruction Scheduler", false, false)
75 MachineScheduler::MachineScheduler()
76 : MachineFunctionPass(ID) {
77 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
80 void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
82 AU.addRequiredID(MachineDominatorsID);
83 AU.addRequired<MachineLoopInfo>();
84 AU.addRequired<AliasAnalysis>();
85 AU.addRequired<TargetPassConfig>();
86 AU.addRequired<SlotIndexes>();
87 AU.addPreserved<SlotIndexes>();
88 AU.addRequired<LiveIntervals>();
89 AU.addPreserved<LiveIntervals>();
90 MachineFunctionPass::getAnalysisUsage(AU);
93 MachinePassRegistry MachineSchedRegistry::Registry;
95 /// A dummy default scheduler factory indicates whether the scheduler
96 /// is overridden on the command line.
97 static ScheduleDAGInstrs *useDefaultMachineSched(MachineSchedContext *C) {
101 /// MachineSchedOpt allows command line selection of the scheduler.
102 static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
103 RegisterPassParser<MachineSchedRegistry> >
104 MachineSchedOpt("misched",
105 cl::init(&useDefaultMachineSched), cl::Hidden,
106 cl::desc("Machine instruction scheduler to use"));
108 static MachineSchedRegistry
109 SchedDefaultRegistry("default", "Use the target's default scheduler choice.",
110 useDefaultMachineSched);
112 /// Forward declare the common machine scheduler. This will be used as the
113 /// default scheduler if the target does not set a default.
114 static ScheduleDAGInstrs *createCommonMachineSched(MachineSchedContext *C);
116 bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
117 // Initialize the context of the pass.
119 MLI = &getAnalysis<MachineLoopInfo>();
120 MDT = &getAnalysis<MachineDominatorTree>();
121 PassConfig = &getAnalysis<TargetPassConfig>();
122 AA = &getAnalysis<AliasAnalysis>();
124 LIS = &getAnalysis<LiveIntervals>();
125 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
127 // Select the scheduler, or set the default.
128 MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
129 if (Ctor == useDefaultMachineSched) {
130 // Get the default scheduler set by the target.
131 Ctor = MachineSchedRegistry::getDefault();
133 Ctor = createCommonMachineSched;
134 MachineSchedRegistry::setDefault(Ctor);
137 // Instantiate the selected scheduler.
138 OwningPtr<ScheduleDAGInstrs> Scheduler(Ctor(this));
140 // Visit all machine basic blocks.
141 for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
142 MBB != MBBEnd; ++MBB) {
144 Scheduler->startBlock(MBB);
146 // Break the block into scheduling regions [I, RegionEnd), and schedule each
147 // region as soon as it is discovered. RegionEnd points the the scheduling
148 // boundary at the bottom of the region. The DAG does not include RegionEnd,
149 // but the region does (i.e. the next RegionEnd is above the previous
150 // RegionBegin). If the current block has no terminator then RegionEnd ==
151 // MBB->end() for the bottom region.
153 // The Scheduler may insert instructions during either schedule() or
154 // exitRegion(), even for empty regions. So the local iterators 'I' and
155 // 'RegionEnd' are invalid across these calls.
156 unsigned RemainingCount = MBB->size();
157 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
158 RegionEnd != MBB->begin(); RegionEnd = Scheduler->begin()) {
159 // Avoid decrementing RegionEnd for blocks with no terminator.
160 if (RegionEnd != MBB->end()
161 || TII->isSchedulingBoundary(llvm::prior(RegionEnd), MBB, *MF)) {
163 // Count the boundary instruction.
167 // The next region starts above the previous region. Look backward in the
168 // instruction stream until we find the nearest boundary.
169 MachineBasicBlock::iterator I = RegionEnd;
170 for(;I != MBB->begin(); --I, --RemainingCount) {
171 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, *MF))
174 // Notify the scheduler of the region, even if we may skip scheduling
175 // it. Perhaps it still needs to be bundled.
176 Scheduler->enterRegion(MBB, I, RegionEnd, RemainingCount);
178 // Skip empty scheduling regions (0 or 1 schedulable instructions).
179 if (I == RegionEnd || I == llvm::prior(RegionEnd)) {
180 // Close the current region. Bundle the terminator if needed.
181 // This invalidates 'RegionEnd' and 'I'.
182 Scheduler->exitRegion();
185 DEBUG(dbgs() << "MachineScheduling " << MF->getFunction()->getName()
186 << ":BB#" << MBB->getNumber() << "\n From: " << *I << " To: ";
187 if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
188 else dbgs() << "End";
189 dbgs() << " Remaining: " << RemainingCount << "\n");
191 // Schedule a region: possibly reorder instructions.
192 // This invalidates 'RegionEnd' and 'I'.
193 Scheduler->schedule();
195 // Close the current region.
196 Scheduler->exitRegion();
198 // Scheduling has invalidated the current iterator 'I'. Ask the
199 // scheduler for the top of it's scheduled region.
200 RegionEnd = Scheduler->begin();
202 assert(RemainingCount == 0 && "Instruction count mismatch!");
203 Scheduler->finishBlock();
208 void MachineScheduler::print(raw_ostream &O, const Module* m) const {
212 //===----------------------------------------------------------------------===//
213 // ScheduleTopeDownLive - Base class for basic top-down scheduling with
214 // LiveIntervals preservation.
215 // ===----------------------------------------------------------------------===//
218 /// ScheduleTopDownLive is an implementation of ScheduleDAGInstrs that schedules
219 /// machine instructions while updating LiveIntervals.
220 class ScheduleTopDownLive : public ScheduleDAGInstrs {
223 ScheduleTopDownLive(MachineSchedContext *C):
224 ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
227 /// ScheduleDAGInstrs interface.
230 /// Interface implemented by the selected top-down liveinterval scheduler.
232 /// Pick the next node to schedule, or return NULL.
233 virtual SUnit *pickNode() = 0;
235 /// When all preceeding dependencies have been resolved, free this node for
237 virtual void releaseNode(SUnit *SU) = 0;
240 void releaseSucc(SUnit *SU, SDep *SuccEdge);
241 void releaseSuccessors(SUnit *SU);
245 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
246 /// NumPredsLeft reaches zero, release the successor node.
247 void ScheduleTopDownLive::releaseSucc(SUnit *SU, SDep *SuccEdge) {
248 SUnit *SuccSU = SuccEdge->getSUnit();
251 if (SuccSU->NumPredsLeft == 0) {
252 dbgs() << "*** Scheduling failed! ***\n";
254 dbgs() << " has been released too many times!\n";
258 --SuccSU->NumPredsLeft;
259 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
263 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
264 void ScheduleTopDownLive::releaseSuccessors(SUnit *SU) {
265 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
267 releaseSucc(SU, &*I);
271 /// schedule - This is called back from ScheduleDAGInstrs::Run() when it's
272 /// time to do some work.
273 void ScheduleTopDownLive::schedule() {
276 DEBUG(dbgs() << "********** MI Scheduling **********\n");
277 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
278 SUnits[su].dumpAll(this));
280 if (ViewMISchedDAGs) viewGraph();
282 // Release any successors of the special Entry node. It is currently unused,
283 // but we keep up appearances.
284 releaseSuccessors(&EntrySU);
286 // Release all DAG roots for scheduling.
287 for (std::vector<SUnit>::iterator I = SUnits.begin(), E = SUnits.end();
289 // A SUnit is ready to schedule if it has no predecessors.
290 if (I->Preds.empty())
294 MachineBasicBlock::iterator InsertPos = RegionBegin;
295 while (SUnit *SU = pickNode()) {
296 DEBUG(dbgs() << "*** Scheduling Instruction:\n"; SU->dump(this));
298 // Move the instruction to its new location in the instruction stream.
299 MachineInstr *MI = SU->getInstr();
300 if (&*InsertPos == MI)
303 BB->splice(InsertPos, BB, MI);
305 if (RegionBegin == InsertPos)
309 // Release dependent instructions for scheduling.
310 releaseSuccessors(SU);
314 //===----------------------------------------------------------------------===//
315 // Placeholder for the default machine instruction scheduler.
316 //===----------------------------------------------------------------------===//
319 class CommonMachineScheduler : public ScheduleDAGInstrs {
322 CommonMachineScheduler(MachineSchedContext *C):
323 ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
326 /// schedule - This is called back from ScheduleDAGInstrs::Run() when it's
327 /// time to do some work.
332 /// The common machine scheduler will be used as the default scheduler if the
333 /// target does not set a default.
334 static ScheduleDAGInstrs *createCommonMachineSched(MachineSchedContext *C) {
335 return new CommonMachineScheduler(C);
337 static MachineSchedRegistry
338 SchedCommonRegistry("common", "Use the target's default scheduler choice.",
339 createCommonMachineSched);
341 /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
342 /// time to do some work.
343 void CommonMachineScheduler::schedule() {
346 DEBUG(dbgs() << "********** MI Scheduling **********\n");
347 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
348 SUnits[su].dumpAll(this));
350 // TODO: Put interesting things here.
352 // When this is fully implemented, it will become a subclass of
353 // ScheduleTopDownLive. So this driver will disappear.
356 //===----------------------------------------------------------------------===//
357 // Machine Instruction Shuffler for Correctness Testing
358 //===----------------------------------------------------------------------===//
362 // Nodes with a higher number have higher priority. This way we attempt to
363 // schedule the latest instructions earliest.
365 // TODO: Relies on the property of the BuildSchedGraph that results in SUnits
366 // being ordered in sequence top-down.
367 struct ShuffleSUnitOrder {
368 bool operator()(SUnit *A, SUnit *B) const {
369 return A->NodeNum < B->NodeNum;
373 /// Reorder instructions as much as possible.
374 class InstructionShuffler : public ScheduleTopDownLive {
375 std::priority_queue<SUnit*, std::vector<SUnit*>, ShuffleSUnitOrder> Queue;
377 InstructionShuffler(MachineSchedContext *C):
378 ScheduleTopDownLive(C) {}
380 /// ScheduleTopDownLive Interface
382 virtual SUnit *pickNode() {
383 if (Queue.empty()) return NULL;
384 SUnit *SU = Queue.top();
389 virtual void releaseNode(SUnit *SU) {
395 static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
396 return new InstructionShuffler(C);
398 static MachineSchedRegistry ShufflerRegistry("shuffle",
399 "Shuffle machine instructions",
400 createInstructionShuffler);