1 //===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MachineScheduler schedules machine instructions after phi elimination. It
11 // preserves LiveIntervals so it can be invoked before register allocation.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/MachineScheduler.h"
16 #include "llvm/ADT/PriorityQueue.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/MachineDominators.h"
20 #include "llvm/CodeGen/MachineLoopInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/CodeGen/RegisterClassInfo.h"
24 #include "llvm/CodeGen/ScheduleDFS.h"
25 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/GraphWriter.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/Target/TargetInstrInfo.h"
36 #define DEBUG_TYPE "misched"
39 cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
40 cl::desc("Force top-down list scheduling"));
41 cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
42 cl::desc("Force bottom-up list scheduling"));
44 DumpCriticalPathLength("misched-dcpl", cl::Hidden,
45 cl::desc("Print critical path length to stdout"));
49 static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden,
50 cl::desc("Pop up a window to show MISched dags after they are processed"));
52 static cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden,
53 cl::desc("Stop scheduling after N instructions"), cl::init(~0U));
55 static cl::opt<std::string> SchedOnlyFunc("misched-only-func", cl::Hidden,
56 cl::desc("Only schedule this function"));
57 static cl::opt<unsigned> SchedOnlyBlock("misched-only-block", cl::Hidden,
58 cl::desc("Only schedule this MBB#"));
60 static bool ViewMISchedDAGs = false;
63 static cl::opt<bool> EnableRegPressure("misched-regpressure", cl::Hidden,
64 cl::desc("Enable register pressure scheduling."), cl::init(true));
66 static cl::opt<bool> EnableCyclicPath("misched-cyclicpath", cl::Hidden,
67 cl::desc("Enable cyclic critical path analysis."), cl::init(true));
69 static cl::opt<bool> EnableLoadCluster("misched-cluster", cl::Hidden,
70 cl::desc("Enable load clustering."), cl::init(true));
72 // Experimental heuristics
73 static cl::opt<bool> EnableMacroFusion("misched-fusion", cl::Hidden,
74 cl::desc("Enable scheduling for macro fusion."), cl::init(true));
76 static cl::opt<bool> VerifyScheduling("verify-misched", cl::Hidden,
77 cl::desc("Verify machine instrs before and after machine scheduling"));
79 // DAG subtrees must have at least this many nodes.
80 static const unsigned MinSubtreeSize = 8;
82 // Pin the vtables to this file.
83 void MachineSchedStrategy::anchor() {}
84 void ScheduleDAGMutation::anchor() {}
86 //===----------------------------------------------------------------------===//
87 // Machine Instruction Scheduling Pass and Registry
88 //===----------------------------------------------------------------------===//
90 MachineSchedContext::MachineSchedContext():
91 MF(nullptr), MLI(nullptr), MDT(nullptr), PassConfig(nullptr), AA(nullptr), LIS(nullptr) {
92 RegClassInfo = new RegisterClassInfo();
95 MachineSchedContext::~MachineSchedContext() {
100 /// Base class for a machine scheduler class that can run at any point.
101 class MachineSchedulerBase : public MachineSchedContext,
102 public MachineFunctionPass {
104 MachineSchedulerBase(char &ID): MachineFunctionPass(ID) {}
106 void print(raw_ostream &O, const Module* = nullptr) const override;
109 void scheduleRegions(ScheduleDAGInstrs &Scheduler);
112 /// MachineScheduler runs after coalescing and before register allocation.
113 class MachineScheduler : public MachineSchedulerBase {
117 void getAnalysisUsage(AnalysisUsage &AU) const override;
119 bool runOnMachineFunction(MachineFunction&) override;
121 static char ID; // Class identification, replacement for typeinfo
124 ScheduleDAGInstrs *createMachineScheduler();
127 /// PostMachineScheduler runs after shortly before code emission.
128 class PostMachineScheduler : public MachineSchedulerBase {
130 PostMachineScheduler();
132 void getAnalysisUsage(AnalysisUsage &AU) const override;
134 bool runOnMachineFunction(MachineFunction&) override;
136 static char ID; // Class identification, replacement for typeinfo
139 ScheduleDAGInstrs *createPostMachineScheduler();
143 char MachineScheduler::ID = 0;
145 char &llvm::MachineSchedulerID = MachineScheduler::ID;
147 INITIALIZE_PASS_BEGIN(MachineScheduler, "machine-scheduler",
148 "Machine Instruction Scheduler", false, false)
149 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
150 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
151 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
152 INITIALIZE_PASS_END(MachineScheduler, "machine-scheduler",
153 "Machine Instruction Scheduler", false, false)
155 MachineScheduler::MachineScheduler()
156 : MachineSchedulerBase(ID) {
157 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
160 void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
161 AU.setPreservesCFG();
162 AU.addRequiredID(MachineDominatorsID);
163 AU.addRequired<MachineLoopInfo>();
164 AU.addRequired<AliasAnalysis>();
165 AU.addRequired<TargetPassConfig>();
166 AU.addRequired<SlotIndexes>();
167 AU.addPreserved<SlotIndexes>();
168 AU.addRequired<LiveIntervals>();
169 AU.addPreserved<LiveIntervals>();
170 MachineFunctionPass::getAnalysisUsage(AU);
173 char PostMachineScheduler::ID = 0;
175 char &llvm::PostMachineSchedulerID = PostMachineScheduler::ID;
177 INITIALIZE_PASS(PostMachineScheduler, "postmisched",
178 "PostRA Machine Instruction Scheduler", false, false)
180 PostMachineScheduler::PostMachineScheduler()
181 : MachineSchedulerBase(ID) {
182 initializePostMachineSchedulerPass(*PassRegistry::getPassRegistry());
185 void PostMachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
186 AU.setPreservesCFG();
187 AU.addRequiredID(MachineDominatorsID);
188 AU.addRequired<MachineLoopInfo>();
189 AU.addRequired<TargetPassConfig>();
190 MachineFunctionPass::getAnalysisUsage(AU);
193 MachinePassRegistry MachineSchedRegistry::Registry;
195 /// A dummy default scheduler factory indicates whether the scheduler
196 /// is overridden on the command line.
197 static ScheduleDAGInstrs *useDefaultMachineSched(MachineSchedContext *C) {
201 /// MachineSchedOpt allows command line selection of the scheduler.
202 static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
203 RegisterPassParser<MachineSchedRegistry> >
204 MachineSchedOpt("misched",
205 cl::init(&useDefaultMachineSched), cl::Hidden,
206 cl::desc("Machine instruction scheduler to use"));
208 static MachineSchedRegistry
209 DefaultSchedRegistry("default", "Use the target's default scheduler choice.",
210 useDefaultMachineSched);
212 /// Forward declare the standard machine scheduler. This will be used as the
213 /// default scheduler if the target does not set a default.
214 static ScheduleDAGInstrs *createGenericSchedLive(MachineSchedContext *C);
215 static ScheduleDAGInstrs *createGenericSchedPostRA(MachineSchedContext *C);
217 /// Decrement this iterator until reaching the top or a non-debug instr.
218 static MachineBasicBlock::const_iterator
219 priorNonDebug(MachineBasicBlock::const_iterator I,
220 MachineBasicBlock::const_iterator Beg) {
221 assert(I != Beg && "reached the top of the region, cannot decrement");
223 if (!I->isDebugValue())
229 /// Non-const version.
230 static MachineBasicBlock::iterator
231 priorNonDebug(MachineBasicBlock::iterator I,
232 MachineBasicBlock::const_iterator Beg) {
233 return const_cast<MachineInstr*>(
234 &*priorNonDebug(MachineBasicBlock::const_iterator(I), Beg));
237 /// If this iterator is a debug value, increment until reaching the End or a
238 /// non-debug instruction.
239 static MachineBasicBlock::const_iterator
240 nextIfDebug(MachineBasicBlock::const_iterator I,
241 MachineBasicBlock::const_iterator End) {
242 for(; I != End; ++I) {
243 if (!I->isDebugValue())
249 /// Non-const version.
250 static MachineBasicBlock::iterator
251 nextIfDebug(MachineBasicBlock::iterator I,
252 MachineBasicBlock::const_iterator End) {
253 // Cast the return value to nonconst MachineInstr, then cast to an
254 // instr_iterator, which does not check for null, finally return a
256 return MachineBasicBlock::instr_iterator(
257 const_cast<MachineInstr*>(
258 &*nextIfDebug(MachineBasicBlock::const_iterator(I), End)));
261 /// Instantiate a ScheduleDAGInstrs that will be owned by the caller.
262 ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() {
263 // Select the scheduler, or set the default.
264 MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
265 if (Ctor != useDefaultMachineSched)
268 // Get the default scheduler set by the target for this function.
269 ScheduleDAGInstrs *Scheduler = PassConfig->createMachineScheduler(this);
273 // Default to GenericScheduler.
274 return createGenericSchedLive(this);
277 /// Instantiate a ScheduleDAGInstrs for PostRA scheduling that will be owned by
278 /// the caller. We don't have a command line option to override the postRA
279 /// scheduler. The Target must configure it.
280 ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
281 // Get the postRA scheduler set by the target for this function.
282 ScheduleDAGInstrs *Scheduler = PassConfig->createPostMachineScheduler(this);
286 // Default to GenericScheduler.
287 return createGenericSchedPostRA(this);
290 /// Top-level MachineScheduler pass driver.
292 /// Visit blocks in function order. Divide each block into scheduling regions
293 /// and visit them bottom-up. Visiting regions bottom-up is not required, but is
294 /// consistent with the DAG builder, which traverses the interior of the
295 /// scheduling regions bottom-up.
297 /// This design avoids exposing scheduling boundaries to the DAG builder,
298 /// simplifying the DAG builder's support for "special" target instructions.
299 /// At the same time the design allows target schedulers to operate across
300 /// scheduling boundaries, for example to bundle the boudary instructions
301 /// without reordering them. This creates complexity, because the target
302 /// scheduler must update the RegionBegin and RegionEnd positions cached by
303 /// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler
304 /// design would be to split blocks at scheduling boundaries, but LLVM has a
305 /// general bias against block splitting purely for implementation simplicity.
306 bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
307 DEBUG(dbgs() << "Before MISsched:\n"; mf.print(dbgs()));
309 // Initialize the context of the pass.
311 MLI = &getAnalysis<MachineLoopInfo>();
312 MDT = &getAnalysis<MachineDominatorTree>();
313 PassConfig = &getAnalysis<TargetPassConfig>();
314 AA = &getAnalysis<AliasAnalysis>();
316 LIS = &getAnalysis<LiveIntervals>();
318 if (VerifyScheduling) {
320 MF->verify(this, "Before machine scheduling.");
322 RegClassInfo->runOnMachineFunction(*MF);
324 // Instantiate the selected scheduler for this target, function, and
325 // optimization level.
326 std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler());
327 scheduleRegions(*Scheduler);
330 if (VerifyScheduling)
331 MF->verify(this, "After machine scheduling.");
335 bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) {
336 if (skipOptnoneFunction(*mf.getFunction()))
339 const TargetSubtargetInfo &ST =
340 mf.getTarget().getSubtarget<TargetSubtargetInfo>();
341 if (!ST.enablePostMachineScheduler()) {
342 DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n");
345 DEBUG(dbgs() << "Before post-MI-sched:\n"; mf.print(dbgs()));
347 // Initialize the context of the pass.
349 PassConfig = &getAnalysis<TargetPassConfig>();
351 if (VerifyScheduling)
352 MF->verify(this, "Before post machine scheduling.");
354 // Instantiate the selected scheduler for this target, function, and
355 // optimization level.
356 std::unique_ptr<ScheduleDAGInstrs> Scheduler(createPostMachineScheduler());
357 scheduleRegions(*Scheduler);
359 if (VerifyScheduling)
360 MF->verify(this, "After post machine scheduling.");
364 /// Return true of the given instruction should not be included in a scheduling
367 /// MachineScheduler does not currently support scheduling across calls. To
368 /// handle calls, the DAG builder needs to be modified to create register
369 /// anti/output dependencies on the registers clobbered by the call's regmask
370 /// operand. In PreRA scheduling, the stack pointer adjustment already prevents
371 /// scheduling across calls. In PostRA scheduling, we need the isCall to enforce
372 /// the boundary, but there would be no benefit to postRA scheduling across
373 /// calls this late anyway.
374 static bool isSchedBoundary(MachineBasicBlock::iterator MI,
375 MachineBasicBlock *MBB,
377 const TargetInstrInfo *TII,
379 return MI->isCall() || TII->isSchedulingBoundary(MI, MBB, *MF);
382 /// Main driver for both MachineScheduler and PostMachineScheduler.
383 void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler) {
384 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
385 bool IsPostRA = Scheduler.isPostRA();
387 // Visit all machine basic blocks.
389 // TODO: Visit blocks in global postorder or postorder within the bottom-up
390 // loop tree. Then we can optionally compute global RegPressure.
391 for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
392 MBB != MBBEnd; ++MBB) {
394 Scheduler.startBlock(MBB);
397 if (SchedOnlyFunc.getNumOccurrences() && SchedOnlyFunc != MF->getName())
399 if (SchedOnlyBlock.getNumOccurrences()
400 && (int)SchedOnlyBlock != MBB->getNumber())
404 // Break the block into scheduling regions [I, RegionEnd), and schedule each
405 // region as soon as it is discovered. RegionEnd points the scheduling
406 // boundary at the bottom of the region. The DAG does not include RegionEnd,
407 // but the region does (i.e. the next RegionEnd is above the previous
408 // RegionBegin). If the current block has no terminator then RegionEnd ==
409 // MBB->end() for the bottom region.
411 // The Scheduler may insert instructions during either schedule() or
412 // exitRegion(), even for empty regions. So the local iterators 'I' and
413 // 'RegionEnd' are invalid across these calls.
415 // MBB::size() uses instr_iterator to count. Here we need a bundle to count
416 // as a single instruction.
417 unsigned RemainingInstrs = std::distance(MBB->begin(), MBB->end());
418 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
419 RegionEnd != MBB->begin(); RegionEnd = Scheduler.begin()) {
421 // Avoid decrementing RegionEnd for blocks with no terminator.
422 if (RegionEnd != MBB->end() ||
423 isSchedBoundary(std::prev(RegionEnd), MBB, MF, TII, IsPostRA)) {
425 // Count the boundary instruction.
429 // The next region starts above the previous region. Look backward in the
430 // instruction stream until we find the nearest boundary.
431 unsigned NumRegionInstrs = 0;
432 MachineBasicBlock::iterator I = RegionEnd;
433 for(;I != MBB->begin(); --I, --RemainingInstrs) {
434 if (isSchedBoundary(std::prev(I), MBB, MF, TII, IsPostRA))
436 if (!I->isDebugValue())
439 // Notify the scheduler of the region, even if we may skip scheduling
440 // it. Perhaps it still needs to be bundled.
441 Scheduler.enterRegion(MBB, I, RegionEnd, NumRegionInstrs);
443 // Skip empty scheduling regions (0 or 1 schedulable instructions).
444 if (I == RegionEnd || I == std::prev(RegionEnd)) {
445 // Close the current region. Bundle the terminator if needed.
446 // This invalidates 'RegionEnd' and 'I'.
447 Scheduler.exitRegion();
450 DEBUG(dbgs() << "********** " << ((Scheduler.isPostRA()) ? "PostRA " : "")
451 << "MI Scheduling **********\n");
452 DEBUG(dbgs() << MF->getName()
453 << ":BB#" << MBB->getNumber() << " " << MBB->getName()
454 << "\n From: " << *I << " To: ";
455 if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
456 else dbgs() << "End";
457 dbgs() << " RegionInstrs: " << NumRegionInstrs
458 << " Remaining: " << RemainingInstrs << "\n");
459 if (DumpCriticalPathLength) {
460 errs() << MF->getName();
461 errs() << ":BB# " << MBB->getNumber();
462 errs() << " " << MBB->getName() << " \n";
465 // Schedule a region: possibly reorder instructions.
466 // This invalidates 'RegionEnd' and 'I'.
467 Scheduler.schedule();
469 // Close the current region.
470 Scheduler.exitRegion();
472 // Scheduling has invalidated the current iterator 'I'. Ask the
473 // scheduler for the top of it's scheduled region.
474 RegionEnd = Scheduler.begin();
476 assert(RemainingInstrs == 0 && "Instruction count mismatch!");
477 Scheduler.finishBlock();
478 if (Scheduler.isPostRA()) {
479 // FIXME: Ideally, no further passes should rely on kill flags. However,
480 // thumb2 size reduction is currently an exception.
481 Scheduler.fixupKills(MBB);
484 Scheduler.finalizeSchedule();
487 void MachineSchedulerBase::print(raw_ostream &O, const Module* m) const {
492 void ReadyQueue::dump() {
493 dbgs() << Name << ": ";
494 for (unsigned i = 0, e = Queue.size(); i < e; ++i)
495 dbgs() << Queue[i]->NodeNum << " ";
499 //===----------------------------------------------------------------------===//
500 // ScheduleDAGMI - Basic machine instruction scheduling. This is
501 // independent of PreRA/PostRA scheduling and involves no extra book-keeping for
502 // virtual registers.
503 // ===----------------------------------------------------------------------===/
505 // Provide a vtable anchor.
506 ScheduleDAGMI::~ScheduleDAGMI() {
509 bool ScheduleDAGMI::canAddEdge(SUnit *SuccSU, SUnit *PredSU) {
510 return SuccSU == &ExitSU || !Topo.IsReachable(PredSU, SuccSU);
513 bool ScheduleDAGMI::addEdge(SUnit *SuccSU, const SDep &PredDep) {
514 if (SuccSU != &ExitSU) {
515 // Do not use WillCreateCycle, it assumes SD scheduling.
516 // If Pred is reachable from Succ, then the edge creates a cycle.
517 if (Topo.IsReachable(PredDep.getSUnit(), SuccSU))
519 Topo.AddPred(SuccSU, PredDep.getSUnit());
521 SuccSU->addPred(PredDep, /*Required=*/!PredDep.isArtificial());
522 // Return true regardless of whether a new edge needed to be inserted.
526 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
527 /// NumPredsLeft reaches zero, release the successor node.
529 /// FIXME: Adjust SuccSU height based on MinLatency.
530 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
531 SUnit *SuccSU = SuccEdge->getSUnit();
533 if (SuccEdge->isWeak()) {
534 --SuccSU->WeakPredsLeft;
535 if (SuccEdge->isCluster())
536 NextClusterSucc = SuccSU;
540 if (SuccSU->NumPredsLeft == 0) {
541 dbgs() << "*** Scheduling failed! ***\n";
543 dbgs() << " has been released too many times!\n";
544 llvm_unreachable(nullptr);
547 // SU->TopReadyCycle was set to CurrCycle when it was scheduled. However,
548 // CurrCycle may have advanced since then.
549 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency())
550 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency();
552 --SuccSU->NumPredsLeft;
553 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
554 SchedImpl->releaseTopNode(SuccSU);
557 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
558 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
559 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
561 releaseSucc(SU, &*I);
565 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. When
566 /// NumSuccsLeft reaches zero, release the predecessor node.
568 /// FIXME: Adjust PredSU height based on MinLatency.
569 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
570 SUnit *PredSU = PredEdge->getSUnit();
572 if (PredEdge->isWeak()) {
573 --PredSU->WeakSuccsLeft;
574 if (PredEdge->isCluster())
575 NextClusterPred = PredSU;
579 if (PredSU->NumSuccsLeft == 0) {
580 dbgs() << "*** Scheduling failed! ***\n";
582 dbgs() << " has been released too many times!\n";
583 llvm_unreachable(nullptr);
586 // SU->BotReadyCycle was set to CurrCycle when it was scheduled. However,
587 // CurrCycle may have advanced since then.
588 if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency())
589 PredSU->BotReadyCycle = SU->BotReadyCycle + PredEdge->getLatency();
591 --PredSU->NumSuccsLeft;
592 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU)
593 SchedImpl->releaseBottomNode(PredSU);
596 /// releasePredecessors - Call releasePred on each of SU's predecessors.
597 void ScheduleDAGMI::releasePredecessors(SUnit *SU) {
598 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
600 releasePred(SU, &*I);
604 /// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
605 /// crossing a scheduling boundary. [begin, end) includes all instructions in
606 /// the region, including the boundary itself and single-instruction regions
607 /// that don't get scheduled.
608 void ScheduleDAGMI::enterRegion(MachineBasicBlock *bb,
609 MachineBasicBlock::iterator begin,
610 MachineBasicBlock::iterator end,
611 unsigned regioninstrs)
613 ScheduleDAGInstrs::enterRegion(bb, begin, end, regioninstrs);
615 SchedImpl->initPolicy(begin, end, regioninstrs);
618 /// This is normally called from the main scheduler loop but may also be invoked
619 /// by the scheduling strategy to perform additional code motion.
620 void ScheduleDAGMI::moveInstruction(
621 MachineInstr *MI, MachineBasicBlock::iterator InsertPos) {
622 // Advance RegionBegin if the first instruction moves down.
623 if (&*RegionBegin == MI)
626 // Update the instruction stream.
627 BB->splice(InsertPos, BB, MI);
629 // Update LiveIntervals
631 LIS->handleMove(MI, /*UpdateFlags=*/true);
633 // Recede RegionBegin if an instruction moves above the first.
634 if (RegionBegin == InsertPos)
638 bool ScheduleDAGMI::checkSchedLimit() {
640 if (NumInstrsScheduled == MISchedCutoff && MISchedCutoff != ~0U) {
641 CurrentTop = CurrentBottom;
644 ++NumInstrsScheduled;
649 /// Per-region scheduling driver, called back from
650 /// MachineScheduler::runOnMachineFunction. This is a simplified driver that
651 /// does not consider liveness or register pressure. It is useful for PostRA
652 /// scheduling and potentially other custom schedulers.
653 void ScheduleDAGMI::schedule() {
657 Topo.InitDAGTopologicalSorting();
661 SmallVector<SUnit*, 8> TopRoots, BotRoots;
662 findRootsAndBiasEdges(TopRoots, BotRoots);
664 // Initialize the strategy before modifying the DAG.
665 // This may initialize a DFSResult to be used for queue priority.
666 SchedImpl->initialize(this);
668 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
669 SUnits[su].dumpAll(this));
670 if (ViewMISchedDAGs) viewGraph();
672 // Initialize ready queues now that the DAG and priority data are finalized.
673 initQueues(TopRoots, BotRoots);
675 bool IsTopNode = false;
676 while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) {
677 assert(!SU->isScheduled && "Node already scheduled");
678 if (!checkSchedLimit())
681 MachineInstr *MI = SU->getInstr();
683 assert(SU->isTopReady() && "node still has unscheduled dependencies");
684 if (&*CurrentTop == MI)
685 CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);
687 moveInstruction(MI, CurrentTop);
690 assert(SU->isBottomReady() && "node still has unscheduled dependencies");
691 MachineBasicBlock::iterator priorII =
692 priorNonDebug(CurrentBottom, CurrentTop);
694 CurrentBottom = priorII;
696 if (&*CurrentTop == MI)
697 CurrentTop = nextIfDebug(++CurrentTop, priorII);
698 moveInstruction(MI, CurrentBottom);
702 // Notify the scheduling strategy before updating the DAG.
703 // This sets the scheduled node's ReadyCycle to CurrCycle. When updateQueues
704 // runs, it can then use the accurate ReadyCycle time to determine whether
705 // newly released nodes can move to the readyQ.
706 SchedImpl->schedNode(SU, IsTopNode);
708 updateQueues(SU, IsTopNode);
710 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
715 unsigned BBNum = begin()->getParent()->getNumber();
716 dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
722 /// Apply each ScheduleDAGMutation step in order.
723 void ScheduleDAGMI::postprocessDAG() {
724 for (unsigned i = 0, e = Mutations.size(); i < e; ++i) {
725 Mutations[i]->apply(this);
730 findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots,
731 SmallVectorImpl<SUnit*> &BotRoots) {
732 for (std::vector<SUnit>::iterator
733 I = SUnits.begin(), E = SUnits.end(); I != E; ++I) {
735 assert(!SU->isBoundaryNode() && "Boundary node should not be in SUnits");
737 // Order predecessors so DFSResult follows the critical path.
738 SU->biasCriticalPath();
740 // A SUnit is ready to top schedule if it has no predecessors.
741 if (!I->NumPredsLeft)
742 TopRoots.push_back(SU);
743 // A SUnit is ready to bottom schedule if it has no successors.
744 if (!I->NumSuccsLeft)
745 BotRoots.push_back(SU);
747 ExitSU.biasCriticalPath();
750 /// Identify DAG roots and setup scheduler queues.
751 void ScheduleDAGMI::initQueues(ArrayRef<SUnit*> TopRoots,
752 ArrayRef<SUnit*> BotRoots) {
753 NextClusterSucc = nullptr;
754 NextClusterPred = nullptr;
756 // Release all DAG roots for scheduling, not including EntrySU/ExitSU.
758 // Nodes with unreleased weak edges can still be roots.
759 // Release top roots in forward order.
760 for (SmallVectorImpl<SUnit*>::const_iterator
761 I = TopRoots.begin(), E = TopRoots.end(); I != E; ++I) {
762 SchedImpl->releaseTopNode(*I);
764 // Release bottom roots in reverse order so the higher priority nodes appear
765 // first. This is more natural and slightly more efficient.
766 for (SmallVectorImpl<SUnit*>::const_reverse_iterator
767 I = BotRoots.rbegin(), E = BotRoots.rend(); I != E; ++I) {
768 SchedImpl->releaseBottomNode(*I);
771 releaseSuccessors(&EntrySU);
772 releasePredecessors(&ExitSU);
774 SchedImpl->registerRoots();
776 // Advance past initial DebugValues.
777 CurrentTop = nextIfDebug(RegionBegin, RegionEnd);
778 CurrentBottom = RegionEnd;
781 /// Update scheduler queues after scheduling an instruction.
782 void ScheduleDAGMI::updateQueues(SUnit *SU, bool IsTopNode) {
783 // Release dependent instructions for scheduling.
785 releaseSuccessors(SU);
787 releasePredecessors(SU);
789 SU->isScheduled = true;
792 /// Reinsert any remaining debug_values, just like the PostRA scheduler.
793 void ScheduleDAGMI::placeDebugValues() {
794 // If first instruction was a DBG_VALUE then put it back.
796 BB->splice(RegionBegin, BB, FirstDbgValue);
797 RegionBegin = FirstDbgValue;
800 for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
801 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
802 std::pair<MachineInstr *, MachineInstr *> P = *std::prev(DI);
803 MachineInstr *DbgValue = P.first;
804 MachineBasicBlock::iterator OrigPrevMI = P.second;
805 if (&*RegionBegin == DbgValue)
807 BB->splice(++OrigPrevMI, BB, DbgValue);
808 if (OrigPrevMI == std::prev(RegionEnd))
809 RegionEnd = DbgValue;
812 FirstDbgValue = nullptr;
815 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
816 void ScheduleDAGMI::dumpSchedule() const {
817 for (MachineBasicBlock::iterator MI = begin(), ME = end(); MI != ME; ++MI) {
818 if (SUnit *SU = getSUnit(&(*MI)))
821 dbgs() << "Missing SUnit\n";
826 //===----------------------------------------------------------------------===//
827 // ScheduleDAGMILive - Base class for MachineInstr scheduling with LiveIntervals
829 //===----------------------------------------------------------------------===//
831 ScheduleDAGMILive::~ScheduleDAGMILive() {
835 /// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
836 /// crossing a scheduling boundary. [begin, end) includes all instructions in
837 /// the region, including the boundary itself and single-instruction regions
838 /// that don't get scheduled.
839 void ScheduleDAGMILive::enterRegion(MachineBasicBlock *bb,
840 MachineBasicBlock::iterator begin,
841 MachineBasicBlock::iterator end,
842 unsigned regioninstrs)
844 // ScheduleDAGMI initializes SchedImpl's per-region policy.
845 ScheduleDAGMI::enterRegion(bb, begin, end, regioninstrs);
847 // For convenience remember the end of the liveness region.
848 LiveRegionEnd = (RegionEnd == bb->end()) ? RegionEnd : std::next(RegionEnd);
850 SUPressureDiffs.clear();
852 ShouldTrackPressure = SchedImpl->shouldTrackPressure();
855 // Setup the register pressure trackers for the top scheduled top and bottom
856 // scheduled regions.
857 void ScheduleDAGMILive::initRegPressure() {
858 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin);
859 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
861 // Close the RPTracker to finalize live ins.
862 RPTracker.closeRegion();
864 DEBUG(RPTracker.dump());
866 // Initialize the live ins and live outs.
867 TopRPTracker.addLiveRegs(RPTracker.getPressure().LiveInRegs);
868 BotRPTracker.addLiveRegs(RPTracker.getPressure().LiveOutRegs);
870 // Close one end of the tracker so we can call
871 // getMaxUpward/DownwardPressureDelta before advancing across any
872 // instructions. This converts currently live regs into live ins/outs.
873 TopRPTracker.closeTop();
874 BotRPTracker.closeBottom();
876 BotRPTracker.initLiveThru(RPTracker);
877 if (!BotRPTracker.getLiveThru().empty()) {
878 TopRPTracker.initLiveThru(BotRPTracker.getLiveThru());
879 DEBUG(dbgs() << "Live Thru: ";
880 dumpRegSetPressure(BotRPTracker.getLiveThru(), TRI));
883 // For each live out vreg reduce the pressure change associated with other
884 // uses of the same vreg below the live-out reaching def.
885 updatePressureDiffs(RPTracker.getPressure().LiveOutRegs);
887 // Account for liveness generated by the region boundary.
888 if (LiveRegionEnd != RegionEnd) {
889 SmallVector<unsigned, 8> LiveUses;
890 BotRPTracker.recede(&LiveUses);
891 updatePressureDiffs(LiveUses);
894 assert(BotRPTracker.getPos() == RegionEnd && "Can't find the region bottom");
896 // Cache the list of excess pressure sets in this region. This will also track
897 // the max pressure in the scheduled code for these sets.
898 RegionCriticalPSets.clear();
899 const std::vector<unsigned> &RegionPressure =
900 RPTracker.getPressure().MaxSetPressure;
901 for (unsigned i = 0, e = RegionPressure.size(); i < e; ++i) {
902 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i);
903 if (RegionPressure[i] > Limit) {
904 DEBUG(dbgs() << TRI->getRegPressureSetName(i)
905 << " Limit " << Limit
906 << " Actual " << RegionPressure[i] << "\n");
907 RegionCriticalPSets.push_back(PressureChange(i));
910 DEBUG(dbgs() << "Excess PSets: ";
911 for (unsigned i = 0, e = RegionCriticalPSets.size(); i != e; ++i)
912 dbgs() << TRI->getRegPressureSetName(
913 RegionCriticalPSets[i].getPSet()) << " ";
917 void ScheduleDAGMILive::
918 updateScheduledPressure(const SUnit *SU,
919 const std::vector<unsigned> &NewMaxPressure) {
920 const PressureDiff &PDiff = getPressureDiff(SU);
921 unsigned CritIdx = 0, CritEnd = RegionCriticalPSets.size();
922 for (PressureDiff::const_iterator I = PDiff.begin(), E = PDiff.end();
926 unsigned ID = I->getPSet();
927 while (CritIdx != CritEnd && RegionCriticalPSets[CritIdx].getPSet() < ID)
929 if (CritIdx != CritEnd && RegionCriticalPSets[CritIdx].getPSet() == ID) {
930 if ((int)NewMaxPressure[ID] > RegionCriticalPSets[CritIdx].getUnitInc()
931 && NewMaxPressure[ID] <= INT16_MAX)
932 RegionCriticalPSets[CritIdx].setUnitInc(NewMaxPressure[ID]);
934 unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID);
935 if (NewMaxPressure[ID] >= Limit - 2) {
936 DEBUG(dbgs() << " " << TRI->getRegPressureSetName(ID) << ": "
937 << NewMaxPressure[ID] << " > " << Limit << "(+ "
938 << BotRPTracker.getLiveThru()[ID] << " livethru)\n");
943 /// Update the PressureDiff array for liveness after scheduling this
945 void ScheduleDAGMILive::updatePressureDiffs(ArrayRef<unsigned> LiveUses) {
946 for (unsigned LUIdx = 0, LUEnd = LiveUses.size(); LUIdx != LUEnd; ++LUIdx) {
947 /// FIXME: Currently assuming single-use physregs.
948 unsigned Reg = LiveUses[LUIdx];
949 DEBUG(dbgs() << " LiveReg: " << PrintVRegOrUnit(Reg, TRI) << "\n");
950 if (!TRI->isVirtualRegister(Reg))
953 // This may be called before CurrentBottom has been initialized. However,
954 // BotRPTracker must have a valid position. We want the value live into the
955 // instruction or live out of the block, so ask for the previous
956 // instruction's live-out.
957 const LiveInterval &LI = LIS->getInterval(Reg);
959 MachineBasicBlock::const_iterator I =
960 nextIfDebug(BotRPTracker.getPos(), BB->end());
962 VNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
964 LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(I));
967 // RegisterPressureTracker guarantees that readsReg is true for LiveUses.
968 assert(VNI && "No live value at use.");
969 for (VReg2UseMap::iterator
970 UI = VRegUses.find(Reg); UI != VRegUses.end(); ++UI) {
972 DEBUG(dbgs() << " UpdateRegP: SU(" << SU->NodeNum << ") "
974 // If this use comes before the reaching def, it cannot be a last use, so
975 // descrease its pressure change.
976 if (!SU->isScheduled && SU != &ExitSU) {
978 = LI.Query(LIS->getInstructionIndex(SU->getInstr()));
979 if (LRQ.valueIn() == VNI)
980 getPressureDiff(SU).addPressureChange(Reg, true, &MRI);
986 /// schedule - Called back from MachineScheduler::runOnMachineFunction
987 /// after setting up the current scheduling region. [RegionBegin, RegionEnd)
988 /// only includes instructions that have DAG nodes, not scheduling boundaries.
990 /// This is a skeletal driver, with all the functionality pushed into helpers,
991 /// so that it can be easilly extended by experimental schedulers. Generally,
992 /// implementing MachineSchedStrategy should be sufficient to implement a new
993 /// scheduling algorithm. However, if a scheduler further subclasses
994 /// ScheduleDAGMILive then it will want to override this virtual method in order
995 /// to update any specialized state.
996 void ScheduleDAGMILive::schedule() {
997 buildDAGWithRegPressure();
999 Topo.InitDAGTopologicalSorting();
1003 SmallVector<SUnit*, 8> TopRoots, BotRoots;
1004 findRootsAndBiasEdges(TopRoots, BotRoots);
1006 // Initialize the strategy before modifying the DAG.
1007 // This may initialize a DFSResult to be used for queue priority.
1008 SchedImpl->initialize(this);
1010 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
1011 SUnits[su].dumpAll(this));
1012 if (ViewMISchedDAGs) viewGraph();
1014 // Initialize ready queues now that the DAG and priority data are finalized.
1015 initQueues(TopRoots, BotRoots);
1017 if (ShouldTrackPressure) {
1018 assert(TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker");
1019 TopRPTracker.setPos(CurrentTop);
1022 bool IsTopNode = false;
1023 while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) {
1024 assert(!SU->isScheduled && "Node already scheduled");
1025 if (!checkSchedLimit())
1028 scheduleMI(SU, IsTopNode);
1030 updateQueues(SU, IsTopNode);
1033 unsigned SubtreeID = DFSResult->getSubtreeID(SU);
1034 if (!ScheduledTrees.test(SubtreeID)) {
1035 ScheduledTrees.set(SubtreeID);
1036 DFSResult->scheduleTree(SubtreeID);
1037 SchedImpl->scheduleTree(SubtreeID);
1041 // Notify the scheduling strategy after updating the DAG.
1042 SchedImpl->schedNode(SU, IsTopNode);
1044 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
1049 unsigned BBNum = begin()->getParent()->getNumber();
1050 dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
1056 /// Build the DAG and setup three register pressure trackers.
1057 void ScheduleDAGMILive::buildDAGWithRegPressure() {
1058 if (!ShouldTrackPressure) {
1060 RegionCriticalPSets.clear();
1061 buildSchedGraph(AA);
1065 // Initialize the register pressure tracker used by buildSchedGraph.
1066 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd,
1067 /*TrackUntiedDefs=*/true);
1069 // Account for liveness generate by the region boundary.
1070 if (LiveRegionEnd != RegionEnd)
1073 // Build the DAG, and compute current register pressure.
1074 buildSchedGraph(AA, &RPTracker, &SUPressureDiffs);
1076 // Initialize top/bottom trackers after computing region pressure.
1080 void ScheduleDAGMILive::computeDFSResult() {
1082 DFSResult = new SchedDFSResult(/*BottomU*/true, MinSubtreeSize);
1084 ScheduledTrees.clear();
1085 DFSResult->resize(SUnits.size());
1086 DFSResult->compute(SUnits);
1087 ScheduledTrees.resize(DFSResult->getNumSubtrees());
1090 /// Compute the max cyclic critical path through the DAG. The scheduling DAG
1091 /// only provides the critical path for single block loops. To handle loops that
1092 /// span blocks, we could use the vreg path latencies provided by
1093 /// MachineTraceMetrics instead. However, MachineTraceMetrics is not currently
1094 /// available for use in the scheduler.
1096 /// The cyclic path estimation identifies a def-use pair that crosses the back
1097 /// edge and considers the depth and height of the nodes. For example, consider
1098 /// the following instruction sequence where each instruction has unit latency
1099 /// and defines an epomymous virtual register:
1101 /// a->b(a,c)->c(b)->d(c)->exit
1103 /// The cyclic critical path is a two cycles: b->c->b
1104 /// The acyclic critical path is four cycles: a->b->c->d->exit
1105 /// LiveOutHeight = height(c) = len(c->d->exit) = 2
1106 /// LiveOutDepth = depth(c) + 1 = len(a->b->c) + 1 = 3
1107 /// LiveInHeight = height(b) + 1 = len(b->c->d->exit) + 1 = 4
1108 /// LiveInDepth = depth(b) = len(a->b) = 1
1110 /// LiveOutDepth - LiveInDepth = 3 - 1 = 2
1111 /// LiveInHeight - LiveOutHeight = 4 - 2 = 2
1112 /// CyclicCriticalPath = min(2, 2) = 2
1114 /// This could be relevant to PostRA scheduling, but is currently implemented
1115 /// assuming LiveIntervals.
1116 unsigned ScheduleDAGMILive::computeCyclicCriticalPath() {
1117 // This only applies to single block loop.
1118 if (!BB->isSuccessor(BB))
1121 unsigned MaxCyclicLatency = 0;
1122 // Visit each live out vreg def to find def/use pairs that cross iterations.
1123 ArrayRef<unsigned> LiveOuts = RPTracker.getPressure().LiveOutRegs;
1124 for (ArrayRef<unsigned>::iterator RI = LiveOuts.begin(), RE = LiveOuts.end();
1127 if (!TRI->isVirtualRegister(Reg))
1129 const LiveInterval &LI = LIS->getInterval(Reg);
1130 const VNInfo *DefVNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
1134 MachineInstr *DefMI = LIS->getInstructionFromIndex(DefVNI->def);
1135 const SUnit *DefSU = getSUnit(DefMI);
1139 unsigned LiveOutHeight = DefSU->getHeight();
1140 unsigned LiveOutDepth = DefSU->getDepth() + DefSU->Latency;
1141 // Visit all local users of the vreg def.
1142 for (VReg2UseMap::iterator
1143 UI = VRegUses.find(Reg); UI != VRegUses.end(); ++UI) {
1144 if (UI->SU == &ExitSU)
1147 // Only consider uses of the phi.
1148 LiveQueryResult LRQ =
1149 LI.Query(LIS->getInstructionIndex(UI->SU->getInstr()));
1150 if (!LRQ.valueIn()->isPHIDef())
1153 // Assume that a path spanning two iterations is a cycle, which could
1154 // overestimate in strange cases. This allows cyclic latency to be
1155 // estimated as the minimum slack of the vreg's depth or height.
1156 unsigned CyclicLatency = 0;
1157 if (LiveOutDepth > UI->SU->getDepth())
1158 CyclicLatency = LiveOutDepth - UI->SU->getDepth();
1160 unsigned LiveInHeight = UI->SU->getHeight() + DefSU->Latency;
1161 if (LiveInHeight > LiveOutHeight) {
1162 if (LiveInHeight - LiveOutHeight < CyclicLatency)
1163 CyclicLatency = LiveInHeight - LiveOutHeight;
1168 DEBUG(dbgs() << "Cyclic Path: SU(" << DefSU->NodeNum << ") -> SU("
1169 << UI->SU->NodeNum << ") = " << CyclicLatency << "c\n");
1170 if (CyclicLatency > MaxCyclicLatency)
1171 MaxCyclicLatency = CyclicLatency;
1174 DEBUG(dbgs() << "Cyclic Critical Path: " << MaxCyclicLatency << "c\n");
1175 return MaxCyclicLatency;
1178 /// Move an instruction and update register pressure.
1179 void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) {
1180 // Move the instruction to its new location in the instruction stream.
1181 MachineInstr *MI = SU->getInstr();
1184 assert(SU->isTopReady() && "node still has unscheduled dependencies");
1185 if (&*CurrentTop == MI)
1186 CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);
1188 moveInstruction(MI, CurrentTop);
1189 TopRPTracker.setPos(MI);
1192 if (ShouldTrackPressure) {
1193 // Update top scheduled pressure.
1194 TopRPTracker.advance();
1195 assert(TopRPTracker.getPos() == CurrentTop && "out of sync");
1196 updateScheduledPressure(SU, TopRPTracker.getPressure().MaxSetPressure);
1200 assert(SU->isBottomReady() && "node still has unscheduled dependencies");
1201 MachineBasicBlock::iterator priorII =
1202 priorNonDebug(CurrentBottom, CurrentTop);
1203 if (&*priorII == MI)
1204 CurrentBottom = priorII;
1206 if (&*CurrentTop == MI) {
1207 CurrentTop = nextIfDebug(++CurrentTop, priorII);
1208 TopRPTracker.setPos(CurrentTop);
1210 moveInstruction(MI, CurrentBottom);
1213 if (ShouldTrackPressure) {
1214 // Update bottom scheduled pressure.
1215 SmallVector<unsigned, 8> LiveUses;
1216 BotRPTracker.recede(&LiveUses);
1217 assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
1218 updateScheduledPressure(SU, BotRPTracker.getPressure().MaxSetPressure);
1219 updatePressureDiffs(LiveUses);
1224 //===----------------------------------------------------------------------===//
1225 // LoadClusterMutation - DAG post-processing to cluster loads.
1226 //===----------------------------------------------------------------------===//
1229 /// \brief Post-process the DAG to create cluster edges between neighboring
1231 class LoadClusterMutation : public ScheduleDAGMutation {
1236 LoadInfo(SUnit *su, unsigned reg, unsigned ofs)
1237 : SU(su), BaseReg(reg), Offset(ofs) {}
1239 bool operator<(const LoadInfo &RHS) const {
1240 return std::tie(BaseReg, Offset) < std::tie(RHS.BaseReg, RHS.Offset);
1244 const TargetInstrInfo *TII;
1245 const TargetRegisterInfo *TRI;
1247 LoadClusterMutation(const TargetInstrInfo *tii,
1248 const TargetRegisterInfo *tri)
1249 : TII(tii), TRI(tri) {}
1251 void apply(ScheduleDAGMI *DAG) override;
1253 void clusterNeighboringLoads(ArrayRef<SUnit*> Loads, ScheduleDAGMI *DAG);
1257 void LoadClusterMutation::clusterNeighboringLoads(ArrayRef<SUnit*> Loads,
1258 ScheduleDAGMI *DAG) {
1259 SmallVector<LoadClusterMutation::LoadInfo,32> LoadRecords;
1260 for (unsigned Idx = 0, End = Loads.size(); Idx != End; ++Idx) {
1261 SUnit *SU = Loads[Idx];
1264 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
1265 LoadRecords.push_back(LoadInfo(SU, BaseReg, Offset));
1267 if (LoadRecords.size() < 2)
1269 std::sort(LoadRecords.begin(), LoadRecords.end());
1270 unsigned ClusterLength = 1;
1271 for (unsigned Idx = 0, End = LoadRecords.size(); Idx < (End - 1); ++Idx) {
1272 if (LoadRecords[Idx].BaseReg != LoadRecords[Idx+1].BaseReg) {
1277 SUnit *SUa = LoadRecords[Idx].SU;
1278 SUnit *SUb = LoadRecords[Idx+1].SU;
1279 if (TII->shouldClusterLoads(SUa->getInstr(), SUb->getInstr(), ClusterLength)
1280 && DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
1282 DEBUG(dbgs() << "Cluster loads SU(" << SUa->NodeNum << ") - SU("
1283 << SUb->NodeNum << ")\n");
1284 // Copy successor edges from SUa to SUb. Interleaving computation
1285 // dependent on SUa can prevent load combining due to register reuse.
1286 // Predecessor edges do not need to be copied from SUb to SUa since nearby
1287 // loads should have effectively the same inputs.
1288 for (SUnit::const_succ_iterator
1289 SI = SUa->Succs.begin(), SE = SUa->Succs.end(); SI != SE; ++SI) {
1290 if (SI->getSUnit() == SUb)
1292 DEBUG(dbgs() << " Copy Succ SU(" << SI->getSUnit()->NodeNum << ")\n");
1293 DAG->addEdge(SI->getSUnit(), SDep(SUb, SDep::Artificial));
1302 /// \brief Callback from DAG postProcessing to create cluster edges for loads.
1303 void LoadClusterMutation::apply(ScheduleDAGMI *DAG) {
1304 // Map DAG NodeNum to store chain ID.
1305 DenseMap<unsigned, unsigned> StoreChainIDs;
1306 // Map each store chain to a set of dependent loads.
1307 SmallVector<SmallVector<SUnit*,4>, 32> StoreChainDependents;
1308 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
1309 SUnit *SU = &DAG->SUnits[Idx];
1310 if (!SU->getInstr()->mayLoad())
1312 unsigned ChainPredID = DAG->SUnits.size();
1313 for (SUnit::const_pred_iterator
1314 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) {
1316 ChainPredID = PI->getSUnit()->NodeNum;
1320 // Check if this chain-like pred has been seen
1321 // before. ChainPredID==MaxNodeID for loads at the top of the schedule.
1322 unsigned NumChains = StoreChainDependents.size();
1323 std::pair<DenseMap<unsigned, unsigned>::iterator, bool> Result =
1324 StoreChainIDs.insert(std::make_pair(ChainPredID, NumChains));
1326 StoreChainDependents.resize(NumChains + 1);
1327 StoreChainDependents[Result.first->second].push_back(SU);
1329 // Iterate over the store chains.
1330 for (unsigned Idx = 0, End = StoreChainDependents.size(); Idx != End; ++Idx)
1331 clusterNeighboringLoads(StoreChainDependents[Idx], DAG);
1334 //===----------------------------------------------------------------------===//
1335 // MacroFusion - DAG post-processing to encourage fusion of macro ops.
1336 //===----------------------------------------------------------------------===//
1339 /// \brief Post-process the DAG to create cluster edges between instructions
1340 /// that may be fused by the processor into a single operation.
1341 class MacroFusion : public ScheduleDAGMutation {
1342 const TargetInstrInfo *TII;
1344 MacroFusion(const TargetInstrInfo *tii): TII(tii) {}
1346 void apply(ScheduleDAGMI *DAG) override;
1350 /// \brief Callback from DAG postProcessing to create cluster edges to encourage
1351 /// fused operations.
1352 void MacroFusion::apply(ScheduleDAGMI *DAG) {
1353 // For now, assume targets can only fuse with the branch.
1354 MachineInstr *Branch = DAG->ExitSU.getInstr();
1358 for (unsigned Idx = DAG->SUnits.size(); Idx > 0;) {
1359 SUnit *SU = &DAG->SUnits[--Idx];
1360 if (!TII->shouldScheduleAdjacent(SU->getInstr(), Branch))
1363 // Create a single weak edge from SU to ExitSU. The only effect is to cause
1364 // bottom-up scheduling to heavily prioritize the clustered SU. There is no
1365 // need to copy predecessor edges from ExitSU to SU, since top-down
1366 // scheduling cannot prioritize ExitSU anyway. To defer top-down scheduling
1367 // of SU, we could create an artificial edge from the deepest root, but it
1368 // hasn't been needed yet.
1369 bool Success = DAG->addEdge(&DAG->ExitSU, SDep(SU, SDep::Cluster));
1371 assert(Success && "No DAG nodes should be reachable from ExitSU");
1373 DEBUG(dbgs() << "Macro Fuse SU(" << SU->NodeNum << ")\n");
1378 //===----------------------------------------------------------------------===//
1379 // CopyConstrain - DAG post-processing to encourage copy elimination.
1380 //===----------------------------------------------------------------------===//
1383 /// \brief Post-process the DAG to create weak edges from all uses of a copy to
1384 /// the one use that defines the copy's source vreg, most likely an induction
1385 /// variable increment.
1386 class CopyConstrain : public ScheduleDAGMutation {
1388 SlotIndex RegionBeginIdx;
1389 // RegionEndIdx is the slot index of the last non-debug instruction in the
1390 // scheduling region. So we may have RegionBeginIdx == RegionEndIdx.
1391 SlotIndex RegionEndIdx;
1393 CopyConstrain(const TargetInstrInfo *, const TargetRegisterInfo *) {}
1395 void apply(ScheduleDAGMI *DAG) override;
1398 void constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG);
1402 /// constrainLocalCopy handles two possibilities:
1407 /// I3: dst = src (copy)
1408 /// (create pred->succ edges I0->I1, I2->I1)
1411 /// I0: dst = src (copy)
1415 /// (create pred->succ edges I1->I2, I3->I2)
1417 /// Although the MachineScheduler is currently constrained to single blocks,
1418 /// this algorithm should handle extended blocks. An EBB is a set of
1419 /// contiguously numbered blocks such that the previous block in the EBB is
1420 /// always the single predecessor.
1421 void CopyConstrain::constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG) {
1422 LiveIntervals *LIS = DAG->getLIS();
1423 MachineInstr *Copy = CopySU->getInstr();
1425 // Check for pure vreg copies.
1426 unsigned SrcReg = Copy->getOperand(1).getReg();
1427 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
1430 unsigned DstReg = Copy->getOperand(0).getReg();
1431 if (!TargetRegisterInfo::isVirtualRegister(DstReg))
1434 // Check if either the dest or source is local. If it's live across a back
1435 // edge, it's not local. Note that if both vregs are live across the back
1436 // edge, we cannot successfully contrain the copy without cyclic scheduling.
1437 // If both the copy's source and dest are local live intervals, then we
1438 // should treat the dest as the global for the purpose of adding
1439 // constraints. This adds edges from source's other uses to the copy.
1440 unsigned LocalReg = SrcReg;
1441 unsigned GlobalReg = DstReg;
1442 LiveInterval *LocalLI = &LIS->getInterval(LocalReg);
1443 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx)) {
1446 LocalLI = &LIS->getInterval(LocalReg);
1447 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx))
1450 LiveInterval *GlobalLI = &LIS->getInterval(GlobalReg);
1452 // Find the global segment after the start of the local LI.
1453 LiveInterval::iterator GlobalSegment = GlobalLI->find(LocalLI->beginIndex());
1454 // If GlobalLI does not overlap LocalLI->start, then a copy directly feeds a
1455 // local live range. We could create edges from other global uses to the local
1456 // start, but the coalescer should have already eliminated these cases, so
1457 // don't bother dealing with it.
1458 if (GlobalSegment == GlobalLI->end())
1461 // If GlobalSegment is killed at the LocalLI->start, the call to find()
1462 // returned the next global segment. But if GlobalSegment overlaps with
1463 // LocalLI->start, then advance to the next segement. If a hole in GlobalLI
1464 // exists in LocalLI's vicinity, GlobalSegment will be the end of the hole.
1465 if (GlobalSegment->contains(LocalLI->beginIndex()))
1468 if (GlobalSegment == GlobalLI->end())
1471 // Check if GlobalLI contains a hole in the vicinity of LocalLI.
1472 if (GlobalSegment != GlobalLI->begin()) {
1473 // Two address defs have no hole.
1474 if (SlotIndex::isSameInstr(std::prev(GlobalSegment)->end,
1475 GlobalSegment->start)) {
1478 // If the prior global segment may be defined by the same two-address
1479 // instruction that also defines LocalLI, then can't make a hole here.
1480 if (SlotIndex::isSameInstr(std::prev(GlobalSegment)->start,
1481 LocalLI->beginIndex())) {
1484 // If GlobalLI has a prior segment, it must be live into the EBB. Otherwise
1485 // it would be a disconnected component in the live range.
1486 assert(std::prev(GlobalSegment)->start < LocalLI->beginIndex() &&
1487 "Disconnected LRG within the scheduling region.");
1489 MachineInstr *GlobalDef = LIS->getInstructionFromIndex(GlobalSegment->start);
1493 SUnit *GlobalSU = DAG->getSUnit(GlobalDef);
1497 // GlobalDef is the bottom of the GlobalLI hole. Open the hole by
1498 // constraining the uses of the last local def to precede GlobalDef.
1499 SmallVector<SUnit*,8> LocalUses;
1500 const VNInfo *LastLocalVN = LocalLI->getVNInfoBefore(LocalLI->endIndex());
1501 MachineInstr *LastLocalDef = LIS->getInstructionFromIndex(LastLocalVN->def);
1502 SUnit *LastLocalSU = DAG->getSUnit(LastLocalDef);
1503 for (SUnit::const_succ_iterator
1504 I = LastLocalSU->Succs.begin(), E = LastLocalSU->Succs.end();
1506 if (I->getKind() != SDep::Data || I->getReg() != LocalReg)
1508 if (I->getSUnit() == GlobalSU)
1510 if (!DAG->canAddEdge(GlobalSU, I->getSUnit()))
1512 LocalUses.push_back(I->getSUnit());
1514 // Open the top of the GlobalLI hole by constraining any earlier global uses
1515 // to precede the start of LocalLI.
1516 SmallVector<SUnit*,8> GlobalUses;
1517 MachineInstr *FirstLocalDef =
1518 LIS->getInstructionFromIndex(LocalLI->beginIndex());
1519 SUnit *FirstLocalSU = DAG->getSUnit(FirstLocalDef);
1520 for (SUnit::const_pred_iterator
1521 I = GlobalSU->Preds.begin(), E = GlobalSU->Preds.end(); I != E; ++I) {
1522 if (I->getKind() != SDep::Anti || I->getReg() != GlobalReg)
1524 if (I->getSUnit() == FirstLocalSU)
1526 if (!DAG->canAddEdge(FirstLocalSU, I->getSUnit()))
1528 GlobalUses.push_back(I->getSUnit());
1530 DEBUG(dbgs() << "Constraining copy SU(" << CopySU->NodeNum << ")\n");
1531 // Add the weak edges.
1532 for (SmallVectorImpl<SUnit*>::const_iterator
1533 I = LocalUses.begin(), E = LocalUses.end(); I != E; ++I) {
1534 DEBUG(dbgs() << " Local use SU(" << (*I)->NodeNum << ") -> SU("
1535 << GlobalSU->NodeNum << ")\n");
1536 DAG->addEdge(GlobalSU, SDep(*I, SDep::Weak));
1538 for (SmallVectorImpl<SUnit*>::const_iterator
1539 I = GlobalUses.begin(), E = GlobalUses.end(); I != E; ++I) {
1540 DEBUG(dbgs() << " Global use SU(" << (*I)->NodeNum << ") -> SU("
1541 << FirstLocalSU->NodeNum << ")\n");
1542 DAG->addEdge(FirstLocalSU, SDep(*I, SDep::Weak));
1546 /// \brief Callback from DAG postProcessing to create weak edges to encourage
1547 /// copy elimination.
1548 void CopyConstrain::apply(ScheduleDAGMI *DAG) {
1549 assert(DAG->hasVRegLiveness() && "Expect VRegs with LiveIntervals");
1551 MachineBasicBlock::iterator FirstPos = nextIfDebug(DAG->begin(), DAG->end());
1552 if (FirstPos == DAG->end())
1554 RegionBeginIdx = DAG->getLIS()->getInstructionIndex(&*FirstPos);
1555 RegionEndIdx = DAG->getLIS()->getInstructionIndex(
1556 &*priorNonDebug(DAG->end(), DAG->begin()));
1558 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
1559 SUnit *SU = &DAG->SUnits[Idx];
1560 if (!SU->getInstr()->isCopy())
1563 constrainLocalCopy(SU, static_cast<ScheduleDAGMILive*>(DAG));
1567 //===----------------------------------------------------------------------===//
1568 // MachineSchedStrategy helpers used by GenericScheduler, GenericPostScheduler
1569 // and possibly other custom schedulers.
1570 //===----------------------------------------------------------------------===//
1572 static const unsigned InvalidCycle = ~0U;
1574 SchedBoundary::~SchedBoundary() { delete HazardRec; }
1576 void SchedBoundary::reset() {
1577 // A new HazardRec is created for each DAG and owned by SchedBoundary.
1578 // Destroying and reconstructing it is very expensive though. So keep
1579 // invalid, placeholder HazardRecs.
1580 if (HazardRec && HazardRec->isEnabled()) {
1582 HazardRec = nullptr;
1586 CheckPending = false;
1590 MinReadyCycle = UINT_MAX;
1591 ExpectedLatency = 0;
1592 DependentLatency = 0;
1594 MaxExecutedResCount = 0;
1596 IsResourceLimited = false;
1597 ReservedCycles.clear();
1599 // Track the maximum number of stall cycles that could arise either from the
1600 // latency of a DAG edge or the number of cycles that a processor resource is
1601 // reserved (SchedBoundary::ReservedCycles).
1602 MaxObservedStall = 0;
1604 // Reserve a zero-count for invalid CritResIdx.
1605 ExecutedResCounts.resize(1);
1606 assert(!ExecutedResCounts[0] && "nonzero count for bad resource");
1609 void SchedRemainder::
1610 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) {
1612 if (!SchedModel->hasInstrSchedModel())
1614 RemainingCounts.resize(SchedModel->getNumProcResourceKinds());
1615 for (std::vector<SUnit>::iterator
1616 I = DAG->SUnits.begin(), E = DAG->SUnits.end(); I != E; ++I) {
1617 const MCSchedClassDesc *SC = DAG->getSchedClass(&*I);
1618 RemIssueCount += SchedModel->getNumMicroOps(I->getInstr(), SC)
1619 * SchedModel->getMicroOpFactor();
1620 for (TargetSchedModel::ProcResIter
1621 PI = SchedModel->getWriteProcResBegin(SC),
1622 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1623 unsigned PIdx = PI->ProcResourceIdx;
1624 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1625 RemainingCounts[PIdx] += (Factor * PI->Cycles);
1630 void SchedBoundary::
1631 init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem) {
1634 SchedModel = smodel;
1636 if (SchedModel->hasInstrSchedModel()) {
1637 ExecutedResCounts.resize(SchedModel->getNumProcResourceKinds());
1638 ReservedCycles.resize(SchedModel->getNumProcResourceKinds(), InvalidCycle);
1642 /// Compute the stall cycles based on this SUnit's ready time. Heuristics treat
1643 /// these "soft stalls" differently than the hard stall cycles based on CPU
1644 /// resources and computed by checkHazard(). A fully in-order model
1645 /// (MicroOpBufferSize==0) will not make use of this since instructions are not
1646 /// available for scheduling until they are ready. However, a weaker in-order
1647 /// model may use this for heuristics. For example, if a processor has in-order
1648 /// behavior when reading certain resources, this may come into play.
1649 unsigned SchedBoundary::getLatencyStallCycles(SUnit *SU) {
1650 if (!SU->isUnbuffered)
1653 unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle);
1654 if (ReadyCycle > CurrCycle)
1655 return ReadyCycle - CurrCycle;
1659 /// Compute the next cycle at which the given processor resource can be
1661 unsigned SchedBoundary::
1662 getNextResourceCycle(unsigned PIdx, unsigned Cycles) {
1663 unsigned NextUnreserved = ReservedCycles[PIdx];
1664 // If this resource has never been used, always return cycle zero.
1665 if (NextUnreserved == InvalidCycle)
1667 // For bottom-up scheduling add the cycles needed for the current operation.
1669 NextUnreserved += Cycles;
1670 return NextUnreserved;
1673 /// Does this SU have a hazard within the current instruction group.
1675 /// The scheduler supports two modes of hazard recognition. The first is the
1676 /// ScheduleHazardRecognizer API. It is a fully general hazard recognizer that
1677 /// supports highly complicated in-order reservation tables
1678 /// (ScoreboardHazardRecognizer) and arbitraty target-specific logic.
1680 /// The second is a streamlined mechanism that checks for hazards based on
1681 /// simple counters that the scheduler itself maintains. It explicitly checks
1682 /// for instruction dispatch limitations, including the number of micro-ops that
1683 /// can dispatch per cycle.
1685 /// TODO: Also check whether the SU must start a new group.
1686 bool SchedBoundary::checkHazard(SUnit *SU) {
1687 if (HazardRec->isEnabled()
1688 && HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard) {
1691 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
1692 if ((CurrMOps > 0) && (CurrMOps + uops > SchedModel->getIssueWidth())) {
1693 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") uops="
1694 << SchedModel->getNumMicroOps(SU->getInstr()) << '\n');
1697 if (SchedModel->hasInstrSchedModel() && SU->hasReservedResource) {
1698 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
1699 for (TargetSchedModel::ProcResIter
1700 PI = SchedModel->getWriteProcResBegin(SC),
1701 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1702 unsigned NRCycle = getNextResourceCycle(PI->ProcResourceIdx, PI->Cycles);
1703 if (NRCycle > CurrCycle) {
1705 MaxObservedStall = std::max(PI->Cycles, MaxObservedStall);
1707 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") "
1708 << SchedModel->getResourceName(PI->ProcResourceIdx)
1709 << "=" << NRCycle << "c\n");
1717 // Find the unscheduled node in ReadySUs with the highest latency.
1718 unsigned SchedBoundary::
1719 findMaxLatency(ArrayRef<SUnit*> ReadySUs) {
1720 SUnit *LateSU = nullptr;
1721 unsigned RemLatency = 0;
1722 for (ArrayRef<SUnit*>::iterator I = ReadySUs.begin(), E = ReadySUs.end();
1724 unsigned L = getUnscheduledLatency(*I);
1725 if (L > RemLatency) {
1731 DEBUG(dbgs() << Available.getName() << " RemLatency SU("
1732 << LateSU->NodeNum << ") " << RemLatency << "c\n");
1737 // Count resources in this zone and the remaining unscheduled
1738 // instruction. Return the max count, scaled. Set OtherCritIdx to the critical
1739 // resource index, or zero if the zone is issue limited.
1740 unsigned SchedBoundary::
1741 getOtherResourceCount(unsigned &OtherCritIdx) {
1743 if (!SchedModel->hasInstrSchedModel())
1746 unsigned OtherCritCount = Rem->RemIssueCount
1747 + (RetiredMOps * SchedModel->getMicroOpFactor());
1748 DEBUG(dbgs() << " " << Available.getName() << " + Remain MOps: "
1749 << OtherCritCount / SchedModel->getMicroOpFactor() << '\n');
1750 for (unsigned PIdx = 1, PEnd = SchedModel->getNumProcResourceKinds();
1751 PIdx != PEnd; ++PIdx) {
1752 unsigned OtherCount = getResourceCount(PIdx) + Rem->RemainingCounts[PIdx];
1753 if (OtherCount > OtherCritCount) {
1754 OtherCritCount = OtherCount;
1755 OtherCritIdx = PIdx;
1759 DEBUG(dbgs() << " " << Available.getName() << " + Remain CritRes: "
1760 << OtherCritCount / SchedModel->getResourceFactor(OtherCritIdx)
1761 << " " << SchedModel->getResourceName(OtherCritIdx) << "\n");
1763 return OtherCritCount;
1766 void SchedBoundary::releaseNode(SUnit *SU, unsigned ReadyCycle) {
1767 assert(SU->getInstr() && "Scheduled SUnit must have instr");
1770 // ReadyCycle was been bumped up to the CurrCycle when this node was
1771 // scheduled, but CurrCycle may have been eagerly advanced immediately after
1772 // scheduling, so may now be greater than ReadyCycle.
1773 if (ReadyCycle > CurrCycle)
1774 MaxObservedStall = std::max(ReadyCycle - CurrCycle, MaxObservedStall);
1777 if (ReadyCycle < MinReadyCycle)
1778 MinReadyCycle = ReadyCycle;
1780 // Check for interlocks first. For the purpose of other heuristics, an
1781 // instruction that cannot issue appears as if it's not in the ReadyQueue.
1782 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
1783 if ((!IsBuffered && ReadyCycle > CurrCycle) || checkHazard(SU))
1788 // Record this node as an immediate dependent of the scheduled node.
1792 void SchedBoundary::releaseTopNode(SUnit *SU) {
1793 if (SU->isScheduled)
1796 releaseNode(SU, SU->TopReadyCycle);
1799 void SchedBoundary::releaseBottomNode(SUnit *SU) {
1800 if (SU->isScheduled)
1803 releaseNode(SU, SU->BotReadyCycle);
1806 /// Move the boundary of scheduled code by one cycle.
1807 void SchedBoundary::bumpCycle(unsigned NextCycle) {
1808 if (SchedModel->getMicroOpBufferSize() == 0) {
1809 assert(MinReadyCycle < UINT_MAX && "MinReadyCycle uninitialized");
1810 if (MinReadyCycle > NextCycle)
1811 NextCycle = MinReadyCycle;
1813 // Update the current micro-ops, which will issue in the next cycle.
1814 unsigned DecMOps = SchedModel->getIssueWidth() * (NextCycle - CurrCycle);
1815 CurrMOps = (CurrMOps <= DecMOps) ? 0 : CurrMOps - DecMOps;
1817 // Decrement DependentLatency based on the next cycle.
1818 if ((NextCycle - CurrCycle) > DependentLatency)
1819 DependentLatency = 0;
1821 DependentLatency -= (NextCycle - CurrCycle);
1823 if (!HazardRec->isEnabled()) {
1824 // Bypass HazardRec virtual calls.
1825 CurrCycle = NextCycle;
1828 // Bypass getHazardType calls in case of long latency.
1829 for (; CurrCycle != NextCycle; ++CurrCycle) {
1831 HazardRec->AdvanceCycle();
1833 HazardRec->RecedeCycle();
1836 CheckPending = true;
1837 unsigned LFactor = SchedModel->getLatencyFactor();
1839 (int)(getCriticalCount() - (getScheduledLatency() * LFactor))
1842 DEBUG(dbgs() << "Cycle: " << CurrCycle << ' ' << Available.getName() << '\n');
1845 void SchedBoundary::incExecutedResources(unsigned PIdx, unsigned Count) {
1846 ExecutedResCounts[PIdx] += Count;
1847 if (ExecutedResCounts[PIdx] > MaxExecutedResCount)
1848 MaxExecutedResCount = ExecutedResCounts[PIdx];
1851 /// Add the given processor resource to this scheduled zone.
1853 /// \param Cycles indicates the number of consecutive (non-pipelined) cycles
1854 /// during which this resource is consumed.
1856 /// \return the next cycle at which the instruction may execute without
1857 /// oversubscribing resources.
1858 unsigned SchedBoundary::
1859 countResource(unsigned PIdx, unsigned Cycles, unsigned NextCycle) {
1860 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1861 unsigned Count = Factor * Cycles;
1862 DEBUG(dbgs() << " " << SchedModel->getResourceName(PIdx)
1863 << " +" << Cycles << "x" << Factor << "u\n");
1865 // Update Executed resources counts.
1866 incExecutedResources(PIdx, Count);
1867 assert(Rem->RemainingCounts[PIdx] >= Count && "resource double counted");
1868 Rem->RemainingCounts[PIdx] -= Count;
1870 // Check if this resource exceeds the current critical resource. If so, it
1871 // becomes the critical resource.
1872 if (ZoneCritResIdx != PIdx && (getResourceCount(PIdx) > getCriticalCount())) {
1873 ZoneCritResIdx = PIdx;
1874 DEBUG(dbgs() << " *** Critical resource "
1875 << SchedModel->getResourceName(PIdx) << ": "
1876 << getResourceCount(PIdx) / SchedModel->getLatencyFactor() << "c\n");
1878 // For reserved resources, record the highest cycle using the resource.
1879 unsigned NextAvailable = getNextResourceCycle(PIdx, Cycles);
1880 if (NextAvailable > CurrCycle) {
1881 DEBUG(dbgs() << " Resource conflict: "
1882 << SchedModel->getProcResource(PIdx)->Name << " reserved until @"
1883 << NextAvailable << "\n");
1885 return NextAvailable;
1888 /// Move the boundary of scheduled code by one SUnit.
1889 void SchedBoundary::bumpNode(SUnit *SU) {
1890 // Update the reservation table.
1891 if (HazardRec->isEnabled()) {
1892 if (!isTop() && SU->isCall) {
1893 // Calls are scheduled with their preceding instructions. For bottom-up
1894 // scheduling, clear the pipeline state before emitting.
1897 HazardRec->EmitInstruction(SU);
1899 // checkHazard should prevent scheduling multiple instructions per cycle that
1900 // exceed the issue width.
1901 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
1902 unsigned IncMOps = SchedModel->getNumMicroOps(SU->getInstr());
1904 (CurrMOps == 0 || (CurrMOps + IncMOps) <= SchedModel->getIssueWidth()) &&
1905 "Cannot schedule this instruction's MicroOps in the current cycle.");
1907 unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle);
1908 DEBUG(dbgs() << " Ready @" << ReadyCycle << "c\n");
1910 unsigned NextCycle = CurrCycle;
1911 switch (SchedModel->getMicroOpBufferSize()) {
1913 assert(ReadyCycle <= CurrCycle && "Broken PendingQueue");
1916 if (ReadyCycle > NextCycle) {
1917 NextCycle = ReadyCycle;
1918 DEBUG(dbgs() << " *** Stall until: " << ReadyCycle << "\n");
1922 // We don't currently model the OOO reorder buffer, so consider all
1923 // scheduled MOps to be "retired". We do loosely model in-order resource
1924 // latency. If this instruction uses an in-order resource, account for any
1925 // likely stall cycles.
1926 if (SU->isUnbuffered && ReadyCycle > NextCycle)
1927 NextCycle = ReadyCycle;
1930 RetiredMOps += IncMOps;
1932 // Update resource counts and critical resource.
1933 if (SchedModel->hasInstrSchedModel()) {
1934 unsigned DecRemIssue = IncMOps * SchedModel->getMicroOpFactor();
1935 assert(Rem->RemIssueCount >= DecRemIssue && "MOps double counted");
1936 Rem->RemIssueCount -= DecRemIssue;
1937 if (ZoneCritResIdx) {
1938 // Scale scheduled micro-ops for comparing with the critical resource.
1939 unsigned ScaledMOps =
1940 RetiredMOps * SchedModel->getMicroOpFactor();
1942 // If scaled micro-ops are now more than the previous critical resource by
1943 // a full cycle, then micro-ops issue becomes critical.
1944 if ((int)(ScaledMOps - getResourceCount(ZoneCritResIdx))
1945 >= (int)SchedModel->getLatencyFactor()) {
1947 DEBUG(dbgs() << " *** Critical resource NumMicroOps: "
1948 << ScaledMOps / SchedModel->getLatencyFactor() << "c\n");
1951 for (TargetSchedModel::ProcResIter
1952 PI = SchedModel->getWriteProcResBegin(SC),
1953 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1955 countResource(PI->ProcResourceIdx, PI->Cycles, NextCycle);
1956 if (RCycle > NextCycle)
1959 if (SU->hasReservedResource) {
1960 // For reserved resources, record the highest cycle using the resource.
1961 // For top-down scheduling, this is the cycle in which we schedule this
1962 // instruction plus the number of cycles the operations reserves the
1963 // resource. For bottom-up is it simply the instruction's cycle.
1964 for (TargetSchedModel::ProcResIter
1965 PI = SchedModel->getWriteProcResBegin(SC),
1966 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1967 unsigned PIdx = PI->ProcResourceIdx;
1968 if (SchedModel->getProcResource(PIdx)->BufferSize == 0) {
1970 ReservedCycles[PIdx] =
1971 std::max(getNextResourceCycle(PIdx, 0), NextCycle + PI->Cycles);
1974 ReservedCycles[PIdx] = NextCycle;
1979 // Update ExpectedLatency and DependentLatency.
1980 unsigned &TopLatency = isTop() ? ExpectedLatency : DependentLatency;
1981 unsigned &BotLatency = isTop() ? DependentLatency : ExpectedLatency;
1982 if (SU->getDepth() > TopLatency) {
1983 TopLatency = SU->getDepth();
1984 DEBUG(dbgs() << " " << Available.getName()
1985 << " TopLatency SU(" << SU->NodeNum << ") " << TopLatency << "c\n");
1987 if (SU->getHeight() > BotLatency) {
1988 BotLatency = SU->getHeight();
1989 DEBUG(dbgs() << " " << Available.getName()
1990 << " BotLatency SU(" << SU->NodeNum << ") " << BotLatency << "c\n");
1992 // If we stall for any reason, bump the cycle.
1993 if (NextCycle > CurrCycle) {
1994 bumpCycle(NextCycle);
1997 // After updating ZoneCritResIdx and ExpectedLatency, check if we're
1998 // resource limited. If a stall occurred, bumpCycle does this.
1999 unsigned LFactor = SchedModel->getLatencyFactor();
2001 (int)(getCriticalCount() - (getScheduledLatency() * LFactor))
2004 // Update CurrMOps after calling bumpCycle to handle stalls, since bumpCycle
2005 // resets CurrMOps. Loop to handle instructions with more MOps than issue in
2006 // one cycle. Since we commonly reach the max MOps here, opportunistically
2007 // bump the cycle to avoid uselessly checking everything in the readyQ.
2008 CurrMOps += IncMOps;
2009 while (CurrMOps >= SchedModel->getIssueWidth()) {
2010 DEBUG(dbgs() << " *** Max MOps " << CurrMOps
2011 << " at cycle " << CurrCycle << '\n');
2012 bumpCycle(++NextCycle);
2014 DEBUG(dumpScheduledState());
2017 /// Release pending ready nodes in to the available queue. This makes them
2018 /// visible to heuristics.
2019 void SchedBoundary::releasePending() {
2020 // If the available queue is empty, it is safe to reset MinReadyCycle.
2021 if (Available.empty())
2022 MinReadyCycle = UINT_MAX;
2024 // Check to see if any of the pending instructions are ready to issue. If
2025 // so, add them to the available queue.
2026 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
2027 for (unsigned i = 0, e = Pending.size(); i != e; ++i) {
2028 SUnit *SU = *(Pending.begin()+i);
2029 unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle;
2031 if (ReadyCycle < MinReadyCycle)
2032 MinReadyCycle = ReadyCycle;
2034 if (!IsBuffered && ReadyCycle > CurrCycle)
2037 if (checkHazard(SU))
2041 Pending.remove(Pending.begin()+i);
2044 DEBUG(if (!Pending.empty()) Pending.dump());
2045 CheckPending = false;
2048 /// Remove SU from the ready set for this boundary.
2049 void SchedBoundary::removeReady(SUnit *SU) {
2050 if (Available.isInQueue(SU))
2051 Available.remove(Available.find(SU));
2053 assert(Pending.isInQueue(SU) && "bad ready count");
2054 Pending.remove(Pending.find(SU));
2058 /// If this queue only has one ready candidate, return it. As a side effect,
2059 /// defer any nodes that now hit a hazard, and advance the cycle until at least
2060 /// one node is ready. If multiple instructions are ready, return NULL.
2061 SUnit *SchedBoundary::pickOnlyChoice() {
2066 // Defer any ready instrs that now have a hazard.
2067 for (ReadyQueue::iterator I = Available.begin(); I != Available.end();) {
2068 if (checkHazard(*I)) {
2070 I = Available.remove(I);
2076 for (unsigned i = 0; Available.empty(); ++i) {
2077 // FIXME: Re-enable assert once PR20057 is resolved.
2078 // assert(i <= (HazardRec->getMaxLookAhead() + MaxObservedStall) &&
2079 // "permanent hazard");
2081 bumpCycle(CurrCycle + 1);
2084 if (Available.size() == 1)
2085 return *Available.begin();
2090 // This is useful information to dump after bumpNode.
2091 // Note that the Queue contents are more useful before pickNodeFromQueue.
2092 void SchedBoundary::dumpScheduledState() {
2095 if (ZoneCritResIdx) {
2096 ResFactor = SchedModel->getResourceFactor(ZoneCritResIdx);
2097 ResCount = getResourceCount(ZoneCritResIdx);
2100 ResFactor = SchedModel->getMicroOpFactor();
2101 ResCount = RetiredMOps * SchedModel->getMicroOpFactor();
2103 unsigned LFactor = SchedModel->getLatencyFactor();
2104 dbgs() << Available.getName() << " @" << CurrCycle << "c\n"
2105 << " Retired: " << RetiredMOps;
2106 dbgs() << "\n Executed: " << getExecutedCount() / LFactor << "c";
2107 dbgs() << "\n Critical: " << ResCount / LFactor << "c, "
2108 << ResCount / ResFactor << " "
2109 << SchedModel->getResourceName(ZoneCritResIdx)
2110 << "\n ExpectedLatency: " << ExpectedLatency << "c\n"
2111 << (IsResourceLimited ? " - Resource" : " - Latency")
2116 //===----------------------------------------------------------------------===//
2117 // GenericScheduler - Generic implementation of MachineSchedStrategy.
2118 //===----------------------------------------------------------------------===//
2120 void GenericSchedulerBase::SchedCandidate::
2121 initResourceDelta(const ScheduleDAGMI *DAG,
2122 const TargetSchedModel *SchedModel) {
2123 if (!Policy.ReduceResIdx && !Policy.DemandResIdx)
2126 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
2127 for (TargetSchedModel::ProcResIter
2128 PI = SchedModel->getWriteProcResBegin(SC),
2129 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
2130 if (PI->ProcResourceIdx == Policy.ReduceResIdx)
2131 ResDelta.CritResources += PI->Cycles;
2132 if (PI->ProcResourceIdx == Policy.DemandResIdx)
2133 ResDelta.DemandedResources += PI->Cycles;
2137 /// Set the CandPolicy given a scheduling zone given the current resources and
2138 /// latencies inside and outside the zone.
2139 void GenericSchedulerBase::setPolicy(CandPolicy &Policy,
2141 SchedBoundary &CurrZone,
2142 SchedBoundary *OtherZone) {
2143 // Apply preemptive heuristics based on the the total latency and resources
2144 // inside and outside this zone. Potential stalls should be considered before
2145 // following this policy.
2147 // Compute remaining latency. We need this both to determine whether the
2148 // overall schedule has become latency-limited and whether the instructions
2149 // outside this zone are resource or latency limited.
2151 // The "dependent" latency is updated incrementally during scheduling as the
2152 // max height/depth of scheduled nodes minus the cycles since it was
2154 // DLat = max (N.depth - (CurrCycle - N.ReadyCycle) for N in Zone
2156 // The "independent" latency is the max ready queue depth:
2157 // ILat = max N.depth for N in Available|Pending
2159 // RemainingLatency is the greater of independent and dependent latency.
2160 unsigned RemLatency = CurrZone.getDependentLatency();
2161 RemLatency = std::max(RemLatency,
2162 CurrZone.findMaxLatency(CurrZone.Available.elements()));
2163 RemLatency = std::max(RemLatency,
2164 CurrZone.findMaxLatency(CurrZone.Pending.elements()));
2166 // Compute the critical resource outside the zone.
2167 unsigned OtherCritIdx = 0;
2168 unsigned OtherCount =
2169 OtherZone ? OtherZone->getOtherResourceCount(OtherCritIdx) : 0;
2171 bool OtherResLimited = false;
2172 if (SchedModel->hasInstrSchedModel()) {
2173 unsigned LFactor = SchedModel->getLatencyFactor();
2174 OtherResLimited = (int)(OtherCount - (RemLatency * LFactor)) > (int)LFactor;
2176 // Schedule aggressively for latency in PostRA mode. We don't check for
2177 // acyclic latency during PostRA, and highly out-of-order processors will
2178 // skip PostRA scheduling.
2179 if (!OtherResLimited) {
2180 if (IsPostRA || (RemLatency + CurrZone.getCurrCycle() > Rem.CriticalPath)) {
2181 Policy.ReduceLatency |= true;
2182 DEBUG(dbgs() << " " << CurrZone.Available.getName()
2183 << " RemainingLatency " << RemLatency << " + "
2184 << CurrZone.getCurrCycle() << "c > CritPath "
2185 << Rem.CriticalPath << "\n");
2188 // If the same resource is limiting inside and outside the zone, do nothing.
2189 if (CurrZone.getZoneCritResIdx() == OtherCritIdx)
2193 if (CurrZone.isResourceLimited()) {
2194 dbgs() << " " << CurrZone.Available.getName() << " ResourceLimited: "
2195 << SchedModel->getResourceName(CurrZone.getZoneCritResIdx())
2198 if (OtherResLimited)
2199 dbgs() << " RemainingLimit: "
2200 << SchedModel->getResourceName(OtherCritIdx) << "\n";
2201 if (!CurrZone.isResourceLimited() && !OtherResLimited)
2202 dbgs() << " Latency limited both directions.\n");
2204 if (CurrZone.isResourceLimited() && !Policy.ReduceResIdx)
2205 Policy.ReduceResIdx = CurrZone.getZoneCritResIdx();
2207 if (OtherResLimited)
2208 Policy.DemandResIdx = OtherCritIdx;
2212 const char *GenericSchedulerBase::getReasonStr(
2213 GenericSchedulerBase::CandReason Reason) {
2215 case NoCand: return "NOCAND ";
2216 case PhysRegCopy: return "PREG-COPY";
2217 case RegExcess: return "REG-EXCESS";
2218 case RegCritical: return "REG-CRIT ";
2219 case Stall: return "STALL ";
2220 case Cluster: return "CLUSTER ";
2221 case Weak: return "WEAK ";
2222 case RegMax: return "REG-MAX ";
2223 case ResourceReduce: return "RES-REDUCE";
2224 case ResourceDemand: return "RES-DEMAND";
2225 case TopDepthReduce: return "TOP-DEPTH ";
2226 case TopPathReduce: return "TOP-PATH ";
2227 case BotHeightReduce:return "BOT-HEIGHT";
2228 case BotPathReduce: return "BOT-PATH ";
2229 case NextDefUse: return "DEF-USE ";
2230 case NodeOrder: return "ORDER ";
2232 llvm_unreachable("Unknown reason!");
2235 void GenericSchedulerBase::traceCandidate(const SchedCandidate &Cand) {
2237 unsigned ResIdx = 0;
2238 unsigned Latency = 0;
2239 switch (Cand.Reason) {
2243 P = Cand.RPDelta.Excess;
2246 P = Cand.RPDelta.CriticalMax;
2249 P = Cand.RPDelta.CurrentMax;
2251 case ResourceReduce:
2252 ResIdx = Cand.Policy.ReduceResIdx;
2254 case ResourceDemand:
2255 ResIdx = Cand.Policy.DemandResIdx;
2257 case TopDepthReduce:
2258 Latency = Cand.SU->getDepth();
2261 Latency = Cand.SU->getHeight();
2263 case BotHeightReduce:
2264 Latency = Cand.SU->getHeight();
2267 Latency = Cand.SU->getDepth();
2270 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason);
2272 dbgs() << " " << TRI->getRegPressureSetName(P.getPSet())
2273 << ":" << P.getUnitInc() << " ";
2277 dbgs() << " " << SchedModel->getProcResource(ResIdx)->Name << " ";
2281 dbgs() << " " << Latency << " cycles ";
2288 /// Return true if this heuristic determines order.
2289 static bool tryLess(int TryVal, int CandVal,
2290 GenericSchedulerBase::SchedCandidate &TryCand,
2291 GenericSchedulerBase::SchedCandidate &Cand,
2292 GenericSchedulerBase::CandReason Reason) {
2293 if (TryVal < CandVal) {
2294 TryCand.Reason = Reason;
2297 if (TryVal > CandVal) {
2298 if (Cand.Reason > Reason)
2299 Cand.Reason = Reason;
2302 Cand.setRepeat(Reason);
2306 static bool tryGreater(int TryVal, int CandVal,
2307 GenericSchedulerBase::SchedCandidate &TryCand,
2308 GenericSchedulerBase::SchedCandidate &Cand,
2309 GenericSchedulerBase::CandReason Reason) {
2310 if (TryVal > CandVal) {
2311 TryCand.Reason = Reason;
2314 if (TryVal < CandVal) {
2315 if (Cand.Reason > Reason)
2316 Cand.Reason = Reason;
2319 Cand.setRepeat(Reason);
2323 static bool tryLatency(GenericSchedulerBase::SchedCandidate &TryCand,
2324 GenericSchedulerBase::SchedCandidate &Cand,
2325 SchedBoundary &Zone) {
2327 if (Cand.SU->getDepth() > Zone.getScheduledLatency()) {
2328 if (tryLess(TryCand.SU->getDepth(), Cand.SU->getDepth(),
2329 TryCand, Cand, GenericSchedulerBase::TopDepthReduce))
2332 if (tryGreater(TryCand.SU->getHeight(), Cand.SU->getHeight(),
2333 TryCand, Cand, GenericSchedulerBase::TopPathReduce))
2337 if (Cand.SU->getHeight() > Zone.getScheduledLatency()) {
2338 if (tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(),
2339 TryCand, Cand, GenericSchedulerBase::BotHeightReduce))
2342 if (tryGreater(TryCand.SU->getDepth(), Cand.SU->getDepth(),
2343 TryCand, Cand, GenericSchedulerBase::BotPathReduce))
2349 static void tracePick(const GenericSchedulerBase::SchedCandidate &Cand,
2351 DEBUG(dbgs() << "Pick " << (IsTop ? "Top " : "Bot ")
2352 << GenericSchedulerBase::getReasonStr(Cand.Reason) << '\n');
2355 void GenericScheduler::initialize(ScheduleDAGMI *dag) {
2356 assert(dag->hasVRegLiveness() &&
2357 "(PreRA)GenericScheduler needs vreg liveness");
2358 DAG = static_cast<ScheduleDAGMILive*>(dag);
2359 SchedModel = DAG->getSchedModel();
2362 Rem.init(DAG, SchedModel);
2363 Top.init(DAG, SchedModel, &Rem);
2364 Bot.init(DAG, SchedModel, &Rem);
2366 // Initialize resource counts.
2368 // Initialize the HazardRecognizers. If itineraries don't exist, are empty, or
2369 // are disabled, then these HazardRecs will be disabled.
2370 const InstrItineraryData *Itin = SchedModel->getInstrItineraries();
2371 if (!Top.HazardRec) {
2373 DAG->MF.getSubtarget().getInstrInfo()->CreateTargetMIHazardRecognizer(
2376 if (!Bot.HazardRec) {
2378 DAG->MF.getSubtarget().getInstrInfo()->CreateTargetMIHazardRecognizer(
2383 /// Initialize the per-region scheduling policy.
2384 void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
2385 MachineBasicBlock::iterator End,
2386 unsigned NumRegionInstrs) {
2387 const MachineFunction &MF = *Begin->getParent()->getParent();
2388 const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
2390 // Avoid setting up the register pressure tracker for small regions to save
2391 // compile time. As a rough heuristic, only track pressure when the number of
2392 // schedulable instructions exceeds half the integer register file.
2393 RegionPolicy.ShouldTrackPressure = true;
2394 for (unsigned VT = MVT::i32; VT > (unsigned)MVT::i1; --VT) {
2395 MVT::SimpleValueType LegalIntVT = (MVT::SimpleValueType)VT;
2396 if (TLI->isTypeLegal(LegalIntVT)) {
2397 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs(
2398 TLI->getRegClassFor(LegalIntVT));
2399 RegionPolicy.ShouldTrackPressure = NumRegionInstrs > (NIntRegs / 2);
2403 // For generic targets, we default to bottom-up, because it's simpler and more
2404 // compile-time optimizations have been implemented in that direction.
2405 RegionPolicy.OnlyBottomUp = true;
2407 // Allow the subtarget to override default policy.
2408 MF.getSubtarget().overrideSchedPolicy(RegionPolicy, Begin, End,
2411 // After subtarget overrides, apply command line options.
2412 if (!EnableRegPressure)
2413 RegionPolicy.ShouldTrackPressure = false;
2415 // Check -misched-topdown/bottomup can force or unforce scheduling direction.
2416 // e.g. -misched-bottomup=false allows scheduling in both directions.
2417 assert((!ForceTopDown || !ForceBottomUp) &&
2418 "-misched-topdown incompatible with -misched-bottomup");
2419 if (ForceBottomUp.getNumOccurrences() > 0) {
2420 RegionPolicy.OnlyBottomUp = ForceBottomUp;
2421 if (RegionPolicy.OnlyBottomUp)
2422 RegionPolicy.OnlyTopDown = false;
2424 if (ForceTopDown.getNumOccurrences() > 0) {
2425 RegionPolicy.OnlyTopDown = ForceTopDown;
2426 if (RegionPolicy.OnlyTopDown)
2427 RegionPolicy.OnlyBottomUp = false;
2431 /// Set IsAcyclicLatencyLimited if the acyclic path is longer than the cyclic
2432 /// critical path by more cycles than it takes to drain the instruction buffer.
2433 /// We estimate an upper bounds on in-flight instructions as:
2435 /// CyclesPerIteration = max( CyclicPath, Loop-Resource-Height )
2436 /// InFlightIterations = AcyclicPath / CyclesPerIteration
2437 /// InFlightResources = InFlightIterations * LoopResources
2439 /// TODO: Check execution resources in addition to IssueCount.
2440 void GenericScheduler::checkAcyclicLatency() {
2441 if (Rem.CyclicCritPath == 0 || Rem.CyclicCritPath >= Rem.CriticalPath)
2444 // Scaled number of cycles per loop iteration.
2445 unsigned IterCount =
2446 std::max(Rem.CyclicCritPath * SchedModel->getLatencyFactor(),
2448 // Scaled acyclic critical path.
2449 unsigned AcyclicCount = Rem.CriticalPath * SchedModel->getLatencyFactor();
2450 // InFlightCount = (AcyclicPath / IterCycles) * InstrPerLoop
2451 unsigned InFlightCount =
2452 (AcyclicCount * Rem.RemIssueCount + IterCount-1) / IterCount;
2453 unsigned BufferLimit =
2454 SchedModel->getMicroOpBufferSize() * SchedModel->getMicroOpFactor();
2456 Rem.IsAcyclicLatencyLimited = InFlightCount > BufferLimit;
2458 DEBUG(dbgs() << "IssueCycles="
2459 << Rem.RemIssueCount / SchedModel->getLatencyFactor() << "c "
2460 << "IterCycles=" << IterCount / SchedModel->getLatencyFactor()
2461 << "c NumIters=" << (AcyclicCount + IterCount-1) / IterCount
2462 << " InFlight=" << InFlightCount / SchedModel->getMicroOpFactor()
2463 << "m BufferLim=" << SchedModel->getMicroOpBufferSize() << "m\n";
2464 if (Rem.IsAcyclicLatencyLimited)
2465 dbgs() << " ACYCLIC LATENCY LIMIT\n");
2468 void GenericScheduler::registerRoots() {
2469 Rem.CriticalPath = DAG->ExitSU.getDepth();
2471 // Some roots may not feed into ExitSU. Check all of them in case.
2472 for (std::vector<SUnit*>::const_iterator
2473 I = Bot.Available.begin(), E = Bot.Available.end(); I != E; ++I) {
2474 if ((*I)->getDepth() > Rem.CriticalPath)
2475 Rem.CriticalPath = (*I)->getDepth();
2477 DEBUG(dbgs() << "Critical Path(GS-RR ): " << Rem.CriticalPath << '\n');
2478 if (DumpCriticalPathLength) {
2479 errs() << "Critical Path(GS-RR ): " << Rem.CriticalPath << " \n";
2482 if (EnableCyclicPath) {
2483 Rem.CyclicCritPath = DAG->computeCyclicCriticalPath();
2484 checkAcyclicLatency();
2488 static bool tryPressure(const PressureChange &TryP,
2489 const PressureChange &CandP,
2490 GenericSchedulerBase::SchedCandidate &TryCand,
2491 GenericSchedulerBase::SchedCandidate &Cand,
2492 GenericSchedulerBase::CandReason Reason) {
2493 int TryRank = TryP.getPSetOrMax();
2494 int CandRank = CandP.getPSetOrMax();
2495 // If both candidates affect the same set, go with the smallest increase.
2496 if (TryRank == CandRank) {
2497 return tryLess(TryP.getUnitInc(), CandP.getUnitInc(), TryCand, Cand,
2500 // If one candidate decreases and the other increases, go with it.
2501 // Invalid candidates have UnitInc==0.
2502 if (tryGreater(TryP.getUnitInc() < 0, CandP.getUnitInc() < 0, TryCand, Cand,
2506 // If the candidates are decreasing pressure, reverse priority.
2507 if (TryP.getUnitInc() < 0)
2508 std::swap(TryRank, CandRank);
2509 return tryGreater(TryRank, CandRank, TryCand, Cand, Reason);
2512 static unsigned getWeakLeft(const SUnit *SU, bool isTop) {
2513 return (isTop) ? SU->WeakPredsLeft : SU->WeakSuccsLeft;
2516 /// Minimize physical register live ranges. Regalloc wants them adjacent to
2517 /// their physreg def/use.
2519 /// FIXME: This is an unnecessary check on the critical path. Most are root/leaf
2520 /// copies which can be prescheduled. The rest (e.g. x86 MUL) could be bundled
2521 /// with the operation that produces or consumes the physreg. We'll do this when
2522 /// regalloc has support for parallel copies.
2523 static int biasPhysRegCopy(const SUnit *SU, bool isTop) {
2524 const MachineInstr *MI = SU->getInstr();
2528 unsigned ScheduledOper = isTop ? 1 : 0;
2529 unsigned UnscheduledOper = isTop ? 0 : 1;
2530 // If we have already scheduled the physreg produce/consumer, immediately
2531 // schedule the copy.
2532 if (TargetRegisterInfo::isPhysicalRegister(
2533 MI->getOperand(ScheduledOper).getReg()))
2535 // If the physreg is at the boundary, defer it. Otherwise schedule it
2536 // immediately to free the dependent. We can hoist the copy later.
2537 bool AtBoundary = isTop ? !SU->NumSuccsLeft : !SU->NumPredsLeft;
2538 if (TargetRegisterInfo::isPhysicalRegister(
2539 MI->getOperand(UnscheduledOper).getReg()))
2540 return AtBoundary ? -1 : 1;
2544 /// Apply a set of heursitics to a new candidate. Heuristics are currently
2545 /// hierarchical. This may be more efficient than a graduated cost model because
2546 /// we don't need to evaluate all aspects of the model for each node in the
2547 /// queue. But it's really done to make the heuristics easier to debug and
2548 /// statistically analyze.
2550 /// \param Cand provides the policy and current best candidate.
2551 /// \param TryCand refers to the next SUnit candidate, otherwise uninitialized.
2552 /// \param Zone describes the scheduled zone that we are extending.
2553 /// \param RPTracker describes reg pressure within the scheduled zone.
2554 /// \param TempTracker is a scratch pressure tracker to reuse in queries.
2555 void GenericScheduler::tryCandidate(SchedCandidate &Cand,
2556 SchedCandidate &TryCand,
2557 SchedBoundary &Zone,
2558 const RegPressureTracker &RPTracker,
2559 RegPressureTracker &TempTracker) {
2561 if (DAG->isTrackingPressure()) {
2562 // Always initialize TryCand's RPDelta.
2564 TempTracker.getMaxDownwardPressureDelta(
2565 TryCand.SU->getInstr(),
2567 DAG->getRegionCriticalPSets(),
2568 DAG->getRegPressure().MaxSetPressure);
2571 if (VerifyScheduling) {
2572 TempTracker.getMaxUpwardPressureDelta(
2573 TryCand.SU->getInstr(),
2574 &DAG->getPressureDiff(TryCand.SU),
2576 DAG->getRegionCriticalPSets(),
2577 DAG->getRegPressure().MaxSetPressure);
2580 RPTracker.getUpwardPressureDelta(
2581 TryCand.SU->getInstr(),
2582 DAG->getPressureDiff(TryCand.SU),
2584 DAG->getRegionCriticalPSets(),
2585 DAG->getRegPressure().MaxSetPressure);
2589 DEBUG(if (TryCand.RPDelta.Excess.isValid())
2590 dbgs() << " SU(" << TryCand.SU->NodeNum << ") "
2591 << TRI->getRegPressureSetName(TryCand.RPDelta.Excess.getPSet())
2592 << ":" << TryCand.RPDelta.Excess.getUnitInc() << "\n");
2594 // Initialize the candidate if needed.
2595 if (!Cand.isValid()) {
2596 TryCand.Reason = NodeOrder;
2600 if (tryGreater(biasPhysRegCopy(TryCand.SU, Zone.isTop()),
2601 biasPhysRegCopy(Cand.SU, Zone.isTop()),
2602 TryCand, Cand, PhysRegCopy))
2605 // Avoid exceeding the target's limit. If signed PSetID is negative, it is
2606 // invalid; convert it to INT_MAX to give it lowest priority.
2607 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.Excess,
2608 Cand.RPDelta.Excess,
2609 TryCand, Cand, RegExcess))
2612 // Avoid increasing the max critical pressure in the scheduled region.
2613 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.CriticalMax,
2614 Cand.RPDelta.CriticalMax,
2615 TryCand, Cand, RegCritical))
2618 // For loops that are acyclic path limited, aggressively schedule for latency.
2619 // This can result in very long dependence chains scheduled in sequence, so
2620 // once every cycle (when CurrMOps == 0), switch to normal heuristics.
2621 if (Rem.IsAcyclicLatencyLimited && !Zone.getCurrMOps()
2622 && tryLatency(TryCand, Cand, Zone))
2625 // Prioritize instructions that read unbuffered resources by stall cycles.
2626 if (tryLess(Zone.getLatencyStallCycles(TryCand.SU),
2627 Zone.getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall))
2630 // Keep clustered nodes together to encourage downstream peephole
2631 // optimizations which may reduce resource requirements.
2633 // This is a best effort to set things up for a post-RA pass. Optimizations
2634 // like generating loads of multiple registers should ideally be done within
2635 // the scheduler pass by combining the loads during DAG postprocessing.
2636 const SUnit *NextClusterSU =
2637 Zone.isTop() ? DAG->getNextClusterSucc() : DAG->getNextClusterPred();
2638 if (tryGreater(TryCand.SU == NextClusterSU, Cand.SU == NextClusterSU,
2639 TryCand, Cand, Cluster))
2642 // Weak edges are for clustering and other constraints.
2643 if (tryLess(getWeakLeft(TryCand.SU, Zone.isTop()),
2644 getWeakLeft(Cand.SU, Zone.isTop()),
2645 TryCand, Cand, Weak)) {
2648 // Avoid increasing the max pressure of the entire region.
2649 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.CurrentMax,
2650 Cand.RPDelta.CurrentMax,
2651 TryCand, Cand, RegMax))
2654 // Avoid critical resource consumption and balance the schedule.
2655 TryCand.initResourceDelta(DAG, SchedModel);
2656 if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
2657 TryCand, Cand, ResourceReduce))
2659 if (tryGreater(TryCand.ResDelta.DemandedResources,
2660 Cand.ResDelta.DemandedResources,
2661 TryCand, Cand, ResourceDemand))
2664 // Avoid serializing long latency dependence chains.
2665 // For acyclic path limited loops, latency was already checked above.
2666 if (Cand.Policy.ReduceLatency && !Rem.IsAcyclicLatencyLimited
2667 && tryLatency(TryCand, Cand, Zone)) {
2671 // Prefer immediate defs/users of the last scheduled instruction. This is a
2672 // local pressure avoidance strategy that also makes the machine code
2674 if (tryGreater(Zone.isNextSU(TryCand.SU), Zone.isNextSU(Cand.SU),
2675 TryCand, Cand, NextDefUse))
2678 // Fall through to original instruction order.
2679 if ((Zone.isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum)
2680 || (!Zone.isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) {
2681 TryCand.Reason = NodeOrder;
2685 /// Pick the best candidate from the queue.
2687 /// TODO: getMaxPressureDelta results can be mostly cached for each SUnit during
2688 /// DAG building. To adjust for the current scheduling location we need to
2689 /// maintain the number of vreg uses remaining to be top-scheduled.
2690 void GenericScheduler::pickNodeFromQueue(SchedBoundary &Zone,
2691 const RegPressureTracker &RPTracker,
2692 SchedCandidate &Cand) {
2693 ReadyQueue &Q = Zone.Available;
2697 // getMaxPressureDelta temporarily modifies the tracker.
2698 RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker);
2700 for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
2702 SchedCandidate TryCand(Cand.Policy);
2704 tryCandidate(Cand, TryCand, Zone, RPTracker, TempTracker);
2705 if (TryCand.Reason != NoCand) {
2706 // Initialize resource delta if needed in case future heuristics query it.
2707 if (TryCand.ResDelta == SchedResourceDelta())
2708 TryCand.initResourceDelta(DAG, SchedModel);
2709 Cand.setBest(TryCand);
2710 DEBUG(traceCandidate(Cand));
2715 /// Pick the best candidate node from either the top or bottom queue.
2716 SUnit *GenericScheduler::pickNodeBidirectional(bool &IsTopNode) {
2717 // Schedule as far as possible in the direction of no choice. This is most
2718 // efficient, but also provides the best heuristics for CriticalPSets.
2719 if (SUnit *SU = Bot.pickOnlyChoice()) {
2721 DEBUG(dbgs() << "Pick Bot NOCAND\n");
2724 if (SUnit *SU = Top.pickOnlyChoice()) {
2726 DEBUG(dbgs() << "Pick Top NOCAND\n");
2729 CandPolicy NoPolicy;
2730 SchedCandidate BotCand(NoPolicy);
2731 SchedCandidate TopCand(NoPolicy);
2732 // Set the bottom-up policy based on the state of the current bottom zone and
2733 // the instructions outside the zone, including the top zone.
2734 setPolicy(BotCand.Policy, /*IsPostRA=*/false, Bot, &Top);
2735 // Set the top-down policy based on the state of the current top zone and
2736 // the instructions outside the zone, including the bottom zone.
2737 setPolicy(TopCand.Policy, /*IsPostRA=*/false, Top, &Bot);
2739 // Prefer bottom scheduling when heuristics are silent.
2740 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2741 assert(BotCand.Reason != NoCand && "failed to find the first candidate");
2743 // If either Q has a single candidate that provides the least increase in
2744 // Excess pressure, we can immediately schedule from that Q.
2746 // RegionCriticalPSets summarizes the pressure within the scheduled region and
2747 // affects picking from either Q. If scheduling in one direction must
2748 // increase pressure for one of the excess PSets, then schedule in that
2749 // direction first to provide more freedom in the other direction.
2750 if ((BotCand.Reason == RegExcess && !BotCand.isRepeat(RegExcess))
2751 || (BotCand.Reason == RegCritical
2752 && !BotCand.isRepeat(RegCritical)))
2755 tracePick(BotCand, IsTopNode);
2758 // Check if the top Q has a better candidate.
2759 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2760 assert(TopCand.Reason != NoCand && "failed to find the first candidate");
2762 // Choose the queue with the most important (lowest enum) reason.
2763 if (TopCand.Reason < BotCand.Reason) {
2765 tracePick(TopCand, IsTopNode);
2768 // Otherwise prefer the bottom candidate, in node order if all else failed.
2770 tracePick(BotCand, IsTopNode);
2774 /// Pick the best node to balance the schedule. Implements MachineSchedStrategy.
2775 SUnit *GenericScheduler::pickNode(bool &IsTopNode) {
2776 if (DAG->top() == DAG->bottom()) {
2777 assert(Top.Available.empty() && Top.Pending.empty() &&
2778 Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage");
2783 if (RegionPolicy.OnlyTopDown) {
2784 SU = Top.pickOnlyChoice();
2786 CandPolicy NoPolicy;
2787 SchedCandidate TopCand(NoPolicy);
2788 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2789 assert(TopCand.Reason != NoCand && "failed to find a candidate");
2790 tracePick(TopCand, true);
2795 else if (RegionPolicy.OnlyBottomUp) {
2796 SU = Bot.pickOnlyChoice();
2798 CandPolicy NoPolicy;
2799 SchedCandidate BotCand(NoPolicy);
2800 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2801 assert(BotCand.Reason != NoCand && "failed to find a candidate");
2802 tracePick(BotCand, false);
2808 SU = pickNodeBidirectional(IsTopNode);
2810 } while (SU->isScheduled);
2812 if (SU->isTopReady())
2813 Top.removeReady(SU);
2814 if (SU->isBottomReady())
2815 Bot.removeReady(SU);
2817 DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr());
2821 void GenericScheduler::reschedulePhysRegCopies(SUnit *SU, bool isTop) {
2823 MachineBasicBlock::iterator InsertPos = SU->getInstr();
2826 SmallVectorImpl<SDep> &Deps = isTop ? SU->Preds : SU->Succs;
2828 // Find already scheduled copies with a single physreg dependence and move
2829 // them just above the scheduled instruction.
2830 for (SmallVectorImpl<SDep>::iterator I = Deps.begin(), E = Deps.end();
2832 if (I->getKind() != SDep::Data || !TRI->isPhysicalRegister(I->getReg()))
2834 SUnit *DepSU = I->getSUnit();
2835 if (isTop ? DepSU->Succs.size() > 1 : DepSU->Preds.size() > 1)
2837 MachineInstr *Copy = DepSU->getInstr();
2838 if (!Copy->isCopy())
2840 DEBUG(dbgs() << " Rescheduling physreg copy ";
2841 I->getSUnit()->dump(DAG));
2842 DAG->moveInstruction(Copy, InsertPos);
2846 /// Update the scheduler's state after scheduling a node. This is the same node
2847 /// that was just returned by pickNode(). However, ScheduleDAGMILive needs to
2848 /// update it's state based on the current cycle before MachineSchedStrategy
2851 /// FIXME: Eventually, we may bundle physreg copies rather than rescheduling
2852 /// them here. See comments in biasPhysRegCopy.
2853 void GenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
2855 SU->TopReadyCycle = std::max(SU->TopReadyCycle, Top.getCurrCycle());
2857 if (SU->hasPhysRegUses)
2858 reschedulePhysRegCopies(SU, true);
2861 SU->BotReadyCycle = std::max(SU->BotReadyCycle, Bot.getCurrCycle());
2863 if (SU->hasPhysRegDefs)
2864 reschedulePhysRegCopies(SU, false);
2868 /// Create the standard converging machine scheduler. This will be used as the
2869 /// default scheduler if the target does not set a default.
2870 static ScheduleDAGInstrs *createGenericSchedLive(MachineSchedContext *C) {
2871 ScheduleDAGMILive *DAG = new ScheduleDAGMILive(C, make_unique<GenericScheduler>(C));
2872 // Register DAG post-processors.
2874 // FIXME: extend the mutation API to allow earlier mutations to instantiate
2875 // data and pass it to later mutations. Have a single mutation that gathers
2876 // the interesting nodes in one pass.
2877 DAG->addMutation(make_unique<CopyConstrain>(DAG->TII, DAG->TRI));
2878 if (EnableLoadCluster && DAG->TII->enableClusterLoads())
2879 DAG->addMutation(make_unique<LoadClusterMutation>(DAG->TII, DAG->TRI));
2880 if (EnableMacroFusion)
2881 DAG->addMutation(make_unique<MacroFusion>(DAG->TII));
2885 static MachineSchedRegistry
2886 GenericSchedRegistry("converge", "Standard converging scheduler.",
2887 createGenericSchedLive);
2889 //===----------------------------------------------------------------------===//
2890 // PostGenericScheduler - Generic PostRA implementation of MachineSchedStrategy.
2891 //===----------------------------------------------------------------------===//
2893 void PostGenericScheduler::initialize(ScheduleDAGMI *Dag) {
2895 SchedModel = DAG->getSchedModel();
2898 Rem.init(DAG, SchedModel);
2899 Top.init(DAG, SchedModel, &Rem);
2902 // Initialize the HazardRecognizers. If itineraries don't exist, are empty,
2903 // or are disabled, then these HazardRecs will be disabled.
2904 const InstrItineraryData *Itin = SchedModel->getInstrItineraries();
2905 if (!Top.HazardRec) {
2907 DAG->MF.getSubtarget().getInstrInfo()->CreateTargetMIHazardRecognizer(
2913 void PostGenericScheduler::registerRoots() {
2914 Rem.CriticalPath = DAG->ExitSU.getDepth();
2916 // Some roots may not feed into ExitSU. Check all of them in case.
2917 for (SmallVectorImpl<SUnit*>::const_iterator
2918 I = BotRoots.begin(), E = BotRoots.end(); I != E; ++I) {
2919 if ((*I)->getDepth() > Rem.CriticalPath)
2920 Rem.CriticalPath = (*I)->getDepth();
2922 DEBUG(dbgs() << "Critical Path: (PGS-RR) " << Rem.CriticalPath << '\n');
2923 if (DumpCriticalPathLength) {
2924 errs() << "Critical Path(PGS-RR ): " << Rem.CriticalPath << " \n";
2928 /// Apply a set of heursitics to a new candidate for PostRA scheduling.
2930 /// \param Cand provides the policy and current best candidate.
2931 /// \param TryCand refers to the next SUnit candidate, otherwise uninitialized.
2932 void PostGenericScheduler::tryCandidate(SchedCandidate &Cand,
2933 SchedCandidate &TryCand) {
2935 // Initialize the candidate if needed.
2936 if (!Cand.isValid()) {
2937 TryCand.Reason = NodeOrder;
2941 // Prioritize instructions that read unbuffered resources by stall cycles.
2942 if (tryLess(Top.getLatencyStallCycles(TryCand.SU),
2943 Top.getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall))
2946 // Avoid critical resource consumption and balance the schedule.
2947 if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
2948 TryCand, Cand, ResourceReduce))
2950 if (tryGreater(TryCand.ResDelta.DemandedResources,
2951 Cand.ResDelta.DemandedResources,
2952 TryCand, Cand, ResourceDemand))
2955 // Avoid serializing long latency dependence chains.
2956 if (Cand.Policy.ReduceLatency && tryLatency(TryCand, Cand, Top)) {
2960 // Fall through to original instruction order.
2961 if (TryCand.SU->NodeNum < Cand.SU->NodeNum)
2962 TryCand.Reason = NodeOrder;
2965 void PostGenericScheduler::pickNodeFromQueue(SchedCandidate &Cand) {
2966 ReadyQueue &Q = Top.Available;
2970 for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
2971 SchedCandidate TryCand(Cand.Policy);
2973 TryCand.initResourceDelta(DAG, SchedModel);
2974 tryCandidate(Cand, TryCand);
2975 if (TryCand.Reason != NoCand) {
2976 Cand.setBest(TryCand);
2977 DEBUG(traceCandidate(Cand));
2982 /// Pick the next node to schedule.
2983 SUnit *PostGenericScheduler::pickNode(bool &IsTopNode) {
2984 if (DAG->top() == DAG->bottom()) {
2985 assert(Top.Available.empty() && Top.Pending.empty() && "ReadyQ garbage");
2990 SU = Top.pickOnlyChoice();
2992 CandPolicy NoPolicy;
2993 SchedCandidate TopCand(NoPolicy);
2994 // Set the top-down policy based on the state of the current top zone and
2995 // the instructions outside the zone, including the bottom zone.
2996 setPolicy(TopCand.Policy, /*IsPostRA=*/true, Top, nullptr);
2997 pickNodeFromQueue(TopCand);
2998 assert(TopCand.Reason != NoCand && "failed to find a candidate");
2999 tracePick(TopCand, true);
3002 } while (SU->isScheduled);
3005 Top.removeReady(SU);
3007 DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr());
3011 /// Called after ScheduleDAGMI has scheduled an instruction and updated
3012 /// scheduled/remaining flags in the DAG nodes.
3013 void PostGenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
3014 SU->TopReadyCycle = std::max(SU->TopReadyCycle, Top.getCurrCycle());
3018 /// Create a generic scheduler with no vreg liveness or DAG mutation passes.
3019 static ScheduleDAGInstrs *createGenericSchedPostRA(MachineSchedContext *C) {
3020 return new ScheduleDAGMI(C, make_unique<PostGenericScheduler>(C), /*IsPostRA=*/true);
3023 //===----------------------------------------------------------------------===//
3024 // ILP Scheduler. Currently for experimental analysis of heuristics.
3025 //===----------------------------------------------------------------------===//
3028 /// \brief Order nodes by the ILP metric.
3030 const SchedDFSResult *DFSResult;
3031 const BitVector *ScheduledTrees;
3034 ILPOrder(bool MaxILP)
3035 : DFSResult(nullptr), ScheduledTrees(nullptr), MaximizeILP(MaxILP) {}
3037 /// \brief Apply a less-than relation on node priority.
3039 /// (Return true if A comes after B in the Q.)
3040 bool operator()(const SUnit *A, const SUnit *B) const {
3041 unsigned SchedTreeA = DFSResult->getSubtreeID(A);
3042 unsigned SchedTreeB = DFSResult->getSubtreeID(B);
3043 if (SchedTreeA != SchedTreeB) {
3044 // Unscheduled trees have lower priority.
3045 if (ScheduledTrees->test(SchedTreeA) != ScheduledTrees->test(SchedTreeB))
3046 return ScheduledTrees->test(SchedTreeB);
3048 // Trees with shallower connections have have lower priority.
3049 if (DFSResult->getSubtreeLevel(SchedTreeA)
3050 != DFSResult->getSubtreeLevel(SchedTreeB)) {
3051 return DFSResult->getSubtreeLevel(SchedTreeA)
3052 < DFSResult->getSubtreeLevel(SchedTreeB);
3056 return DFSResult->getILP(A) < DFSResult->getILP(B);
3058 return DFSResult->getILP(A) > DFSResult->getILP(B);
3062 /// \brief Schedule based on the ILP metric.
3063 class ILPScheduler : public MachineSchedStrategy {
3064 ScheduleDAGMILive *DAG;
3067 std::vector<SUnit*> ReadyQ;
3069 ILPScheduler(bool MaximizeILP): DAG(nullptr), Cmp(MaximizeILP) {}
3071 void initialize(ScheduleDAGMI *dag) override {
3072 assert(dag->hasVRegLiveness() && "ILPScheduler needs vreg liveness");
3073 DAG = static_cast<ScheduleDAGMILive*>(dag);
3074 DAG->computeDFSResult();
3075 Cmp.DFSResult = DAG->getDFSResult();
3076 Cmp.ScheduledTrees = &DAG->getScheduledTrees();
3080 void registerRoots() override {
3081 // Restore the heap in ReadyQ with the updated DFS results.
3082 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3085 /// Implement MachineSchedStrategy interface.
3086 /// -----------------------------------------
3088 /// Callback to select the highest priority node from the ready Q.
3089 SUnit *pickNode(bool &IsTopNode) override {
3090 if (ReadyQ.empty()) return nullptr;
3091 std::pop_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3092 SUnit *SU = ReadyQ.back();
3095 DEBUG(dbgs() << "Pick node " << "SU(" << SU->NodeNum << ") "
3096 << " ILP: " << DAG->getDFSResult()->getILP(SU)
3097 << " Tree: " << DAG->getDFSResult()->getSubtreeID(SU) << " @"
3098 << DAG->getDFSResult()->getSubtreeLevel(
3099 DAG->getDFSResult()->getSubtreeID(SU)) << '\n'
3100 << "Scheduling " << *SU->getInstr());
3104 /// \brief Scheduler callback to notify that a new subtree is scheduled.
3105 void scheduleTree(unsigned SubtreeID) override {
3106 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3109 /// Callback after a node is scheduled. Mark a newly scheduled tree, notify
3110 /// DFSResults, and resort the priority Q.
3111 void schedNode(SUnit *SU, bool IsTopNode) override {
3112 assert(!IsTopNode && "SchedDFSResult needs bottom-up");
3115 void releaseTopNode(SUnit *) override { /*only called for top roots*/ }
3117 void releaseBottomNode(SUnit *SU) override {
3118 ReadyQ.push_back(SU);
3119 std::push_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3124 static ScheduleDAGInstrs *createILPMaxScheduler(MachineSchedContext *C) {
3125 return new ScheduleDAGMILive(C, make_unique<ILPScheduler>(true));
3127 static ScheduleDAGInstrs *createILPMinScheduler(MachineSchedContext *C) {
3128 return new ScheduleDAGMILive(C, make_unique<ILPScheduler>(false));
3130 static MachineSchedRegistry ILPMaxRegistry(
3131 "ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler);
3132 static MachineSchedRegistry ILPMinRegistry(
3133 "ilpmin", "Schedule bottom-up for min ILP", createILPMinScheduler);
3135 //===----------------------------------------------------------------------===//
3136 // Machine Instruction Shuffler for Correctness Testing
3137 //===----------------------------------------------------------------------===//
3141 /// Apply a less-than relation on the node order, which corresponds to the
3142 /// instruction order prior to scheduling. IsReverse implements greater-than.
3143 template<bool IsReverse>
3145 bool operator()(SUnit *A, SUnit *B) const {
3147 return A->NodeNum > B->NodeNum;
3149 return A->NodeNum < B->NodeNum;
3153 /// Reorder instructions as much as possible.
3154 class InstructionShuffler : public MachineSchedStrategy {
3158 // Using a less-than relation (SUnitOrder<false>) for the TopQ priority
3159 // gives nodes with a higher number higher priority causing the latest
3160 // instructions to be scheduled first.
3161 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false> >
3163 // When scheduling bottom-up, use greater-than as the queue priority.
3164 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true> >
3167 InstructionShuffler(bool alternate, bool topdown)
3168 : IsAlternating(alternate), IsTopDown(topdown) {}
3170 void initialize(ScheduleDAGMI*) override {
3175 /// Implement MachineSchedStrategy interface.
3176 /// -----------------------------------------
3178 SUnit *pickNode(bool &IsTopNode) override {
3182 if (TopQ.empty()) return nullptr;
3185 } while (SU->isScheduled);
3190 if (BottomQ.empty()) return nullptr;
3193 } while (SU->isScheduled);
3197 IsTopDown = !IsTopDown;
3201 void schedNode(SUnit *SU, bool IsTopNode) override {}
3203 void releaseTopNode(SUnit *SU) override {
3206 void releaseBottomNode(SUnit *SU) override {
3212 static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
3213 bool Alternate = !ForceTopDown && !ForceBottomUp;
3214 bool TopDown = !ForceBottomUp;
3215 assert((TopDown || !ForceTopDown) &&
3216 "-misched-topdown incompatible with -misched-bottomup");
3217 return new ScheduleDAGMILive(C, make_unique<InstructionShuffler>(Alternate, TopDown));
3219 static MachineSchedRegistry ShufflerRegistry(
3220 "shuffle", "Shuffle machine instructions alternating directions",
3221 createInstructionShuffler);
3224 //===----------------------------------------------------------------------===//
3225 // GraphWriter support for ScheduleDAGMILive.
3226 //===----------------------------------------------------------------------===//
3231 template<> struct GraphTraits<
3232 ScheduleDAGMI*> : public GraphTraits<ScheduleDAG*> {};
3235 struct DOTGraphTraits<ScheduleDAGMI*> : public DefaultDOTGraphTraits {
3237 DOTGraphTraits (bool isSimple=false) : DefaultDOTGraphTraits(isSimple) {}
3239 static std::string getGraphName(const ScheduleDAG *G) {
3240 return G->MF.getName();
3243 static bool renderGraphFromBottomUp() {
3247 static bool isNodeHidden(const SUnit *Node) {
3248 return (Node->Preds.size() > 10 || Node->Succs.size() > 10);
3251 static bool hasNodeAddressLabel(const SUnit *Node,
3252 const ScheduleDAG *Graph) {
3256 /// If you want to override the dot attributes printed for a particular
3257 /// edge, override this method.
3258 static std::string getEdgeAttributes(const SUnit *Node,
3260 const ScheduleDAG *Graph) {
3261 if (EI.isArtificialDep())
3262 return "color=cyan,style=dashed";
3264 return "color=blue,style=dashed";
3268 static std::string getNodeLabel(const SUnit *SU, const ScheduleDAG *G) {
3270 raw_string_ostream SS(Str);
3271 const ScheduleDAGMI *DAG = static_cast<const ScheduleDAGMI*>(G);
3272 const SchedDFSResult *DFS = DAG->hasVRegLiveness() ?
3273 static_cast<const ScheduleDAGMILive*>(G)->getDFSResult() : nullptr;
3274 SS << "SU:" << SU->NodeNum;
3276 SS << " I:" << DFS->getNumInstrs(SU);
3279 static std::string getNodeDescription(const SUnit *SU, const ScheduleDAG *G) {
3280 return G->getGraphNodeLabel(SU);
3283 static std::string getNodeAttributes(const SUnit *N, const ScheduleDAG *G) {
3284 std::string Str("shape=Mrecord");
3285 const ScheduleDAGMI *DAG = static_cast<const ScheduleDAGMI*>(G);
3286 const SchedDFSResult *DFS = DAG->hasVRegLiveness() ?
3287 static_cast<const ScheduleDAGMILive*>(G)->getDFSResult() : nullptr;
3289 Str += ",style=filled,fillcolor=\"#";
3290 Str += DOT::getColorString(DFS->getSubtreeID(N));
3299 /// viewGraph - Pop up a ghostview window with the reachable parts of the DAG
3300 /// rendered using 'dot'.
3302 void ScheduleDAGMI::viewGraph(const Twine &Name, const Twine &Title) {
3304 ViewGraph(this, Name, false, Title);
3306 errs() << "ScheduleDAGMI::viewGraph is only available in debug builds on "
3307 << "systems with Graphviz or gv!\n";
3311 /// Out-of-line implementation with no arguments is handy for gdb.
3312 void ScheduleDAGMI::viewGraph() {
3313 viewGraph(getDAGName(), "Scheduling-Units Graph for " + getDAGName());