1 //===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MachineScheduler schedules machine instructions after phi elimination. It
11 // preserves LiveIntervals so it can be invoked before register allocation.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/MachineScheduler.h"
16 #include "llvm/ADT/PriorityQueue.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/MachineDominators.h"
20 #include "llvm/CodeGen/MachineLoopInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/CodeGen/RegisterClassInfo.h"
24 #include "llvm/CodeGen/ScheduleDFS.h"
25 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/GraphWriter.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/Target/TargetInstrInfo.h"
36 #define DEBUG_TYPE "misched"
39 cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
40 cl::desc("Force top-down list scheduling"));
41 cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
42 cl::desc("Force bottom-up list scheduling"));
44 DumpCriticalPathLength("misched-dcpl", cl::Hidden,
45 cl::desc("Print critical path length to stdout"));
49 static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden,
50 cl::desc("Pop up a window to show MISched dags after they are processed"));
52 /// In some situations a few uninteresting nodes depend on nearly all other
53 /// nodes in the graph, provide a cutoff to hide them.
54 static cl::opt<unsigned> ViewMISchedCutoff("view-misched-cutoff", cl::Hidden,
55 cl::desc("Hide nodes with more predecessor/successor than cutoff"));
57 static cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden,
58 cl::desc("Stop scheduling after N instructions"), cl::init(~0U));
60 static cl::opt<std::string> SchedOnlyFunc("misched-only-func", cl::Hidden,
61 cl::desc("Only schedule this function"));
62 static cl::opt<unsigned> SchedOnlyBlock("misched-only-block", cl::Hidden,
63 cl::desc("Only schedule this MBB#"));
65 static bool ViewMISchedDAGs = false;
68 static cl::opt<bool> EnableRegPressure("misched-regpressure", cl::Hidden,
69 cl::desc("Enable register pressure scheduling."), cl::init(true));
71 static cl::opt<bool> EnableCyclicPath("misched-cyclicpath", cl::Hidden,
72 cl::desc("Enable cyclic critical path analysis."), cl::init(true));
74 static cl::opt<bool> EnableLoadCluster("misched-cluster", cl::Hidden,
75 cl::desc("Enable load clustering."), cl::init(true));
77 // Experimental heuristics
78 static cl::opt<bool> EnableMacroFusion("misched-fusion", cl::Hidden,
79 cl::desc("Enable scheduling for macro fusion."), cl::init(true));
81 static cl::opt<bool> VerifyScheduling("verify-misched", cl::Hidden,
82 cl::desc("Verify machine instrs before and after machine scheduling"));
84 // DAG subtrees must have at least this many nodes.
85 static const unsigned MinSubtreeSize = 8;
87 // Pin the vtables to this file.
88 void MachineSchedStrategy::anchor() {}
89 void ScheduleDAGMutation::anchor() {}
91 //===----------------------------------------------------------------------===//
92 // Machine Instruction Scheduling Pass and Registry
93 //===----------------------------------------------------------------------===//
95 MachineSchedContext::MachineSchedContext():
96 MF(nullptr), MLI(nullptr), MDT(nullptr), PassConfig(nullptr), AA(nullptr), LIS(nullptr) {
97 RegClassInfo = new RegisterClassInfo();
100 MachineSchedContext::~MachineSchedContext() {
105 /// Base class for a machine scheduler class that can run at any point.
106 class MachineSchedulerBase : public MachineSchedContext,
107 public MachineFunctionPass {
109 MachineSchedulerBase(char &ID): MachineFunctionPass(ID) {}
111 void print(raw_ostream &O, const Module* = nullptr) const override;
114 void scheduleRegions(ScheduleDAGInstrs &Scheduler, bool FixKillFlags);
117 /// MachineScheduler runs after coalescing and before register allocation.
118 class MachineScheduler : public MachineSchedulerBase {
122 void getAnalysisUsage(AnalysisUsage &AU) const override;
124 bool runOnMachineFunction(MachineFunction&) override;
126 static char ID; // Class identification, replacement for typeinfo
129 ScheduleDAGInstrs *createMachineScheduler();
132 /// PostMachineScheduler runs after shortly before code emission.
133 class PostMachineScheduler : public MachineSchedulerBase {
135 PostMachineScheduler();
137 void getAnalysisUsage(AnalysisUsage &AU) const override;
139 bool runOnMachineFunction(MachineFunction&) override;
141 static char ID; // Class identification, replacement for typeinfo
144 ScheduleDAGInstrs *createPostMachineScheduler();
148 char MachineScheduler::ID = 0;
150 char &llvm::MachineSchedulerID = MachineScheduler::ID;
152 INITIALIZE_PASS_BEGIN(MachineScheduler, "machine-scheduler",
153 "Machine Instruction Scheduler", false, false)
154 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
155 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
156 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
157 INITIALIZE_PASS_END(MachineScheduler, "machine-scheduler",
158 "Machine Instruction Scheduler", false, false)
160 MachineScheduler::MachineScheduler()
161 : MachineSchedulerBase(ID) {
162 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
165 void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
166 AU.setPreservesCFG();
167 AU.addRequiredID(MachineDominatorsID);
168 AU.addRequired<MachineLoopInfo>();
169 AU.addRequired<AAResultsWrapperPass>();
170 AU.addRequired<TargetPassConfig>();
171 AU.addRequired<SlotIndexes>();
172 AU.addPreserved<SlotIndexes>();
173 AU.addRequired<LiveIntervals>();
174 AU.addPreserved<LiveIntervals>();
175 MachineFunctionPass::getAnalysisUsage(AU);
178 char PostMachineScheduler::ID = 0;
180 char &llvm::PostMachineSchedulerID = PostMachineScheduler::ID;
182 INITIALIZE_PASS(PostMachineScheduler, "postmisched",
183 "PostRA Machine Instruction Scheduler", false, false)
185 PostMachineScheduler::PostMachineScheduler()
186 : MachineSchedulerBase(ID) {
187 initializePostMachineSchedulerPass(*PassRegistry::getPassRegistry());
190 void PostMachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
191 AU.setPreservesCFG();
192 AU.addRequiredID(MachineDominatorsID);
193 AU.addRequired<MachineLoopInfo>();
194 AU.addRequired<TargetPassConfig>();
195 MachineFunctionPass::getAnalysisUsage(AU);
198 MachinePassRegistry MachineSchedRegistry::Registry;
200 /// A dummy default scheduler factory indicates whether the scheduler
201 /// is overridden on the command line.
202 static ScheduleDAGInstrs *useDefaultMachineSched(MachineSchedContext *C) {
206 /// MachineSchedOpt allows command line selection of the scheduler.
207 static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
208 RegisterPassParser<MachineSchedRegistry> >
209 MachineSchedOpt("misched",
210 cl::init(&useDefaultMachineSched), cl::Hidden,
211 cl::desc("Machine instruction scheduler to use"));
213 static MachineSchedRegistry
214 DefaultSchedRegistry("default", "Use the target's default scheduler choice.",
215 useDefaultMachineSched);
217 static cl::opt<bool> EnableMachineSched(
219 cl::desc("Enable the machine instruction scheduling pass."), cl::init(true),
222 /// Forward declare the standard machine scheduler. This will be used as the
223 /// default scheduler if the target does not set a default.
224 static ScheduleDAGInstrs *createGenericSchedLive(MachineSchedContext *C);
225 static ScheduleDAGInstrs *createGenericSchedPostRA(MachineSchedContext *C);
227 /// Decrement this iterator until reaching the top or a non-debug instr.
228 static MachineBasicBlock::const_iterator
229 priorNonDebug(MachineBasicBlock::const_iterator I,
230 MachineBasicBlock::const_iterator Beg) {
231 assert(I != Beg && "reached the top of the region, cannot decrement");
233 if (!I->isDebugValue())
239 /// Non-const version.
240 static MachineBasicBlock::iterator
241 priorNonDebug(MachineBasicBlock::iterator I,
242 MachineBasicBlock::const_iterator Beg) {
243 return const_cast<MachineInstr*>(
244 &*priorNonDebug(MachineBasicBlock::const_iterator(I), Beg));
247 /// If this iterator is a debug value, increment until reaching the End or a
248 /// non-debug instruction.
249 static MachineBasicBlock::const_iterator
250 nextIfDebug(MachineBasicBlock::const_iterator I,
251 MachineBasicBlock::const_iterator End) {
252 for(; I != End; ++I) {
253 if (!I->isDebugValue())
259 /// Non-const version.
260 static MachineBasicBlock::iterator
261 nextIfDebug(MachineBasicBlock::iterator I,
262 MachineBasicBlock::const_iterator End) {
263 // Cast the return value to nonconst MachineInstr, then cast to an
264 // instr_iterator, which does not check for null, finally return a
266 return MachineBasicBlock::instr_iterator(
267 const_cast<MachineInstr*>(
268 &*nextIfDebug(MachineBasicBlock::const_iterator(I), End)));
271 /// Instantiate a ScheduleDAGInstrs that will be owned by the caller.
272 ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() {
273 // Select the scheduler, or set the default.
274 MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
275 if (Ctor != useDefaultMachineSched)
278 // Get the default scheduler set by the target for this function.
279 ScheduleDAGInstrs *Scheduler = PassConfig->createMachineScheduler(this);
283 // Default to GenericScheduler.
284 return createGenericSchedLive(this);
287 /// Instantiate a ScheduleDAGInstrs for PostRA scheduling that will be owned by
288 /// the caller. We don't have a command line option to override the postRA
289 /// scheduler. The Target must configure it.
290 ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
291 // Get the postRA scheduler set by the target for this function.
292 ScheduleDAGInstrs *Scheduler = PassConfig->createPostMachineScheduler(this);
296 // Default to GenericScheduler.
297 return createGenericSchedPostRA(this);
300 /// Top-level MachineScheduler pass driver.
302 /// Visit blocks in function order. Divide each block into scheduling regions
303 /// and visit them bottom-up. Visiting regions bottom-up is not required, but is
304 /// consistent with the DAG builder, which traverses the interior of the
305 /// scheduling regions bottom-up.
307 /// This design avoids exposing scheduling boundaries to the DAG builder,
308 /// simplifying the DAG builder's support for "special" target instructions.
309 /// At the same time the design allows target schedulers to operate across
310 /// scheduling boundaries, for example to bundle the boudary instructions
311 /// without reordering them. This creates complexity, because the target
312 /// scheduler must update the RegionBegin and RegionEnd positions cached by
313 /// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler
314 /// design would be to split blocks at scheduling boundaries, but LLVM has a
315 /// general bias against block splitting purely for implementation simplicity.
316 bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
317 if (EnableMachineSched.getNumOccurrences()) {
318 if (!EnableMachineSched)
320 } else if (!mf.getSubtarget().enableMachineScheduler())
323 DEBUG(dbgs() << "Before MISched:\n"; mf.print(dbgs()));
325 // Initialize the context of the pass.
327 MLI = &getAnalysis<MachineLoopInfo>();
328 MDT = &getAnalysis<MachineDominatorTree>();
329 PassConfig = &getAnalysis<TargetPassConfig>();
330 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
332 LIS = &getAnalysis<LiveIntervals>();
334 if (VerifyScheduling) {
336 MF->verify(this, "Before machine scheduling.");
338 RegClassInfo->runOnMachineFunction(*MF);
340 // Instantiate the selected scheduler for this target, function, and
341 // optimization level.
342 std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler());
343 scheduleRegions(*Scheduler, false);
346 if (VerifyScheduling)
347 MF->verify(this, "After machine scheduling.");
351 bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) {
352 if (skipOptnoneFunction(*mf.getFunction()))
355 if (!mf.getSubtarget().enablePostRAScheduler()) {
356 DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n");
359 DEBUG(dbgs() << "Before post-MI-sched:\n"; mf.print(dbgs()));
361 // Initialize the context of the pass.
363 PassConfig = &getAnalysis<TargetPassConfig>();
365 if (VerifyScheduling)
366 MF->verify(this, "Before post machine scheduling.");
368 // Instantiate the selected scheduler for this target, function, and
369 // optimization level.
370 std::unique_ptr<ScheduleDAGInstrs> Scheduler(createPostMachineScheduler());
371 scheduleRegions(*Scheduler, true);
373 if (VerifyScheduling)
374 MF->verify(this, "After post machine scheduling.");
378 /// Return true of the given instruction should not be included in a scheduling
381 /// MachineScheduler does not currently support scheduling across calls. To
382 /// handle calls, the DAG builder needs to be modified to create register
383 /// anti/output dependencies on the registers clobbered by the call's regmask
384 /// operand. In PreRA scheduling, the stack pointer adjustment already prevents
385 /// scheduling across calls. In PostRA scheduling, we need the isCall to enforce
386 /// the boundary, but there would be no benefit to postRA scheduling across
387 /// calls this late anyway.
388 static bool isSchedBoundary(MachineBasicBlock::iterator MI,
389 MachineBasicBlock *MBB,
391 const TargetInstrInfo *TII) {
392 return MI->isCall() || TII->isSchedulingBoundary(MI, MBB, *MF);
395 /// Main driver for both MachineScheduler and PostMachineScheduler.
396 void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler,
398 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
400 // Visit all machine basic blocks.
402 // TODO: Visit blocks in global postorder or postorder within the bottom-up
403 // loop tree. Then we can optionally compute global RegPressure.
404 for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
405 MBB != MBBEnd; ++MBB) {
407 Scheduler.startBlock(&*MBB);
410 if (SchedOnlyFunc.getNumOccurrences() && SchedOnlyFunc != MF->getName())
412 if (SchedOnlyBlock.getNumOccurrences()
413 && (int)SchedOnlyBlock != MBB->getNumber())
417 // Break the block into scheduling regions [I, RegionEnd), and schedule each
418 // region as soon as it is discovered. RegionEnd points the scheduling
419 // boundary at the bottom of the region. The DAG does not include RegionEnd,
420 // but the region does (i.e. the next RegionEnd is above the previous
421 // RegionBegin). If the current block has no terminator then RegionEnd ==
422 // MBB->end() for the bottom region.
424 // The Scheduler may insert instructions during either schedule() or
425 // exitRegion(), even for empty regions. So the local iterators 'I' and
426 // 'RegionEnd' are invalid across these calls.
428 // MBB::size() uses instr_iterator to count. Here we need a bundle to count
429 // as a single instruction.
430 unsigned RemainingInstrs = std::distance(MBB->begin(), MBB->end());
431 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
432 RegionEnd != MBB->begin(); RegionEnd = Scheduler.begin()) {
434 // Avoid decrementing RegionEnd for blocks with no terminator.
435 if (RegionEnd != MBB->end() ||
436 isSchedBoundary(&*std::prev(RegionEnd), &*MBB, MF, TII)) {
438 // Count the boundary instruction.
442 // The next region starts above the previous region. Look backward in the
443 // instruction stream until we find the nearest boundary.
444 unsigned NumRegionInstrs = 0;
445 MachineBasicBlock::iterator I = RegionEnd;
446 for(;I != MBB->begin(); --I, --RemainingInstrs) {
447 if (isSchedBoundary(&*std::prev(I), &*MBB, MF, TII))
449 if (!I->isDebugValue())
452 // Notify the scheduler of the region, even if we may skip scheduling
453 // it. Perhaps it still needs to be bundled.
454 Scheduler.enterRegion(&*MBB, I, RegionEnd, NumRegionInstrs);
456 // Skip empty scheduling regions (0 or 1 schedulable instructions).
457 if (I == RegionEnd || I == std::prev(RegionEnd)) {
458 // Close the current region. Bundle the terminator if needed.
459 // This invalidates 'RegionEnd' and 'I'.
460 Scheduler.exitRegion();
463 DEBUG(dbgs() << "********** MI Scheduling **********\n");
464 DEBUG(dbgs() << MF->getName()
465 << ":BB#" << MBB->getNumber() << " " << MBB->getName()
466 << "\n From: " << *I << " To: ";
467 if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
468 else dbgs() << "End";
469 dbgs() << " RegionInstrs: " << NumRegionInstrs
470 << " Remaining: " << RemainingInstrs << "\n");
471 if (DumpCriticalPathLength) {
472 errs() << MF->getName();
473 errs() << ":BB# " << MBB->getNumber();
474 errs() << " " << MBB->getName() << " \n";
477 // Schedule a region: possibly reorder instructions.
478 // This invalidates 'RegionEnd' and 'I'.
479 Scheduler.schedule();
481 // Close the current region.
482 Scheduler.exitRegion();
484 // Scheduling has invalidated the current iterator 'I'. Ask the
485 // scheduler for the top of it's scheduled region.
486 RegionEnd = Scheduler.begin();
488 assert(RemainingInstrs == 0 && "Instruction count mismatch!");
489 Scheduler.finishBlock();
490 // FIXME: Ideally, no further passes should rely on kill flags. However,
491 // thumb2 size reduction is currently an exception, so the PostMIScheduler
494 Scheduler.fixupKills(&*MBB);
496 Scheduler.finalizeSchedule();
499 void MachineSchedulerBase::print(raw_ostream &O, const Module* m) const {
504 void ReadyQueue::dump() {
505 dbgs() << "Queue " << Name << ": ";
506 for (unsigned i = 0, e = Queue.size(); i < e; ++i)
507 dbgs() << Queue[i]->NodeNum << " ";
511 //===----------------------------------------------------------------------===//
512 // ScheduleDAGMI - Basic machine instruction scheduling. This is
513 // independent of PreRA/PostRA scheduling and involves no extra book-keeping for
514 // virtual registers.
515 // ===----------------------------------------------------------------------===/
517 // Provide a vtable anchor.
518 ScheduleDAGMI::~ScheduleDAGMI() {
521 bool ScheduleDAGMI::canAddEdge(SUnit *SuccSU, SUnit *PredSU) {
522 return SuccSU == &ExitSU || !Topo.IsReachable(PredSU, SuccSU);
525 bool ScheduleDAGMI::addEdge(SUnit *SuccSU, const SDep &PredDep) {
526 if (SuccSU != &ExitSU) {
527 // Do not use WillCreateCycle, it assumes SD scheduling.
528 // If Pred is reachable from Succ, then the edge creates a cycle.
529 if (Topo.IsReachable(PredDep.getSUnit(), SuccSU))
531 Topo.AddPred(SuccSU, PredDep.getSUnit());
533 SuccSU->addPred(PredDep, /*Required=*/!PredDep.isArtificial());
534 // Return true regardless of whether a new edge needed to be inserted.
538 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
539 /// NumPredsLeft reaches zero, release the successor node.
541 /// FIXME: Adjust SuccSU height based on MinLatency.
542 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
543 SUnit *SuccSU = SuccEdge->getSUnit();
545 if (SuccEdge->isWeak()) {
546 --SuccSU->WeakPredsLeft;
547 if (SuccEdge->isCluster())
548 NextClusterSucc = SuccSU;
552 if (SuccSU->NumPredsLeft == 0) {
553 dbgs() << "*** Scheduling failed! ***\n";
555 dbgs() << " has been released too many times!\n";
556 llvm_unreachable(nullptr);
559 // SU->TopReadyCycle was set to CurrCycle when it was scheduled. However,
560 // CurrCycle may have advanced since then.
561 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency())
562 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency();
564 --SuccSU->NumPredsLeft;
565 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
566 SchedImpl->releaseTopNode(SuccSU);
569 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
570 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
571 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
573 releaseSucc(SU, &*I);
577 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. When
578 /// NumSuccsLeft reaches zero, release the predecessor node.
580 /// FIXME: Adjust PredSU height based on MinLatency.
581 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
582 SUnit *PredSU = PredEdge->getSUnit();
584 if (PredEdge->isWeak()) {
585 --PredSU->WeakSuccsLeft;
586 if (PredEdge->isCluster())
587 NextClusterPred = PredSU;
591 if (PredSU->NumSuccsLeft == 0) {
592 dbgs() << "*** Scheduling failed! ***\n";
594 dbgs() << " has been released too many times!\n";
595 llvm_unreachable(nullptr);
598 // SU->BotReadyCycle was set to CurrCycle when it was scheduled. However,
599 // CurrCycle may have advanced since then.
600 if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency())
601 PredSU->BotReadyCycle = SU->BotReadyCycle + PredEdge->getLatency();
603 --PredSU->NumSuccsLeft;
604 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU)
605 SchedImpl->releaseBottomNode(PredSU);
608 /// releasePredecessors - Call releasePred on each of SU's predecessors.
609 void ScheduleDAGMI::releasePredecessors(SUnit *SU) {
610 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
612 releasePred(SU, &*I);
616 /// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
617 /// crossing a scheduling boundary. [begin, end) includes all instructions in
618 /// the region, including the boundary itself and single-instruction regions
619 /// that don't get scheduled.
620 void ScheduleDAGMI::enterRegion(MachineBasicBlock *bb,
621 MachineBasicBlock::iterator begin,
622 MachineBasicBlock::iterator end,
623 unsigned regioninstrs)
625 ScheduleDAGInstrs::enterRegion(bb, begin, end, regioninstrs);
627 SchedImpl->initPolicy(begin, end, regioninstrs);
630 /// This is normally called from the main scheduler loop but may also be invoked
631 /// by the scheduling strategy to perform additional code motion.
632 void ScheduleDAGMI::moveInstruction(
633 MachineInstr *MI, MachineBasicBlock::iterator InsertPos) {
634 // Advance RegionBegin if the first instruction moves down.
635 if (&*RegionBegin == MI)
638 // Update the instruction stream.
639 BB->splice(InsertPos, BB, MI);
641 // Update LiveIntervals
643 LIS->handleMove(MI, /*UpdateFlags=*/true);
645 // Recede RegionBegin if an instruction moves above the first.
646 if (RegionBegin == InsertPos)
650 bool ScheduleDAGMI::checkSchedLimit() {
652 if (NumInstrsScheduled == MISchedCutoff && MISchedCutoff != ~0U) {
653 CurrentTop = CurrentBottom;
656 ++NumInstrsScheduled;
661 /// Per-region scheduling driver, called back from
662 /// MachineScheduler::runOnMachineFunction. This is a simplified driver that
663 /// does not consider liveness or register pressure. It is useful for PostRA
664 /// scheduling and potentially other custom schedulers.
665 void ScheduleDAGMI::schedule() {
666 DEBUG(dbgs() << "ScheduleDAGMI::schedule starting\n");
667 DEBUG(SchedImpl->dumpPolicy());
672 Topo.InitDAGTopologicalSorting();
676 SmallVector<SUnit*, 8> TopRoots, BotRoots;
677 findRootsAndBiasEdges(TopRoots, BotRoots);
679 // Initialize the strategy before modifying the DAG.
680 // This may initialize a DFSResult to be used for queue priority.
681 SchedImpl->initialize(this);
683 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
684 SUnits[su].dumpAll(this));
685 if (ViewMISchedDAGs) viewGraph();
687 // Initialize ready queues now that the DAG and priority data are finalized.
688 initQueues(TopRoots, BotRoots);
690 bool IsTopNode = false;
692 DEBUG(dbgs() << "** ScheduleDAGMI::schedule picking next node\n");
693 SUnit *SU = SchedImpl->pickNode(IsTopNode);
696 assert(!SU->isScheduled && "Node already scheduled");
697 if (!checkSchedLimit())
700 MachineInstr *MI = SU->getInstr();
702 assert(SU->isTopReady() && "node still has unscheduled dependencies");
703 if (&*CurrentTop == MI)
704 CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);
706 moveInstruction(MI, CurrentTop);
709 assert(SU->isBottomReady() && "node still has unscheduled dependencies");
710 MachineBasicBlock::iterator priorII =
711 priorNonDebug(CurrentBottom, CurrentTop);
713 CurrentBottom = priorII;
715 if (&*CurrentTop == MI)
716 CurrentTop = nextIfDebug(++CurrentTop, priorII);
717 moveInstruction(MI, CurrentBottom);
721 // Notify the scheduling strategy before updating the DAG.
722 // This sets the scheduled node's ReadyCycle to CurrCycle. When updateQueues
723 // runs, it can then use the accurate ReadyCycle time to determine whether
724 // newly released nodes can move to the readyQ.
725 SchedImpl->schedNode(SU, IsTopNode);
727 updateQueues(SU, IsTopNode);
729 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
734 unsigned BBNum = begin()->getParent()->getNumber();
735 dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
741 /// Apply each ScheduleDAGMutation step in order.
742 void ScheduleDAGMI::postprocessDAG() {
743 for (unsigned i = 0, e = Mutations.size(); i < e; ++i) {
744 Mutations[i]->apply(this);
749 findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots,
750 SmallVectorImpl<SUnit*> &BotRoots) {
751 for (std::vector<SUnit>::iterator
752 I = SUnits.begin(), E = SUnits.end(); I != E; ++I) {
754 assert(!SU->isBoundaryNode() && "Boundary node should not be in SUnits");
756 // Order predecessors so DFSResult follows the critical path.
757 SU->biasCriticalPath();
759 // A SUnit is ready to top schedule if it has no predecessors.
760 if (!I->NumPredsLeft)
761 TopRoots.push_back(SU);
762 // A SUnit is ready to bottom schedule if it has no successors.
763 if (!I->NumSuccsLeft)
764 BotRoots.push_back(SU);
766 ExitSU.biasCriticalPath();
769 /// Identify DAG roots and setup scheduler queues.
770 void ScheduleDAGMI::initQueues(ArrayRef<SUnit*> TopRoots,
771 ArrayRef<SUnit*> BotRoots) {
772 NextClusterSucc = nullptr;
773 NextClusterPred = nullptr;
775 // Release all DAG roots for scheduling, not including EntrySU/ExitSU.
777 // Nodes with unreleased weak edges can still be roots.
778 // Release top roots in forward order.
779 for (SmallVectorImpl<SUnit*>::const_iterator
780 I = TopRoots.begin(), E = TopRoots.end(); I != E; ++I) {
781 SchedImpl->releaseTopNode(*I);
783 // Release bottom roots in reverse order so the higher priority nodes appear
784 // first. This is more natural and slightly more efficient.
785 for (SmallVectorImpl<SUnit*>::const_reverse_iterator
786 I = BotRoots.rbegin(), E = BotRoots.rend(); I != E; ++I) {
787 SchedImpl->releaseBottomNode(*I);
790 releaseSuccessors(&EntrySU);
791 releasePredecessors(&ExitSU);
793 SchedImpl->registerRoots();
795 // Advance past initial DebugValues.
796 CurrentTop = nextIfDebug(RegionBegin, RegionEnd);
797 CurrentBottom = RegionEnd;
800 /// Update scheduler queues after scheduling an instruction.
801 void ScheduleDAGMI::updateQueues(SUnit *SU, bool IsTopNode) {
802 // Release dependent instructions for scheduling.
804 releaseSuccessors(SU);
806 releasePredecessors(SU);
808 SU->isScheduled = true;
811 /// Reinsert any remaining debug_values, just like the PostRA scheduler.
812 void ScheduleDAGMI::placeDebugValues() {
813 // If first instruction was a DBG_VALUE then put it back.
815 BB->splice(RegionBegin, BB, FirstDbgValue);
816 RegionBegin = FirstDbgValue;
819 for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
820 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
821 std::pair<MachineInstr *, MachineInstr *> P = *std::prev(DI);
822 MachineInstr *DbgValue = P.first;
823 MachineBasicBlock::iterator OrigPrevMI = P.second;
824 if (&*RegionBegin == DbgValue)
826 BB->splice(++OrigPrevMI, BB, DbgValue);
827 if (OrigPrevMI == std::prev(RegionEnd))
828 RegionEnd = DbgValue;
831 FirstDbgValue = nullptr;
834 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
835 void ScheduleDAGMI::dumpSchedule() const {
836 for (MachineBasicBlock::iterator MI = begin(), ME = end(); MI != ME; ++MI) {
837 if (SUnit *SU = getSUnit(&(*MI)))
840 dbgs() << "Missing SUnit\n";
845 //===----------------------------------------------------------------------===//
846 // ScheduleDAGMILive - Base class for MachineInstr scheduling with LiveIntervals
848 //===----------------------------------------------------------------------===//
850 ScheduleDAGMILive::~ScheduleDAGMILive() {
854 /// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
855 /// crossing a scheduling boundary. [begin, end) includes all instructions in
856 /// the region, including the boundary itself and single-instruction regions
857 /// that don't get scheduled.
858 void ScheduleDAGMILive::enterRegion(MachineBasicBlock *bb,
859 MachineBasicBlock::iterator begin,
860 MachineBasicBlock::iterator end,
861 unsigned regioninstrs)
863 // ScheduleDAGMI initializes SchedImpl's per-region policy.
864 ScheduleDAGMI::enterRegion(bb, begin, end, regioninstrs);
866 // For convenience remember the end of the liveness region.
867 LiveRegionEnd = (RegionEnd == bb->end()) ? RegionEnd : std::next(RegionEnd);
869 SUPressureDiffs.clear();
871 ShouldTrackPressure = SchedImpl->shouldTrackPressure();
874 // Setup the register pressure trackers for the top scheduled top and bottom
875 // scheduled regions.
876 void ScheduleDAGMILive::initRegPressure() {
877 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin);
878 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
880 // Close the RPTracker to finalize live ins.
881 RPTracker.closeRegion();
883 DEBUG(RPTracker.dump());
885 // Initialize the live ins and live outs.
886 TopRPTracker.addLiveRegs(RPTracker.getPressure().LiveInRegs);
887 BotRPTracker.addLiveRegs(RPTracker.getPressure().LiveOutRegs);
889 // Close one end of the tracker so we can call
890 // getMaxUpward/DownwardPressureDelta before advancing across any
891 // instructions. This converts currently live regs into live ins/outs.
892 TopRPTracker.closeTop();
893 BotRPTracker.closeBottom();
895 BotRPTracker.initLiveThru(RPTracker);
896 if (!BotRPTracker.getLiveThru().empty()) {
897 TopRPTracker.initLiveThru(BotRPTracker.getLiveThru());
898 DEBUG(dbgs() << "Live Thru: ";
899 dumpRegSetPressure(BotRPTracker.getLiveThru(), TRI));
902 // For each live out vreg reduce the pressure change associated with other
903 // uses of the same vreg below the live-out reaching def.
904 updatePressureDiffs(RPTracker.getPressure().LiveOutRegs);
906 // Account for liveness generated by the region boundary.
907 if (LiveRegionEnd != RegionEnd) {
908 SmallVector<unsigned, 8> LiveUses;
909 BotRPTracker.recede(&LiveUses);
910 updatePressureDiffs(LiveUses);
913 assert(BotRPTracker.getPos() == RegionEnd && "Can't find the region bottom");
915 // Cache the list of excess pressure sets in this region. This will also track
916 // the max pressure in the scheduled code for these sets.
917 RegionCriticalPSets.clear();
918 const std::vector<unsigned> &RegionPressure =
919 RPTracker.getPressure().MaxSetPressure;
920 for (unsigned i = 0, e = RegionPressure.size(); i < e; ++i) {
921 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i);
922 if (RegionPressure[i] > Limit) {
923 DEBUG(dbgs() << TRI->getRegPressureSetName(i)
924 << " Limit " << Limit
925 << " Actual " << RegionPressure[i] << "\n");
926 RegionCriticalPSets.push_back(PressureChange(i));
929 DEBUG(dbgs() << "Excess PSets: ";
930 for (unsigned i = 0, e = RegionCriticalPSets.size(); i != e; ++i)
931 dbgs() << TRI->getRegPressureSetName(
932 RegionCriticalPSets[i].getPSet()) << " ";
936 void ScheduleDAGMILive::
937 updateScheduledPressure(const SUnit *SU,
938 const std::vector<unsigned> &NewMaxPressure) {
939 const PressureDiff &PDiff = getPressureDiff(SU);
940 unsigned CritIdx = 0, CritEnd = RegionCriticalPSets.size();
941 for (PressureDiff::const_iterator I = PDiff.begin(), E = PDiff.end();
945 unsigned ID = I->getPSet();
946 while (CritIdx != CritEnd && RegionCriticalPSets[CritIdx].getPSet() < ID)
948 if (CritIdx != CritEnd && RegionCriticalPSets[CritIdx].getPSet() == ID) {
949 if ((int)NewMaxPressure[ID] > RegionCriticalPSets[CritIdx].getUnitInc()
950 && NewMaxPressure[ID] <= INT16_MAX)
951 RegionCriticalPSets[CritIdx].setUnitInc(NewMaxPressure[ID]);
953 unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID);
954 if (NewMaxPressure[ID] >= Limit - 2) {
955 DEBUG(dbgs() << " " << TRI->getRegPressureSetName(ID) << ": "
956 << NewMaxPressure[ID]
957 << ((NewMaxPressure[ID] > Limit) ? " > " : " <= ") << Limit
958 << "(+ " << BotRPTracker.getLiveThru()[ID] << " livethru)\n");
963 /// Update the PressureDiff array for liveness after scheduling this
965 void ScheduleDAGMILive::updatePressureDiffs(ArrayRef<unsigned> LiveUses) {
966 for (unsigned LUIdx = 0, LUEnd = LiveUses.size(); LUIdx != LUEnd; ++LUIdx) {
967 /// FIXME: Currently assuming single-use physregs.
968 unsigned Reg = LiveUses[LUIdx];
969 DEBUG(dbgs() << " LiveReg: " << PrintVRegOrUnit(Reg, TRI) << "\n");
970 if (!TRI->isVirtualRegister(Reg))
973 // This may be called before CurrentBottom has been initialized. However,
974 // BotRPTracker must have a valid position. We want the value live into the
975 // instruction or live out of the block, so ask for the previous
976 // instruction's live-out.
977 const LiveInterval &LI = LIS->getInterval(Reg);
979 MachineBasicBlock::const_iterator I =
980 nextIfDebug(BotRPTracker.getPos(), BB->end());
982 VNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
984 LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(I));
987 // RegisterPressureTracker guarantees that readsReg is true for LiveUses.
988 assert(VNI && "No live value at use.");
989 for (const VReg2SUnit &V2SU
990 : make_range(VRegUses.find(Reg), VRegUses.end())) {
992 DEBUG(dbgs() << " UpdateRegP: SU(" << SU->NodeNum << ") "
994 // If this use comes before the reaching def, it cannot be a last use, so
995 // descrease its pressure change.
996 if (!SU->isScheduled && SU != &ExitSU) {
998 = LI.Query(LIS->getInstructionIndex(SU->getInstr()));
999 if (LRQ.valueIn() == VNI)
1000 getPressureDiff(SU).addPressureChange(Reg, true, &MRI);
1006 /// schedule - Called back from MachineScheduler::runOnMachineFunction
1007 /// after setting up the current scheduling region. [RegionBegin, RegionEnd)
1008 /// only includes instructions that have DAG nodes, not scheduling boundaries.
1010 /// This is a skeletal driver, with all the functionality pushed into helpers,
1011 /// so that it can be easily extended by experimental schedulers. Generally,
1012 /// implementing MachineSchedStrategy should be sufficient to implement a new
1013 /// scheduling algorithm. However, if a scheduler further subclasses
1014 /// ScheduleDAGMILive then it will want to override this virtual method in order
1015 /// to update any specialized state.
1016 void ScheduleDAGMILive::schedule() {
1017 DEBUG(dbgs() << "ScheduleDAGMILive::schedule starting\n");
1018 DEBUG(SchedImpl->dumpPolicy());
1019 buildDAGWithRegPressure();
1021 Topo.InitDAGTopologicalSorting();
1025 SmallVector<SUnit*, 8> TopRoots, BotRoots;
1026 findRootsAndBiasEdges(TopRoots, BotRoots);
1028 // Initialize the strategy before modifying the DAG.
1029 // This may initialize a DFSResult to be used for queue priority.
1030 SchedImpl->initialize(this);
1032 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
1033 SUnits[su].dumpAll(this));
1034 if (ViewMISchedDAGs) viewGraph();
1036 // Initialize ready queues now that the DAG and priority data are finalized.
1037 initQueues(TopRoots, BotRoots);
1039 if (ShouldTrackPressure) {
1040 assert(TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker");
1041 TopRPTracker.setPos(CurrentTop);
1044 bool IsTopNode = false;
1046 DEBUG(dbgs() << "** ScheduleDAGMILive::schedule picking next node\n");
1047 SUnit *SU = SchedImpl->pickNode(IsTopNode);
1050 assert(!SU->isScheduled && "Node already scheduled");
1051 if (!checkSchedLimit())
1054 scheduleMI(SU, IsTopNode);
1057 unsigned SubtreeID = DFSResult->getSubtreeID(SU);
1058 if (!ScheduledTrees.test(SubtreeID)) {
1059 ScheduledTrees.set(SubtreeID);
1060 DFSResult->scheduleTree(SubtreeID);
1061 SchedImpl->scheduleTree(SubtreeID);
1065 // Notify the scheduling strategy after updating the DAG.
1066 SchedImpl->schedNode(SU, IsTopNode);
1068 updateQueues(SU, IsTopNode);
1070 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
1075 unsigned BBNum = begin()->getParent()->getNumber();
1076 dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
1082 /// Build the DAG and setup three register pressure trackers.
1083 void ScheduleDAGMILive::buildDAGWithRegPressure() {
1084 if (!ShouldTrackPressure) {
1086 RegionCriticalPSets.clear();
1087 buildSchedGraph(AA);
1091 // Initialize the register pressure tracker used by buildSchedGraph.
1092 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd,
1093 /*TrackUntiedDefs=*/true);
1095 // Account for liveness generate by the region boundary.
1096 if (LiveRegionEnd != RegionEnd)
1099 // Build the DAG, and compute current register pressure.
1100 buildSchedGraph(AA, &RPTracker, &SUPressureDiffs);
1102 // Initialize top/bottom trackers after computing region pressure.
1106 void ScheduleDAGMILive::computeDFSResult() {
1108 DFSResult = new SchedDFSResult(/*BottomU*/true, MinSubtreeSize);
1110 ScheduledTrees.clear();
1111 DFSResult->resize(SUnits.size());
1112 DFSResult->compute(SUnits);
1113 ScheduledTrees.resize(DFSResult->getNumSubtrees());
1116 /// Compute the max cyclic critical path through the DAG. The scheduling DAG
1117 /// only provides the critical path for single block loops. To handle loops that
1118 /// span blocks, we could use the vreg path latencies provided by
1119 /// MachineTraceMetrics instead. However, MachineTraceMetrics is not currently
1120 /// available for use in the scheduler.
1122 /// The cyclic path estimation identifies a def-use pair that crosses the back
1123 /// edge and considers the depth and height of the nodes. For example, consider
1124 /// the following instruction sequence where each instruction has unit latency
1125 /// and defines an epomymous virtual register:
1127 /// a->b(a,c)->c(b)->d(c)->exit
1129 /// The cyclic critical path is a two cycles: b->c->b
1130 /// The acyclic critical path is four cycles: a->b->c->d->exit
1131 /// LiveOutHeight = height(c) = len(c->d->exit) = 2
1132 /// LiveOutDepth = depth(c) + 1 = len(a->b->c) + 1 = 3
1133 /// LiveInHeight = height(b) + 1 = len(b->c->d->exit) + 1 = 4
1134 /// LiveInDepth = depth(b) = len(a->b) = 1
1136 /// LiveOutDepth - LiveInDepth = 3 - 1 = 2
1137 /// LiveInHeight - LiveOutHeight = 4 - 2 = 2
1138 /// CyclicCriticalPath = min(2, 2) = 2
1140 /// This could be relevant to PostRA scheduling, but is currently implemented
1141 /// assuming LiveIntervals.
1142 unsigned ScheduleDAGMILive::computeCyclicCriticalPath() {
1143 // This only applies to single block loop.
1144 if (!BB->isSuccessor(BB))
1147 unsigned MaxCyclicLatency = 0;
1148 // Visit each live out vreg def to find def/use pairs that cross iterations.
1149 ArrayRef<unsigned> LiveOuts = RPTracker.getPressure().LiveOutRegs;
1150 for (ArrayRef<unsigned>::iterator RI = LiveOuts.begin(), RE = LiveOuts.end();
1153 if (!TRI->isVirtualRegister(Reg))
1155 const LiveInterval &LI = LIS->getInterval(Reg);
1156 const VNInfo *DefVNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
1160 MachineInstr *DefMI = LIS->getInstructionFromIndex(DefVNI->def);
1161 const SUnit *DefSU = getSUnit(DefMI);
1165 unsigned LiveOutHeight = DefSU->getHeight();
1166 unsigned LiveOutDepth = DefSU->getDepth() + DefSU->Latency;
1167 // Visit all local users of the vreg def.
1168 for (const VReg2SUnit &V2SU
1169 : make_range(VRegUses.find(Reg), VRegUses.end())) {
1170 SUnit *SU = V2SU.SU;
1174 // Only consider uses of the phi.
1175 LiveQueryResult LRQ =
1176 LI.Query(LIS->getInstructionIndex(SU->getInstr()));
1177 if (!LRQ.valueIn()->isPHIDef())
1180 // Assume that a path spanning two iterations is a cycle, which could
1181 // overestimate in strange cases. This allows cyclic latency to be
1182 // estimated as the minimum slack of the vreg's depth or height.
1183 unsigned CyclicLatency = 0;
1184 if (LiveOutDepth > SU->getDepth())
1185 CyclicLatency = LiveOutDepth - SU->getDepth();
1187 unsigned LiveInHeight = SU->getHeight() + DefSU->Latency;
1188 if (LiveInHeight > LiveOutHeight) {
1189 if (LiveInHeight - LiveOutHeight < CyclicLatency)
1190 CyclicLatency = LiveInHeight - LiveOutHeight;
1195 DEBUG(dbgs() << "Cyclic Path: SU(" << DefSU->NodeNum << ") -> SU("
1196 << SU->NodeNum << ") = " << CyclicLatency << "c\n");
1197 if (CyclicLatency > MaxCyclicLatency)
1198 MaxCyclicLatency = CyclicLatency;
1201 DEBUG(dbgs() << "Cyclic Critical Path: " << MaxCyclicLatency << "c\n");
1202 return MaxCyclicLatency;
1205 /// Move an instruction and update register pressure.
1206 void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) {
1207 // Move the instruction to its new location in the instruction stream.
1208 MachineInstr *MI = SU->getInstr();
1211 assert(SU->isTopReady() && "node still has unscheduled dependencies");
1212 if (&*CurrentTop == MI)
1213 CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);
1215 moveInstruction(MI, CurrentTop);
1216 TopRPTracker.setPos(MI);
1219 if (ShouldTrackPressure) {
1220 // Update top scheduled pressure.
1221 TopRPTracker.advance();
1222 assert(TopRPTracker.getPos() == CurrentTop && "out of sync");
1223 updateScheduledPressure(SU, TopRPTracker.getPressure().MaxSetPressure);
1227 assert(SU->isBottomReady() && "node still has unscheduled dependencies");
1228 MachineBasicBlock::iterator priorII =
1229 priorNonDebug(CurrentBottom, CurrentTop);
1230 if (&*priorII == MI)
1231 CurrentBottom = priorII;
1233 if (&*CurrentTop == MI) {
1234 CurrentTop = nextIfDebug(++CurrentTop, priorII);
1235 TopRPTracker.setPos(CurrentTop);
1237 moveInstruction(MI, CurrentBottom);
1240 if (ShouldTrackPressure) {
1241 // Update bottom scheduled pressure.
1242 SmallVector<unsigned, 8> LiveUses;
1243 BotRPTracker.recede(&LiveUses);
1244 assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
1245 updateScheduledPressure(SU, BotRPTracker.getPressure().MaxSetPressure);
1246 updatePressureDiffs(LiveUses);
1251 //===----------------------------------------------------------------------===//
1252 // LoadClusterMutation - DAG post-processing to cluster loads.
1253 //===----------------------------------------------------------------------===//
1256 /// \brief Post-process the DAG to create cluster edges between neighboring
1258 class LoadClusterMutation : public ScheduleDAGMutation {
1263 LoadInfo(SUnit *su, unsigned reg, unsigned ofs)
1264 : SU(su), BaseReg(reg), Offset(ofs) {}
1266 bool operator<(const LoadInfo &RHS) const {
1267 return std::tie(BaseReg, Offset) < std::tie(RHS.BaseReg, RHS.Offset);
1271 const TargetInstrInfo *TII;
1272 const TargetRegisterInfo *TRI;
1274 LoadClusterMutation(const TargetInstrInfo *tii,
1275 const TargetRegisterInfo *tri)
1276 : TII(tii), TRI(tri) {}
1278 void apply(ScheduleDAGMI *DAG) override;
1280 void clusterNeighboringLoads(ArrayRef<SUnit*> Loads, ScheduleDAGMI *DAG);
1284 void LoadClusterMutation::clusterNeighboringLoads(ArrayRef<SUnit*> Loads,
1285 ScheduleDAGMI *DAG) {
1286 SmallVector<LoadClusterMutation::LoadInfo,32> LoadRecords;
1287 for (unsigned Idx = 0, End = Loads.size(); Idx != End; ++Idx) {
1288 SUnit *SU = Loads[Idx];
1291 if (TII->getMemOpBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
1292 LoadRecords.push_back(LoadInfo(SU, BaseReg, Offset));
1294 if (LoadRecords.size() < 2)
1296 std::sort(LoadRecords.begin(), LoadRecords.end());
1297 unsigned ClusterLength = 1;
1298 for (unsigned Idx = 0, End = LoadRecords.size(); Idx < (End - 1); ++Idx) {
1299 if (LoadRecords[Idx].BaseReg != LoadRecords[Idx+1].BaseReg) {
1304 SUnit *SUa = LoadRecords[Idx].SU;
1305 SUnit *SUb = LoadRecords[Idx+1].SU;
1306 if (TII->shouldClusterLoads(SUa->getInstr(), SUb->getInstr(), ClusterLength)
1307 && DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
1309 DEBUG(dbgs() << "Cluster loads SU(" << SUa->NodeNum << ") - SU("
1310 << SUb->NodeNum << ")\n");
1311 // Copy successor edges from SUa to SUb. Interleaving computation
1312 // dependent on SUa can prevent load combining due to register reuse.
1313 // Predecessor edges do not need to be copied from SUb to SUa since nearby
1314 // loads should have effectively the same inputs.
1315 for (SUnit::const_succ_iterator
1316 SI = SUa->Succs.begin(), SE = SUa->Succs.end(); SI != SE; ++SI) {
1317 if (SI->getSUnit() == SUb)
1319 DEBUG(dbgs() << " Copy Succ SU(" << SI->getSUnit()->NodeNum << ")\n");
1320 DAG->addEdge(SI->getSUnit(), SDep(SUb, SDep::Artificial));
1329 /// \brief Callback from DAG postProcessing to create cluster edges for loads.
1330 void LoadClusterMutation::apply(ScheduleDAGMI *DAG) {
1331 // Map DAG NodeNum to store chain ID.
1332 DenseMap<unsigned, unsigned> StoreChainIDs;
1333 // Map each store chain to a set of dependent loads.
1334 SmallVector<SmallVector<SUnit*,4>, 32> StoreChainDependents;
1335 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
1336 SUnit *SU = &DAG->SUnits[Idx];
1337 if (!SU->getInstr()->mayLoad())
1339 unsigned ChainPredID = DAG->SUnits.size();
1340 for (SUnit::const_pred_iterator
1341 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) {
1343 ChainPredID = PI->getSUnit()->NodeNum;
1347 // Check if this chain-like pred has been seen
1348 // before. ChainPredID==MaxNodeID for loads at the top of the schedule.
1349 unsigned NumChains = StoreChainDependents.size();
1350 std::pair<DenseMap<unsigned, unsigned>::iterator, bool> Result =
1351 StoreChainIDs.insert(std::make_pair(ChainPredID, NumChains));
1353 StoreChainDependents.resize(NumChains + 1);
1354 StoreChainDependents[Result.first->second].push_back(SU);
1356 // Iterate over the store chains.
1357 for (unsigned Idx = 0, End = StoreChainDependents.size(); Idx != End; ++Idx)
1358 clusterNeighboringLoads(StoreChainDependents[Idx], DAG);
1361 //===----------------------------------------------------------------------===//
1362 // MacroFusion - DAG post-processing to encourage fusion of macro ops.
1363 //===----------------------------------------------------------------------===//
1366 /// \brief Post-process the DAG to create cluster edges between instructions
1367 /// that may be fused by the processor into a single operation.
1368 class MacroFusion : public ScheduleDAGMutation {
1369 const TargetInstrInfo &TII;
1370 const TargetRegisterInfo &TRI;
1372 MacroFusion(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI)
1373 : TII(TII), TRI(TRI) {}
1375 void apply(ScheduleDAGMI *DAG) override;
1379 /// Returns true if \p MI reads a register written by \p Other.
1380 static bool HasDataDep(const TargetRegisterInfo &TRI, const MachineInstr &MI,
1381 const MachineInstr &Other) {
1382 for (const MachineOperand &MO : MI.uses()) {
1383 if (!MO.isReg() || !MO.readsReg())
1386 unsigned Reg = MO.getReg();
1387 if (Other.modifiesRegister(Reg, &TRI))
1393 /// \brief Callback from DAG postProcessing to create cluster edges to encourage
1394 /// fused operations.
1395 void MacroFusion::apply(ScheduleDAGMI *DAG) {
1396 // For now, assume targets can only fuse with the branch.
1397 SUnit &ExitSU = DAG->ExitSU;
1398 MachineInstr *Branch = ExitSU.getInstr();
1402 for (SUnit &SU : DAG->SUnits) {
1403 // SUnits with successors can't be schedule in front of the ExitSU.
1404 if (!SU.Succs.empty())
1406 // We only care if the node writes to a register that the branch reads.
1407 MachineInstr *Pred = SU.getInstr();
1408 if (!HasDataDep(TRI, *Branch, *Pred))
1411 if (!TII.shouldScheduleAdjacent(Pred, Branch))
1414 // Create a single weak edge from SU to ExitSU. The only effect is to cause
1415 // bottom-up scheduling to heavily prioritize the clustered SU. There is no
1416 // need to copy predecessor edges from ExitSU to SU, since top-down
1417 // scheduling cannot prioritize ExitSU anyway. To defer top-down scheduling
1418 // of SU, we could create an artificial edge from the deepest root, but it
1419 // hasn't been needed yet.
1420 bool Success = DAG->addEdge(&ExitSU, SDep(&SU, SDep::Cluster));
1422 assert(Success && "No DAG nodes should be reachable from ExitSU");
1424 DEBUG(dbgs() << "Macro Fuse SU(" << SU.NodeNum << ")\n");
1429 //===----------------------------------------------------------------------===//
1430 // CopyConstrain - DAG post-processing to encourage copy elimination.
1431 //===----------------------------------------------------------------------===//
1434 /// \brief Post-process the DAG to create weak edges from all uses of a copy to
1435 /// the one use that defines the copy's source vreg, most likely an induction
1436 /// variable increment.
1437 class CopyConstrain : public ScheduleDAGMutation {
1439 SlotIndex RegionBeginIdx;
1440 // RegionEndIdx is the slot index of the last non-debug instruction in the
1441 // scheduling region. So we may have RegionBeginIdx == RegionEndIdx.
1442 SlotIndex RegionEndIdx;
1444 CopyConstrain(const TargetInstrInfo *, const TargetRegisterInfo *) {}
1446 void apply(ScheduleDAGMI *DAG) override;
1449 void constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG);
1453 /// constrainLocalCopy handles two possibilities:
1458 /// I3: dst = src (copy)
1459 /// (create pred->succ edges I0->I1, I2->I1)
1462 /// I0: dst = src (copy)
1466 /// (create pred->succ edges I1->I2, I3->I2)
1468 /// Although the MachineScheduler is currently constrained to single blocks,
1469 /// this algorithm should handle extended blocks. An EBB is a set of
1470 /// contiguously numbered blocks such that the previous block in the EBB is
1471 /// always the single predecessor.
1472 void CopyConstrain::constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG) {
1473 LiveIntervals *LIS = DAG->getLIS();
1474 MachineInstr *Copy = CopySU->getInstr();
1476 // Check for pure vreg copies.
1477 unsigned SrcReg = Copy->getOperand(1).getReg();
1478 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
1481 unsigned DstReg = Copy->getOperand(0).getReg();
1482 if (!TargetRegisterInfo::isVirtualRegister(DstReg))
1485 // Check if either the dest or source is local. If it's live across a back
1486 // edge, it's not local. Note that if both vregs are live across the back
1487 // edge, we cannot successfully contrain the copy without cyclic scheduling.
1488 // If both the copy's source and dest are local live intervals, then we
1489 // should treat the dest as the global for the purpose of adding
1490 // constraints. This adds edges from source's other uses to the copy.
1491 unsigned LocalReg = SrcReg;
1492 unsigned GlobalReg = DstReg;
1493 LiveInterval *LocalLI = &LIS->getInterval(LocalReg);
1494 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx)) {
1497 LocalLI = &LIS->getInterval(LocalReg);
1498 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx))
1501 LiveInterval *GlobalLI = &LIS->getInterval(GlobalReg);
1503 // Find the global segment after the start of the local LI.
1504 LiveInterval::iterator GlobalSegment = GlobalLI->find(LocalLI->beginIndex());
1505 // If GlobalLI does not overlap LocalLI->start, then a copy directly feeds a
1506 // local live range. We could create edges from other global uses to the local
1507 // start, but the coalescer should have already eliminated these cases, so
1508 // don't bother dealing with it.
1509 if (GlobalSegment == GlobalLI->end())
1512 // If GlobalSegment is killed at the LocalLI->start, the call to find()
1513 // returned the next global segment. But if GlobalSegment overlaps with
1514 // LocalLI->start, then advance to the next segement. If a hole in GlobalLI
1515 // exists in LocalLI's vicinity, GlobalSegment will be the end of the hole.
1516 if (GlobalSegment->contains(LocalLI->beginIndex()))
1519 if (GlobalSegment == GlobalLI->end())
1522 // Check if GlobalLI contains a hole in the vicinity of LocalLI.
1523 if (GlobalSegment != GlobalLI->begin()) {
1524 // Two address defs have no hole.
1525 if (SlotIndex::isSameInstr(std::prev(GlobalSegment)->end,
1526 GlobalSegment->start)) {
1529 // If the prior global segment may be defined by the same two-address
1530 // instruction that also defines LocalLI, then can't make a hole here.
1531 if (SlotIndex::isSameInstr(std::prev(GlobalSegment)->start,
1532 LocalLI->beginIndex())) {
1535 // If GlobalLI has a prior segment, it must be live into the EBB. Otherwise
1536 // it would be a disconnected component in the live range.
1537 assert(std::prev(GlobalSegment)->start < LocalLI->beginIndex() &&
1538 "Disconnected LRG within the scheduling region.");
1540 MachineInstr *GlobalDef = LIS->getInstructionFromIndex(GlobalSegment->start);
1544 SUnit *GlobalSU = DAG->getSUnit(GlobalDef);
1548 // GlobalDef is the bottom of the GlobalLI hole. Open the hole by
1549 // constraining the uses of the last local def to precede GlobalDef.
1550 SmallVector<SUnit*,8> LocalUses;
1551 const VNInfo *LastLocalVN = LocalLI->getVNInfoBefore(LocalLI->endIndex());
1552 MachineInstr *LastLocalDef = LIS->getInstructionFromIndex(LastLocalVN->def);
1553 SUnit *LastLocalSU = DAG->getSUnit(LastLocalDef);
1554 for (SUnit::const_succ_iterator
1555 I = LastLocalSU->Succs.begin(), E = LastLocalSU->Succs.end();
1557 if (I->getKind() != SDep::Data || I->getReg() != LocalReg)
1559 if (I->getSUnit() == GlobalSU)
1561 if (!DAG->canAddEdge(GlobalSU, I->getSUnit()))
1563 LocalUses.push_back(I->getSUnit());
1565 // Open the top of the GlobalLI hole by constraining any earlier global uses
1566 // to precede the start of LocalLI.
1567 SmallVector<SUnit*,8> GlobalUses;
1568 MachineInstr *FirstLocalDef =
1569 LIS->getInstructionFromIndex(LocalLI->beginIndex());
1570 SUnit *FirstLocalSU = DAG->getSUnit(FirstLocalDef);
1571 for (SUnit::const_pred_iterator
1572 I = GlobalSU->Preds.begin(), E = GlobalSU->Preds.end(); I != E; ++I) {
1573 if (I->getKind() != SDep::Anti || I->getReg() != GlobalReg)
1575 if (I->getSUnit() == FirstLocalSU)
1577 if (!DAG->canAddEdge(FirstLocalSU, I->getSUnit()))
1579 GlobalUses.push_back(I->getSUnit());
1581 DEBUG(dbgs() << "Constraining copy SU(" << CopySU->NodeNum << ")\n");
1582 // Add the weak edges.
1583 for (SmallVectorImpl<SUnit*>::const_iterator
1584 I = LocalUses.begin(), E = LocalUses.end(); I != E; ++I) {
1585 DEBUG(dbgs() << " Local use SU(" << (*I)->NodeNum << ") -> SU("
1586 << GlobalSU->NodeNum << ")\n");
1587 DAG->addEdge(GlobalSU, SDep(*I, SDep::Weak));
1589 for (SmallVectorImpl<SUnit*>::const_iterator
1590 I = GlobalUses.begin(), E = GlobalUses.end(); I != E; ++I) {
1591 DEBUG(dbgs() << " Global use SU(" << (*I)->NodeNum << ") -> SU("
1592 << FirstLocalSU->NodeNum << ")\n");
1593 DAG->addEdge(FirstLocalSU, SDep(*I, SDep::Weak));
1597 /// \brief Callback from DAG postProcessing to create weak edges to encourage
1598 /// copy elimination.
1599 void CopyConstrain::apply(ScheduleDAGMI *DAG) {
1600 assert(DAG->hasVRegLiveness() && "Expect VRegs with LiveIntervals");
1602 MachineBasicBlock::iterator FirstPos = nextIfDebug(DAG->begin(), DAG->end());
1603 if (FirstPos == DAG->end())
1605 RegionBeginIdx = DAG->getLIS()->getInstructionIndex(&*FirstPos);
1606 RegionEndIdx = DAG->getLIS()->getInstructionIndex(
1607 &*priorNonDebug(DAG->end(), DAG->begin()));
1609 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
1610 SUnit *SU = &DAG->SUnits[Idx];
1611 if (!SU->getInstr()->isCopy())
1614 constrainLocalCopy(SU, static_cast<ScheduleDAGMILive*>(DAG));
1618 //===----------------------------------------------------------------------===//
1619 // MachineSchedStrategy helpers used by GenericScheduler, GenericPostScheduler
1620 // and possibly other custom schedulers.
1621 //===----------------------------------------------------------------------===//
1623 static const unsigned InvalidCycle = ~0U;
1625 SchedBoundary::~SchedBoundary() { delete HazardRec; }
1627 void SchedBoundary::reset() {
1628 // A new HazardRec is created for each DAG and owned by SchedBoundary.
1629 // Destroying and reconstructing it is very expensive though. So keep
1630 // invalid, placeholder HazardRecs.
1631 if (HazardRec && HazardRec->isEnabled()) {
1633 HazardRec = nullptr;
1637 CheckPending = false;
1641 MinReadyCycle = UINT_MAX;
1642 ExpectedLatency = 0;
1643 DependentLatency = 0;
1645 MaxExecutedResCount = 0;
1647 IsResourceLimited = false;
1648 ReservedCycles.clear();
1650 // Track the maximum number of stall cycles that could arise either from the
1651 // latency of a DAG edge or the number of cycles that a processor resource is
1652 // reserved (SchedBoundary::ReservedCycles).
1653 MaxObservedStall = 0;
1655 // Reserve a zero-count for invalid CritResIdx.
1656 ExecutedResCounts.resize(1);
1657 assert(!ExecutedResCounts[0] && "nonzero count for bad resource");
1660 void SchedRemainder::
1661 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) {
1663 if (!SchedModel->hasInstrSchedModel())
1665 RemainingCounts.resize(SchedModel->getNumProcResourceKinds());
1666 for (std::vector<SUnit>::iterator
1667 I = DAG->SUnits.begin(), E = DAG->SUnits.end(); I != E; ++I) {
1668 const MCSchedClassDesc *SC = DAG->getSchedClass(&*I);
1669 RemIssueCount += SchedModel->getNumMicroOps(I->getInstr(), SC)
1670 * SchedModel->getMicroOpFactor();
1671 for (TargetSchedModel::ProcResIter
1672 PI = SchedModel->getWriteProcResBegin(SC),
1673 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1674 unsigned PIdx = PI->ProcResourceIdx;
1675 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1676 RemainingCounts[PIdx] += (Factor * PI->Cycles);
1681 void SchedBoundary::
1682 init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem) {
1685 SchedModel = smodel;
1687 if (SchedModel->hasInstrSchedModel()) {
1688 ExecutedResCounts.resize(SchedModel->getNumProcResourceKinds());
1689 ReservedCycles.resize(SchedModel->getNumProcResourceKinds(), InvalidCycle);
1693 /// Compute the stall cycles based on this SUnit's ready time. Heuristics treat
1694 /// these "soft stalls" differently than the hard stall cycles based on CPU
1695 /// resources and computed by checkHazard(). A fully in-order model
1696 /// (MicroOpBufferSize==0) will not make use of this since instructions are not
1697 /// available for scheduling until they are ready. However, a weaker in-order
1698 /// model may use this for heuristics. For example, if a processor has in-order
1699 /// behavior when reading certain resources, this may come into play.
1700 unsigned SchedBoundary::getLatencyStallCycles(SUnit *SU) {
1701 if (!SU->isUnbuffered)
1704 unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle);
1705 if (ReadyCycle > CurrCycle)
1706 return ReadyCycle - CurrCycle;
1710 /// Compute the next cycle at which the given processor resource can be
1712 unsigned SchedBoundary::
1713 getNextResourceCycle(unsigned PIdx, unsigned Cycles) {
1714 unsigned NextUnreserved = ReservedCycles[PIdx];
1715 // If this resource has never been used, always return cycle zero.
1716 if (NextUnreserved == InvalidCycle)
1718 // For bottom-up scheduling add the cycles needed for the current operation.
1720 NextUnreserved += Cycles;
1721 return NextUnreserved;
1724 /// Does this SU have a hazard within the current instruction group.
1726 /// The scheduler supports two modes of hazard recognition. The first is the
1727 /// ScheduleHazardRecognizer API. It is a fully general hazard recognizer that
1728 /// supports highly complicated in-order reservation tables
1729 /// (ScoreboardHazardRecognizer) and arbitraty target-specific logic.
1731 /// The second is a streamlined mechanism that checks for hazards based on
1732 /// simple counters that the scheduler itself maintains. It explicitly checks
1733 /// for instruction dispatch limitations, including the number of micro-ops that
1734 /// can dispatch per cycle.
1736 /// TODO: Also check whether the SU must start a new group.
1737 bool SchedBoundary::checkHazard(SUnit *SU) {
1738 if (HazardRec->isEnabled()
1739 && HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard) {
1742 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
1743 if ((CurrMOps > 0) && (CurrMOps + uops > SchedModel->getIssueWidth())) {
1744 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") uops="
1745 << SchedModel->getNumMicroOps(SU->getInstr()) << '\n');
1748 if (SchedModel->hasInstrSchedModel() && SU->hasReservedResource) {
1749 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
1750 for (TargetSchedModel::ProcResIter
1751 PI = SchedModel->getWriteProcResBegin(SC),
1752 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1753 unsigned NRCycle = getNextResourceCycle(PI->ProcResourceIdx, PI->Cycles);
1754 if (NRCycle > CurrCycle) {
1756 MaxObservedStall = std::max(PI->Cycles, MaxObservedStall);
1758 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") "
1759 << SchedModel->getResourceName(PI->ProcResourceIdx)
1760 << "=" << NRCycle << "c\n");
1768 // Find the unscheduled node in ReadySUs with the highest latency.
1769 unsigned SchedBoundary::
1770 findMaxLatency(ArrayRef<SUnit*> ReadySUs) {
1771 SUnit *LateSU = nullptr;
1772 unsigned RemLatency = 0;
1773 for (ArrayRef<SUnit*>::iterator I = ReadySUs.begin(), E = ReadySUs.end();
1775 unsigned L = getUnscheduledLatency(*I);
1776 if (L > RemLatency) {
1782 DEBUG(dbgs() << Available.getName() << " RemLatency SU("
1783 << LateSU->NodeNum << ") " << RemLatency << "c\n");
1788 // Count resources in this zone and the remaining unscheduled
1789 // instruction. Return the max count, scaled. Set OtherCritIdx to the critical
1790 // resource index, or zero if the zone is issue limited.
1791 unsigned SchedBoundary::
1792 getOtherResourceCount(unsigned &OtherCritIdx) {
1794 if (!SchedModel->hasInstrSchedModel())
1797 unsigned OtherCritCount = Rem->RemIssueCount
1798 + (RetiredMOps * SchedModel->getMicroOpFactor());
1799 DEBUG(dbgs() << " " << Available.getName() << " + Remain MOps: "
1800 << OtherCritCount / SchedModel->getMicroOpFactor() << '\n');
1801 for (unsigned PIdx = 1, PEnd = SchedModel->getNumProcResourceKinds();
1802 PIdx != PEnd; ++PIdx) {
1803 unsigned OtherCount = getResourceCount(PIdx) + Rem->RemainingCounts[PIdx];
1804 if (OtherCount > OtherCritCount) {
1805 OtherCritCount = OtherCount;
1806 OtherCritIdx = PIdx;
1810 DEBUG(dbgs() << " " << Available.getName() << " + Remain CritRes: "
1811 << OtherCritCount / SchedModel->getResourceFactor(OtherCritIdx)
1812 << " " << SchedModel->getResourceName(OtherCritIdx) << "\n");
1814 return OtherCritCount;
1817 void SchedBoundary::releaseNode(SUnit *SU, unsigned ReadyCycle) {
1818 assert(SU->getInstr() && "Scheduled SUnit must have instr");
1821 // ReadyCycle was been bumped up to the CurrCycle when this node was
1822 // scheduled, but CurrCycle may have been eagerly advanced immediately after
1823 // scheduling, so may now be greater than ReadyCycle.
1824 if (ReadyCycle > CurrCycle)
1825 MaxObservedStall = std::max(ReadyCycle - CurrCycle, MaxObservedStall);
1828 if (ReadyCycle < MinReadyCycle)
1829 MinReadyCycle = ReadyCycle;
1831 // Check for interlocks first. For the purpose of other heuristics, an
1832 // instruction that cannot issue appears as if it's not in the ReadyQueue.
1833 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
1834 if ((!IsBuffered && ReadyCycle > CurrCycle) || checkHazard(SU))
1839 // Record this node as an immediate dependent of the scheduled node.
1843 void SchedBoundary::releaseTopNode(SUnit *SU) {
1844 if (SU->isScheduled)
1847 releaseNode(SU, SU->TopReadyCycle);
1850 void SchedBoundary::releaseBottomNode(SUnit *SU) {
1851 if (SU->isScheduled)
1854 releaseNode(SU, SU->BotReadyCycle);
1857 /// Move the boundary of scheduled code by one cycle.
1858 void SchedBoundary::bumpCycle(unsigned NextCycle) {
1859 if (SchedModel->getMicroOpBufferSize() == 0) {
1860 assert(MinReadyCycle < UINT_MAX && "MinReadyCycle uninitialized");
1861 if (MinReadyCycle > NextCycle)
1862 NextCycle = MinReadyCycle;
1864 // Update the current micro-ops, which will issue in the next cycle.
1865 unsigned DecMOps = SchedModel->getIssueWidth() * (NextCycle - CurrCycle);
1866 CurrMOps = (CurrMOps <= DecMOps) ? 0 : CurrMOps - DecMOps;
1868 // Decrement DependentLatency based on the next cycle.
1869 if ((NextCycle - CurrCycle) > DependentLatency)
1870 DependentLatency = 0;
1872 DependentLatency -= (NextCycle - CurrCycle);
1874 if (!HazardRec->isEnabled()) {
1875 // Bypass HazardRec virtual calls.
1876 CurrCycle = NextCycle;
1879 // Bypass getHazardType calls in case of long latency.
1880 for (; CurrCycle != NextCycle; ++CurrCycle) {
1882 HazardRec->AdvanceCycle();
1884 HazardRec->RecedeCycle();
1887 CheckPending = true;
1888 unsigned LFactor = SchedModel->getLatencyFactor();
1890 (int)(getCriticalCount() - (getScheduledLatency() * LFactor))
1893 DEBUG(dbgs() << "Cycle: " << CurrCycle << ' ' << Available.getName() << '\n');
1896 void SchedBoundary::incExecutedResources(unsigned PIdx, unsigned Count) {
1897 ExecutedResCounts[PIdx] += Count;
1898 if (ExecutedResCounts[PIdx] > MaxExecutedResCount)
1899 MaxExecutedResCount = ExecutedResCounts[PIdx];
1902 /// Add the given processor resource to this scheduled zone.
1904 /// \param Cycles indicates the number of consecutive (non-pipelined) cycles
1905 /// during which this resource is consumed.
1907 /// \return the next cycle at which the instruction may execute without
1908 /// oversubscribing resources.
1909 unsigned SchedBoundary::
1910 countResource(unsigned PIdx, unsigned Cycles, unsigned NextCycle) {
1911 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1912 unsigned Count = Factor * Cycles;
1913 DEBUG(dbgs() << " " << SchedModel->getResourceName(PIdx)
1914 << " +" << Cycles << "x" << Factor << "u\n");
1916 // Update Executed resources counts.
1917 incExecutedResources(PIdx, Count);
1918 assert(Rem->RemainingCounts[PIdx] >= Count && "resource double counted");
1919 Rem->RemainingCounts[PIdx] -= Count;
1921 // Check if this resource exceeds the current critical resource. If so, it
1922 // becomes the critical resource.
1923 if (ZoneCritResIdx != PIdx && (getResourceCount(PIdx) > getCriticalCount())) {
1924 ZoneCritResIdx = PIdx;
1925 DEBUG(dbgs() << " *** Critical resource "
1926 << SchedModel->getResourceName(PIdx) << ": "
1927 << getResourceCount(PIdx) / SchedModel->getLatencyFactor() << "c\n");
1929 // For reserved resources, record the highest cycle using the resource.
1930 unsigned NextAvailable = getNextResourceCycle(PIdx, Cycles);
1931 if (NextAvailable > CurrCycle) {
1932 DEBUG(dbgs() << " Resource conflict: "
1933 << SchedModel->getProcResource(PIdx)->Name << " reserved until @"
1934 << NextAvailable << "\n");
1936 return NextAvailable;
1939 /// Move the boundary of scheduled code by one SUnit.
1940 void SchedBoundary::bumpNode(SUnit *SU) {
1941 // Update the reservation table.
1942 if (HazardRec->isEnabled()) {
1943 if (!isTop() && SU->isCall) {
1944 // Calls are scheduled with their preceding instructions. For bottom-up
1945 // scheduling, clear the pipeline state before emitting.
1948 HazardRec->EmitInstruction(SU);
1950 // checkHazard should prevent scheduling multiple instructions per cycle that
1951 // exceed the issue width.
1952 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
1953 unsigned IncMOps = SchedModel->getNumMicroOps(SU->getInstr());
1955 (CurrMOps == 0 || (CurrMOps + IncMOps) <= SchedModel->getIssueWidth()) &&
1956 "Cannot schedule this instruction's MicroOps in the current cycle.");
1958 unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle);
1959 DEBUG(dbgs() << " Ready @" << ReadyCycle << "c\n");
1961 unsigned NextCycle = CurrCycle;
1962 switch (SchedModel->getMicroOpBufferSize()) {
1964 assert(ReadyCycle <= CurrCycle && "Broken PendingQueue");
1967 if (ReadyCycle > NextCycle) {
1968 NextCycle = ReadyCycle;
1969 DEBUG(dbgs() << " *** Stall until: " << ReadyCycle << "\n");
1973 // We don't currently model the OOO reorder buffer, so consider all
1974 // scheduled MOps to be "retired". We do loosely model in-order resource
1975 // latency. If this instruction uses an in-order resource, account for any
1976 // likely stall cycles.
1977 if (SU->isUnbuffered && ReadyCycle > NextCycle)
1978 NextCycle = ReadyCycle;
1981 RetiredMOps += IncMOps;
1983 // Update resource counts and critical resource.
1984 if (SchedModel->hasInstrSchedModel()) {
1985 unsigned DecRemIssue = IncMOps * SchedModel->getMicroOpFactor();
1986 assert(Rem->RemIssueCount >= DecRemIssue && "MOps double counted");
1987 Rem->RemIssueCount -= DecRemIssue;
1988 if (ZoneCritResIdx) {
1989 // Scale scheduled micro-ops for comparing with the critical resource.
1990 unsigned ScaledMOps =
1991 RetiredMOps * SchedModel->getMicroOpFactor();
1993 // If scaled micro-ops are now more than the previous critical resource by
1994 // a full cycle, then micro-ops issue becomes critical.
1995 if ((int)(ScaledMOps - getResourceCount(ZoneCritResIdx))
1996 >= (int)SchedModel->getLatencyFactor()) {
1998 DEBUG(dbgs() << " *** Critical resource NumMicroOps: "
1999 << ScaledMOps / SchedModel->getLatencyFactor() << "c\n");
2002 for (TargetSchedModel::ProcResIter
2003 PI = SchedModel->getWriteProcResBegin(SC),
2004 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
2006 countResource(PI->ProcResourceIdx, PI->Cycles, NextCycle);
2007 if (RCycle > NextCycle)
2010 if (SU->hasReservedResource) {
2011 // For reserved resources, record the highest cycle using the resource.
2012 // For top-down scheduling, this is the cycle in which we schedule this
2013 // instruction plus the number of cycles the operations reserves the
2014 // resource. For bottom-up is it simply the instruction's cycle.
2015 for (TargetSchedModel::ProcResIter
2016 PI = SchedModel->getWriteProcResBegin(SC),
2017 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
2018 unsigned PIdx = PI->ProcResourceIdx;
2019 if (SchedModel->getProcResource(PIdx)->BufferSize == 0) {
2021 ReservedCycles[PIdx] =
2022 std::max(getNextResourceCycle(PIdx, 0), NextCycle + PI->Cycles);
2025 ReservedCycles[PIdx] = NextCycle;
2030 // Update ExpectedLatency and DependentLatency.
2031 unsigned &TopLatency = isTop() ? ExpectedLatency : DependentLatency;
2032 unsigned &BotLatency = isTop() ? DependentLatency : ExpectedLatency;
2033 if (SU->getDepth() > TopLatency) {
2034 TopLatency = SU->getDepth();
2035 DEBUG(dbgs() << " " << Available.getName()
2036 << " TopLatency SU(" << SU->NodeNum << ") " << TopLatency << "c\n");
2038 if (SU->getHeight() > BotLatency) {
2039 BotLatency = SU->getHeight();
2040 DEBUG(dbgs() << " " << Available.getName()
2041 << " BotLatency SU(" << SU->NodeNum << ") " << BotLatency << "c\n");
2043 // If we stall for any reason, bump the cycle.
2044 if (NextCycle > CurrCycle) {
2045 bumpCycle(NextCycle);
2048 // After updating ZoneCritResIdx and ExpectedLatency, check if we're
2049 // resource limited. If a stall occurred, bumpCycle does this.
2050 unsigned LFactor = SchedModel->getLatencyFactor();
2052 (int)(getCriticalCount() - (getScheduledLatency() * LFactor))
2055 // Update CurrMOps after calling bumpCycle to handle stalls, since bumpCycle
2056 // resets CurrMOps. Loop to handle instructions with more MOps than issue in
2057 // one cycle. Since we commonly reach the max MOps here, opportunistically
2058 // bump the cycle to avoid uselessly checking everything in the readyQ.
2059 CurrMOps += IncMOps;
2060 while (CurrMOps >= SchedModel->getIssueWidth()) {
2061 DEBUG(dbgs() << " *** Max MOps " << CurrMOps
2062 << " at cycle " << CurrCycle << '\n');
2063 bumpCycle(++NextCycle);
2065 DEBUG(dumpScheduledState());
2068 /// Release pending ready nodes in to the available queue. This makes them
2069 /// visible to heuristics.
2070 void SchedBoundary::releasePending() {
2071 // If the available queue is empty, it is safe to reset MinReadyCycle.
2072 if (Available.empty())
2073 MinReadyCycle = UINT_MAX;
2075 // Check to see if any of the pending instructions are ready to issue. If
2076 // so, add them to the available queue.
2077 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
2078 for (unsigned i = 0, e = Pending.size(); i != e; ++i) {
2079 SUnit *SU = *(Pending.begin()+i);
2080 unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle;
2082 if (ReadyCycle < MinReadyCycle)
2083 MinReadyCycle = ReadyCycle;
2085 if (!IsBuffered && ReadyCycle > CurrCycle)
2088 if (checkHazard(SU))
2092 Pending.remove(Pending.begin()+i);
2095 DEBUG(if (!Pending.empty()) Pending.dump());
2096 CheckPending = false;
2099 /// Remove SU from the ready set for this boundary.
2100 void SchedBoundary::removeReady(SUnit *SU) {
2101 if (Available.isInQueue(SU))
2102 Available.remove(Available.find(SU));
2104 assert(Pending.isInQueue(SU) && "bad ready count");
2105 Pending.remove(Pending.find(SU));
2109 /// If this queue only has one ready candidate, return it. As a side effect,
2110 /// defer any nodes that now hit a hazard, and advance the cycle until at least
2111 /// one node is ready. If multiple instructions are ready, return NULL.
2112 SUnit *SchedBoundary::pickOnlyChoice() {
2117 // Defer any ready instrs that now have a hazard.
2118 for (ReadyQueue::iterator I = Available.begin(); I != Available.end();) {
2119 if (checkHazard(*I)) {
2121 I = Available.remove(I);
2127 for (unsigned i = 0; Available.empty(); ++i) {
2128 // FIXME: Re-enable assert once PR20057 is resolved.
2129 // assert(i <= (HazardRec->getMaxLookAhead() + MaxObservedStall) &&
2130 // "permanent hazard");
2132 bumpCycle(CurrCycle + 1);
2135 if (Available.size() == 1)
2136 return *Available.begin();
2141 // This is useful information to dump after bumpNode.
2142 // Note that the Queue contents are more useful before pickNodeFromQueue.
2143 void SchedBoundary::dumpScheduledState() {
2146 if (ZoneCritResIdx) {
2147 ResFactor = SchedModel->getResourceFactor(ZoneCritResIdx);
2148 ResCount = getResourceCount(ZoneCritResIdx);
2151 ResFactor = SchedModel->getMicroOpFactor();
2152 ResCount = RetiredMOps * SchedModel->getMicroOpFactor();
2154 unsigned LFactor = SchedModel->getLatencyFactor();
2155 dbgs() << Available.getName() << " @" << CurrCycle << "c\n"
2156 << " Retired: " << RetiredMOps;
2157 dbgs() << "\n Executed: " << getExecutedCount() / LFactor << "c";
2158 dbgs() << "\n Critical: " << ResCount / LFactor << "c, "
2159 << ResCount / ResFactor << " "
2160 << SchedModel->getResourceName(ZoneCritResIdx)
2161 << "\n ExpectedLatency: " << ExpectedLatency << "c\n"
2162 << (IsResourceLimited ? " - Resource" : " - Latency")
2167 //===----------------------------------------------------------------------===//
2168 // GenericScheduler - Generic implementation of MachineSchedStrategy.
2169 //===----------------------------------------------------------------------===//
2171 void GenericSchedulerBase::SchedCandidate::
2172 initResourceDelta(const ScheduleDAGMI *DAG,
2173 const TargetSchedModel *SchedModel) {
2174 if (!Policy.ReduceResIdx && !Policy.DemandResIdx)
2177 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
2178 for (TargetSchedModel::ProcResIter
2179 PI = SchedModel->getWriteProcResBegin(SC),
2180 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
2181 if (PI->ProcResourceIdx == Policy.ReduceResIdx)
2182 ResDelta.CritResources += PI->Cycles;
2183 if (PI->ProcResourceIdx == Policy.DemandResIdx)
2184 ResDelta.DemandedResources += PI->Cycles;
2188 /// Set the CandPolicy given a scheduling zone given the current resources and
2189 /// latencies inside and outside the zone.
2190 void GenericSchedulerBase::setPolicy(CandPolicy &Policy,
2192 SchedBoundary &CurrZone,
2193 SchedBoundary *OtherZone) {
2194 // Apply preemptive heuristics based on the total latency and resources
2195 // inside and outside this zone. Potential stalls should be considered before
2196 // following this policy.
2198 // Compute remaining latency. We need this both to determine whether the
2199 // overall schedule has become latency-limited and whether the instructions
2200 // outside this zone are resource or latency limited.
2202 // The "dependent" latency is updated incrementally during scheduling as the
2203 // max height/depth of scheduled nodes minus the cycles since it was
2205 // DLat = max (N.depth - (CurrCycle - N.ReadyCycle) for N in Zone
2207 // The "independent" latency is the max ready queue depth:
2208 // ILat = max N.depth for N in Available|Pending
2210 // RemainingLatency is the greater of independent and dependent latency.
2211 unsigned RemLatency = CurrZone.getDependentLatency();
2212 RemLatency = std::max(RemLatency,
2213 CurrZone.findMaxLatency(CurrZone.Available.elements()));
2214 RemLatency = std::max(RemLatency,
2215 CurrZone.findMaxLatency(CurrZone.Pending.elements()));
2217 // Compute the critical resource outside the zone.
2218 unsigned OtherCritIdx = 0;
2219 unsigned OtherCount =
2220 OtherZone ? OtherZone->getOtherResourceCount(OtherCritIdx) : 0;
2222 bool OtherResLimited = false;
2223 if (SchedModel->hasInstrSchedModel()) {
2224 unsigned LFactor = SchedModel->getLatencyFactor();
2225 OtherResLimited = (int)(OtherCount - (RemLatency * LFactor)) > (int)LFactor;
2227 // Schedule aggressively for latency in PostRA mode. We don't check for
2228 // acyclic latency during PostRA, and highly out-of-order processors will
2229 // skip PostRA scheduling.
2230 if (!OtherResLimited) {
2231 if (IsPostRA || (RemLatency + CurrZone.getCurrCycle() > Rem.CriticalPath)) {
2232 Policy.ReduceLatency |= true;
2233 DEBUG(dbgs() << " " << CurrZone.Available.getName()
2234 << " RemainingLatency " << RemLatency << " + "
2235 << CurrZone.getCurrCycle() << "c > CritPath "
2236 << Rem.CriticalPath << "\n");
2239 // If the same resource is limiting inside and outside the zone, do nothing.
2240 if (CurrZone.getZoneCritResIdx() == OtherCritIdx)
2244 if (CurrZone.isResourceLimited()) {
2245 dbgs() << " " << CurrZone.Available.getName() << " ResourceLimited: "
2246 << SchedModel->getResourceName(CurrZone.getZoneCritResIdx())
2249 if (OtherResLimited)
2250 dbgs() << " RemainingLimit: "
2251 << SchedModel->getResourceName(OtherCritIdx) << "\n";
2252 if (!CurrZone.isResourceLimited() && !OtherResLimited)
2253 dbgs() << " Latency limited both directions.\n");
2255 if (CurrZone.isResourceLimited() && !Policy.ReduceResIdx)
2256 Policy.ReduceResIdx = CurrZone.getZoneCritResIdx();
2258 if (OtherResLimited)
2259 Policy.DemandResIdx = OtherCritIdx;
2263 const char *GenericSchedulerBase::getReasonStr(
2264 GenericSchedulerBase::CandReason Reason) {
2266 case NoCand: return "NOCAND ";
2267 case PhysRegCopy: return "PREG-COPY";
2268 case RegExcess: return "REG-EXCESS";
2269 case RegCritical: return "REG-CRIT ";
2270 case Stall: return "STALL ";
2271 case Cluster: return "CLUSTER ";
2272 case Weak: return "WEAK ";
2273 case RegMax: return "REG-MAX ";
2274 case ResourceReduce: return "RES-REDUCE";
2275 case ResourceDemand: return "RES-DEMAND";
2276 case TopDepthReduce: return "TOP-DEPTH ";
2277 case TopPathReduce: return "TOP-PATH ";
2278 case BotHeightReduce:return "BOT-HEIGHT";
2279 case BotPathReduce: return "BOT-PATH ";
2280 case NextDefUse: return "DEF-USE ";
2281 case NodeOrder: return "ORDER ";
2283 llvm_unreachable("Unknown reason!");
2286 void GenericSchedulerBase::traceCandidate(const SchedCandidate &Cand) {
2288 unsigned ResIdx = 0;
2289 unsigned Latency = 0;
2290 switch (Cand.Reason) {
2294 P = Cand.RPDelta.Excess;
2297 P = Cand.RPDelta.CriticalMax;
2300 P = Cand.RPDelta.CurrentMax;
2302 case ResourceReduce:
2303 ResIdx = Cand.Policy.ReduceResIdx;
2305 case ResourceDemand:
2306 ResIdx = Cand.Policy.DemandResIdx;
2308 case TopDepthReduce:
2309 Latency = Cand.SU->getDepth();
2312 Latency = Cand.SU->getHeight();
2314 case BotHeightReduce:
2315 Latency = Cand.SU->getHeight();
2318 Latency = Cand.SU->getDepth();
2321 dbgs() << " Cand SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason);
2323 dbgs() << " " << TRI->getRegPressureSetName(P.getPSet())
2324 << ":" << P.getUnitInc() << " ";
2328 dbgs() << " " << SchedModel->getProcResource(ResIdx)->Name << " ";
2332 dbgs() << " " << Latency << " cycles ";
2339 /// Return true if this heuristic determines order.
2340 static bool tryLess(int TryVal, int CandVal,
2341 GenericSchedulerBase::SchedCandidate &TryCand,
2342 GenericSchedulerBase::SchedCandidate &Cand,
2343 GenericSchedulerBase::CandReason Reason) {
2344 if (TryVal < CandVal) {
2345 TryCand.Reason = Reason;
2348 if (TryVal > CandVal) {
2349 if (Cand.Reason > Reason)
2350 Cand.Reason = Reason;
2353 Cand.setRepeat(Reason);
2357 static bool tryGreater(int TryVal, int CandVal,
2358 GenericSchedulerBase::SchedCandidate &TryCand,
2359 GenericSchedulerBase::SchedCandidate &Cand,
2360 GenericSchedulerBase::CandReason Reason) {
2361 if (TryVal > CandVal) {
2362 TryCand.Reason = Reason;
2365 if (TryVal < CandVal) {
2366 if (Cand.Reason > Reason)
2367 Cand.Reason = Reason;
2370 Cand.setRepeat(Reason);
2374 static bool tryLatency(GenericSchedulerBase::SchedCandidate &TryCand,
2375 GenericSchedulerBase::SchedCandidate &Cand,
2376 SchedBoundary &Zone) {
2378 if (Cand.SU->getDepth() > Zone.getScheduledLatency()) {
2379 if (tryLess(TryCand.SU->getDepth(), Cand.SU->getDepth(),
2380 TryCand, Cand, GenericSchedulerBase::TopDepthReduce))
2383 if (tryGreater(TryCand.SU->getHeight(), Cand.SU->getHeight(),
2384 TryCand, Cand, GenericSchedulerBase::TopPathReduce))
2388 if (Cand.SU->getHeight() > Zone.getScheduledLatency()) {
2389 if (tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(),
2390 TryCand, Cand, GenericSchedulerBase::BotHeightReduce))
2393 if (tryGreater(TryCand.SU->getDepth(), Cand.SU->getDepth(),
2394 TryCand, Cand, GenericSchedulerBase::BotPathReduce))
2400 static void tracePick(const GenericSchedulerBase::SchedCandidate &Cand,
2402 DEBUG(dbgs() << "Pick " << (IsTop ? "Top " : "Bot ")
2403 << GenericSchedulerBase::getReasonStr(Cand.Reason) << '\n');
2406 void GenericScheduler::initialize(ScheduleDAGMI *dag) {
2407 assert(dag->hasVRegLiveness() &&
2408 "(PreRA)GenericScheduler needs vreg liveness");
2409 DAG = static_cast<ScheduleDAGMILive*>(dag);
2410 SchedModel = DAG->getSchedModel();
2413 Rem.init(DAG, SchedModel);
2414 Top.init(DAG, SchedModel, &Rem);
2415 Bot.init(DAG, SchedModel, &Rem);
2417 // Initialize resource counts.
2419 // Initialize the HazardRecognizers. If itineraries don't exist, are empty, or
2420 // are disabled, then these HazardRecs will be disabled.
2421 const InstrItineraryData *Itin = SchedModel->getInstrItineraries();
2422 if (!Top.HazardRec) {
2424 DAG->MF.getSubtarget().getInstrInfo()->CreateTargetMIHazardRecognizer(
2427 if (!Bot.HazardRec) {
2429 DAG->MF.getSubtarget().getInstrInfo()->CreateTargetMIHazardRecognizer(
2434 /// Initialize the per-region scheduling policy.
2435 void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
2436 MachineBasicBlock::iterator End,
2437 unsigned NumRegionInstrs) {
2438 const MachineFunction &MF = *Begin->getParent()->getParent();
2439 const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
2441 // Avoid setting up the register pressure tracker for small regions to save
2442 // compile time. As a rough heuristic, only track pressure when the number of
2443 // schedulable instructions exceeds half the integer register file.
2444 RegionPolicy.ShouldTrackPressure = true;
2445 for (unsigned VT = MVT::i32; VT > (unsigned)MVT::i1; --VT) {
2446 MVT::SimpleValueType LegalIntVT = (MVT::SimpleValueType)VT;
2447 if (TLI->isTypeLegal(LegalIntVT)) {
2448 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs(
2449 TLI->getRegClassFor(LegalIntVT));
2450 RegionPolicy.ShouldTrackPressure = NumRegionInstrs > (NIntRegs / 2);
2454 // For generic targets, we default to bottom-up, because it's simpler and more
2455 // compile-time optimizations have been implemented in that direction.
2456 RegionPolicy.OnlyBottomUp = true;
2458 // Allow the subtarget to override default policy.
2459 MF.getSubtarget().overrideSchedPolicy(RegionPolicy, Begin, End,
2462 // After subtarget overrides, apply command line options.
2463 if (!EnableRegPressure)
2464 RegionPolicy.ShouldTrackPressure = false;
2466 // Check -misched-topdown/bottomup can force or unforce scheduling direction.
2467 // e.g. -misched-bottomup=false allows scheduling in both directions.
2468 assert((!ForceTopDown || !ForceBottomUp) &&
2469 "-misched-topdown incompatible with -misched-bottomup");
2470 if (ForceBottomUp.getNumOccurrences() > 0) {
2471 RegionPolicy.OnlyBottomUp = ForceBottomUp;
2472 if (RegionPolicy.OnlyBottomUp)
2473 RegionPolicy.OnlyTopDown = false;
2475 if (ForceTopDown.getNumOccurrences() > 0) {
2476 RegionPolicy.OnlyTopDown = ForceTopDown;
2477 if (RegionPolicy.OnlyTopDown)
2478 RegionPolicy.OnlyBottomUp = false;
2482 void GenericScheduler::dumpPolicy() {
2483 dbgs() << "GenericScheduler RegionPolicy: "
2484 << " ShouldTrackPressure=" << RegionPolicy.ShouldTrackPressure
2485 << " OnlyTopDown=" << RegionPolicy.OnlyTopDown
2486 << " OnlyBottomUp=" << RegionPolicy.OnlyBottomUp
2490 /// Set IsAcyclicLatencyLimited if the acyclic path is longer than the cyclic
2491 /// critical path by more cycles than it takes to drain the instruction buffer.
2492 /// We estimate an upper bounds on in-flight instructions as:
2494 /// CyclesPerIteration = max( CyclicPath, Loop-Resource-Height )
2495 /// InFlightIterations = AcyclicPath / CyclesPerIteration
2496 /// InFlightResources = InFlightIterations * LoopResources
2498 /// TODO: Check execution resources in addition to IssueCount.
2499 void GenericScheduler::checkAcyclicLatency() {
2500 if (Rem.CyclicCritPath == 0 || Rem.CyclicCritPath >= Rem.CriticalPath)
2503 // Scaled number of cycles per loop iteration.
2504 unsigned IterCount =
2505 std::max(Rem.CyclicCritPath * SchedModel->getLatencyFactor(),
2507 // Scaled acyclic critical path.
2508 unsigned AcyclicCount = Rem.CriticalPath * SchedModel->getLatencyFactor();
2509 // InFlightCount = (AcyclicPath / IterCycles) * InstrPerLoop
2510 unsigned InFlightCount =
2511 (AcyclicCount * Rem.RemIssueCount + IterCount-1) / IterCount;
2512 unsigned BufferLimit =
2513 SchedModel->getMicroOpBufferSize() * SchedModel->getMicroOpFactor();
2515 Rem.IsAcyclicLatencyLimited = InFlightCount > BufferLimit;
2517 DEBUG(dbgs() << "IssueCycles="
2518 << Rem.RemIssueCount / SchedModel->getLatencyFactor() << "c "
2519 << "IterCycles=" << IterCount / SchedModel->getLatencyFactor()
2520 << "c NumIters=" << (AcyclicCount + IterCount-1) / IterCount
2521 << " InFlight=" << InFlightCount / SchedModel->getMicroOpFactor()
2522 << "m BufferLim=" << SchedModel->getMicroOpBufferSize() << "m\n";
2523 if (Rem.IsAcyclicLatencyLimited)
2524 dbgs() << " ACYCLIC LATENCY LIMIT\n");
2527 void GenericScheduler::registerRoots() {
2528 Rem.CriticalPath = DAG->ExitSU.getDepth();
2530 // Some roots may not feed into ExitSU. Check all of them in case.
2531 for (std::vector<SUnit*>::const_iterator
2532 I = Bot.Available.begin(), E = Bot.Available.end(); I != E; ++I) {
2533 if ((*I)->getDepth() > Rem.CriticalPath)
2534 Rem.CriticalPath = (*I)->getDepth();
2536 DEBUG(dbgs() << "Critical Path(GS-RR ): " << Rem.CriticalPath << '\n');
2537 if (DumpCriticalPathLength) {
2538 errs() << "Critical Path(GS-RR ): " << Rem.CriticalPath << " \n";
2541 if (EnableCyclicPath) {
2542 Rem.CyclicCritPath = DAG->computeCyclicCriticalPath();
2543 checkAcyclicLatency();
2547 static bool tryPressure(const PressureChange &TryP,
2548 const PressureChange &CandP,
2549 GenericSchedulerBase::SchedCandidate &TryCand,
2550 GenericSchedulerBase::SchedCandidate &Cand,
2551 GenericSchedulerBase::CandReason Reason) {
2552 int TryRank = TryP.getPSetOrMax();
2553 int CandRank = CandP.getPSetOrMax();
2554 // If both candidates affect the same set, go with the smallest increase.
2555 if (TryRank == CandRank) {
2556 return tryLess(TryP.getUnitInc(), CandP.getUnitInc(), TryCand, Cand,
2559 // If one candidate decreases and the other increases, go with it.
2560 // Invalid candidates have UnitInc==0.
2561 if (tryGreater(TryP.getUnitInc() < 0, CandP.getUnitInc() < 0, TryCand, Cand,
2565 // If the candidates are decreasing pressure, reverse priority.
2566 if (TryP.getUnitInc() < 0)
2567 std::swap(TryRank, CandRank);
2568 return tryGreater(TryRank, CandRank, TryCand, Cand, Reason);
2571 static unsigned getWeakLeft(const SUnit *SU, bool isTop) {
2572 return (isTop) ? SU->WeakPredsLeft : SU->WeakSuccsLeft;
2575 /// Minimize physical register live ranges. Regalloc wants them adjacent to
2576 /// their physreg def/use.
2578 /// FIXME: This is an unnecessary check on the critical path. Most are root/leaf
2579 /// copies which can be prescheduled. The rest (e.g. x86 MUL) could be bundled
2580 /// with the operation that produces or consumes the physreg. We'll do this when
2581 /// regalloc has support for parallel copies.
2582 static int biasPhysRegCopy(const SUnit *SU, bool isTop) {
2583 const MachineInstr *MI = SU->getInstr();
2587 unsigned ScheduledOper = isTop ? 1 : 0;
2588 unsigned UnscheduledOper = isTop ? 0 : 1;
2589 // If we have already scheduled the physreg produce/consumer, immediately
2590 // schedule the copy.
2591 if (TargetRegisterInfo::isPhysicalRegister(
2592 MI->getOperand(ScheduledOper).getReg()))
2594 // If the physreg is at the boundary, defer it. Otherwise schedule it
2595 // immediately to free the dependent. We can hoist the copy later.
2596 bool AtBoundary = isTop ? !SU->NumSuccsLeft : !SU->NumPredsLeft;
2597 if (TargetRegisterInfo::isPhysicalRegister(
2598 MI->getOperand(UnscheduledOper).getReg()))
2599 return AtBoundary ? -1 : 1;
2603 /// Apply a set of heursitics to a new candidate. Heuristics are currently
2604 /// hierarchical. This may be more efficient than a graduated cost model because
2605 /// we don't need to evaluate all aspects of the model for each node in the
2606 /// queue. But it's really done to make the heuristics easier to debug and
2607 /// statistically analyze.
2609 /// \param Cand provides the policy and current best candidate.
2610 /// \param TryCand refers to the next SUnit candidate, otherwise uninitialized.
2611 /// \param Zone describes the scheduled zone that we are extending.
2612 /// \param RPTracker describes reg pressure within the scheduled zone.
2613 /// \param TempTracker is a scratch pressure tracker to reuse in queries.
2614 void GenericScheduler::tryCandidate(SchedCandidate &Cand,
2615 SchedCandidate &TryCand,
2616 SchedBoundary &Zone,
2617 const RegPressureTracker &RPTracker,
2618 RegPressureTracker &TempTracker) {
2620 if (DAG->isTrackingPressure()) {
2621 // Always initialize TryCand's RPDelta.
2623 TempTracker.getMaxDownwardPressureDelta(
2624 TryCand.SU->getInstr(),
2626 DAG->getRegionCriticalPSets(),
2627 DAG->getRegPressure().MaxSetPressure);
2630 if (VerifyScheduling) {
2631 TempTracker.getMaxUpwardPressureDelta(
2632 TryCand.SU->getInstr(),
2633 &DAG->getPressureDiff(TryCand.SU),
2635 DAG->getRegionCriticalPSets(),
2636 DAG->getRegPressure().MaxSetPressure);
2639 RPTracker.getUpwardPressureDelta(
2640 TryCand.SU->getInstr(),
2641 DAG->getPressureDiff(TryCand.SU),
2643 DAG->getRegionCriticalPSets(),
2644 DAG->getRegPressure().MaxSetPressure);
2648 DEBUG(if (TryCand.RPDelta.Excess.isValid())
2649 dbgs() << " Try SU(" << TryCand.SU->NodeNum << ") "
2650 << TRI->getRegPressureSetName(TryCand.RPDelta.Excess.getPSet())
2651 << ":" << TryCand.RPDelta.Excess.getUnitInc() << "\n");
2653 // Initialize the candidate if needed.
2654 if (!Cand.isValid()) {
2655 TryCand.Reason = NodeOrder;
2659 if (tryGreater(biasPhysRegCopy(TryCand.SU, Zone.isTop()),
2660 biasPhysRegCopy(Cand.SU, Zone.isTop()),
2661 TryCand, Cand, PhysRegCopy))
2664 // Avoid exceeding the target's limit.
2665 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.Excess,
2666 Cand.RPDelta.Excess,
2667 TryCand, Cand, RegExcess))
2670 // Avoid increasing the max critical pressure in the scheduled region.
2671 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.CriticalMax,
2672 Cand.RPDelta.CriticalMax,
2673 TryCand, Cand, RegCritical))
2676 // For loops that are acyclic path limited, aggressively schedule for latency.
2677 // This can result in very long dependence chains scheduled in sequence, so
2678 // once every cycle (when CurrMOps == 0), switch to normal heuristics.
2679 if (Rem.IsAcyclicLatencyLimited && !Zone.getCurrMOps()
2680 && tryLatency(TryCand, Cand, Zone))
2683 // Prioritize instructions that read unbuffered resources by stall cycles.
2684 if (tryLess(Zone.getLatencyStallCycles(TryCand.SU),
2685 Zone.getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall))
2688 // Keep clustered nodes together to encourage downstream peephole
2689 // optimizations which may reduce resource requirements.
2691 // This is a best effort to set things up for a post-RA pass. Optimizations
2692 // like generating loads of multiple registers should ideally be done within
2693 // the scheduler pass by combining the loads during DAG postprocessing.
2694 const SUnit *NextClusterSU =
2695 Zone.isTop() ? DAG->getNextClusterSucc() : DAG->getNextClusterPred();
2696 if (tryGreater(TryCand.SU == NextClusterSU, Cand.SU == NextClusterSU,
2697 TryCand, Cand, Cluster))
2700 // Weak edges are for clustering and other constraints.
2701 if (tryLess(getWeakLeft(TryCand.SU, Zone.isTop()),
2702 getWeakLeft(Cand.SU, Zone.isTop()),
2703 TryCand, Cand, Weak)) {
2706 // Avoid increasing the max pressure of the entire region.
2707 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.CurrentMax,
2708 Cand.RPDelta.CurrentMax,
2709 TryCand, Cand, RegMax))
2712 // Avoid critical resource consumption and balance the schedule.
2713 TryCand.initResourceDelta(DAG, SchedModel);
2714 if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
2715 TryCand, Cand, ResourceReduce))
2717 if (tryGreater(TryCand.ResDelta.DemandedResources,
2718 Cand.ResDelta.DemandedResources,
2719 TryCand, Cand, ResourceDemand))
2722 // Avoid serializing long latency dependence chains.
2723 // For acyclic path limited loops, latency was already checked above.
2724 if (!RegionPolicy.DisableLatencyHeuristic && Cand.Policy.ReduceLatency &&
2725 !Rem.IsAcyclicLatencyLimited && tryLatency(TryCand, Cand, Zone)) {
2729 // Prefer immediate defs/users of the last scheduled instruction. This is a
2730 // local pressure avoidance strategy that also makes the machine code
2732 if (tryGreater(Zone.isNextSU(TryCand.SU), Zone.isNextSU(Cand.SU),
2733 TryCand, Cand, NextDefUse))
2736 // Fall through to original instruction order.
2737 if ((Zone.isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum)
2738 || (!Zone.isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) {
2739 TryCand.Reason = NodeOrder;
2743 /// Pick the best candidate from the queue.
2745 /// TODO: getMaxPressureDelta results can be mostly cached for each SUnit during
2746 /// DAG building. To adjust for the current scheduling location we need to
2747 /// maintain the number of vreg uses remaining to be top-scheduled.
2748 void GenericScheduler::pickNodeFromQueue(SchedBoundary &Zone,
2749 const RegPressureTracker &RPTracker,
2750 SchedCandidate &Cand) {
2751 ReadyQueue &Q = Zone.Available;
2755 // getMaxPressureDelta temporarily modifies the tracker.
2756 RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker);
2758 for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
2760 SchedCandidate TryCand(Cand.Policy);
2762 tryCandidate(Cand, TryCand, Zone, RPTracker, TempTracker);
2763 if (TryCand.Reason != NoCand) {
2764 // Initialize resource delta if needed in case future heuristics query it.
2765 if (TryCand.ResDelta == SchedResourceDelta())
2766 TryCand.initResourceDelta(DAG, SchedModel);
2767 Cand.setBest(TryCand);
2768 DEBUG(traceCandidate(Cand));
2773 /// Pick the best candidate node from either the top or bottom queue.
2774 SUnit *GenericScheduler::pickNodeBidirectional(bool &IsTopNode) {
2775 // Schedule as far as possible in the direction of no choice. This is most
2776 // efficient, but also provides the best heuristics for CriticalPSets.
2777 if (SUnit *SU = Bot.pickOnlyChoice()) {
2779 DEBUG(dbgs() << "Pick Bot NOCAND\n");
2782 if (SUnit *SU = Top.pickOnlyChoice()) {
2784 DEBUG(dbgs() << "Pick Top NOCAND\n");
2787 CandPolicy NoPolicy;
2788 SchedCandidate BotCand(NoPolicy);
2789 SchedCandidate TopCand(NoPolicy);
2790 // Set the bottom-up policy based on the state of the current bottom zone and
2791 // the instructions outside the zone, including the top zone.
2792 setPolicy(BotCand.Policy, /*IsPostRA=*/false, Bot, &Top);
2793 // Set the top-down policy based on the state of the current top zone and
2794 // the instructions outside the zone, including the bottom zone.
2795 setPolicy(TopCand.Policy, /*IsPostRA=*/false, Top, &Bot);
2797 // Prefer bottom scheduling when heuristics are silent.
2798 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2799 assert(BotCand.Reason != NoCand && "failed to find the first candidate");
2801 // If either Q has a single candidate that provides the least increase in
2802 // Excess pressure, we can immediately schedule from that Q.
2804 // RegionCriticalPSets summarizes the pressure within the scheduled region and
2805 // affects picking from either Q. If scheduling in one direction must
2806 // increase pressure for one of the excess PSets, then schedule in that
2807 // direction first to provide more freedom in the other direction.
2808 if ((BotCand.Reason == RegExcess && !BotCand.isRepeat(RegExcess))
2809 || (BotCand.Reason == RegCritical
2810 && !BotCand.isRepeat(RegCritical)))
2813 tracePick(BotCand, IsTopNode);
2816 // Check if the top Q has a better candidate.
2817 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2818 assert(TopCand.Reason != NoCand && "failed to find the first candidate");
2820 // Choose the queue with the most important (lowest enum) reason.
2821 if (TopCand.Reason < BotCand.Reason) {
2823 tracePick(TopCand, IsTopNode);
2826 // Otherwise prefer the bottom candidate, in node order if all else failed.
2828 tracePick(BotCand, IsTopNode);
2832 /// Pick the best node to balance the schedule. Implements MachineSchedStrategy.
2833 SUnit *GenericScheduler::pickNode(bool &IsTopNode) {
2834 if (DAG->top() == DAG->bottom()) {
2835 assert(Top.Available.empty() && Top.Pending.empty() &&
2836 Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage");
2841 if (RegionPolicy.OnlyTopDown) {
2842 SU = Top.pickOnlyChoice();
2844 CandPolicy NoPolicy;
2845 SchedCandidate TopCand(NoPolicy);
2846 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2847 assert(TopCand.Reason != NoCand && "failed to find a candidate");
2848 tracePick(TopCand, true);
2853 else if (RegionPolicy.OnlyBottomUp) {
2854 SU = Bot.pickOnlyChoice();
2856 CandPolicy NoPolicy;
2857 SchedCandidate BotCand(NoPolicy);
2858 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2859 assert(BotCand.Reason != NoCand && "failed to find a candidate");
2860 tracePick(BotCand, false);
2866 SU = pickNodeBidirectional(IsTopNode);
2868 } while (SU->isScheduled);
2870 if (SU->isTopReady())
2871 Top.removeReady(SU);
2872 if (SU->isBottomReady())
2873 Bot.removeReady(SU);
2875 DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr());
2879 void GenericScheduler::reschedulePhysRegCopies(SUnit *SU, bool isTop) {
2881 MachineBasicBlock::iterator InsertPos = SU->getInstr();
2884 SmallVectorImpl<SDep> &Deps = isTop ? SU->Preds : SU->Succs;
2886 // Find already scheduled copies with a single physreg dependence and move
2887 // them just above the scheduled instruction.
2888 for (SmallVectorImpl<SDep>::iterator I = Deps.begin(), E = Deps.end();
2890 if (I->getKind() != SDep::Data || !TRI->isPhysicalRegister(I->getReg()))
2892 SUnit *DepSU = I->getSUnit();
2893 if (isTop ? DepSU->Succs.size() > 1 : DepSU->Preds.size() > 1)
2895 MachineInstr *Copy = DepSU->getInstr();
2896 if (!Copy->isCopy())
2898 DEBUG(dbgs() << " Rescheduling physreg copy ";
2899 I->getSUnit()->dump(DAG));
2900 DAG->moveInstruction(Copy, InsertPos);
2904 /// Update the scheduler's state after scheduling a node. This is the same node
2905 /// that was just returned by pickNode(). However, ScheduleDAGMILive needs to
2906 /// update it's state based on the current cycle before MachineSchedStrategy
2909 /// FIXME: Eventually, we may bundle physreg copies rather than rescheduling
2910 /// them here. See comments in biasPhysRegCopy.
2911 void GenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
2913 SU->TopReadyCycle = std::max(SU->TopReadyCycle, Top.getCurrCycle());
2915 if (SU->hasPhysRegUses)
2916 reschedulePhysRegCopies(SU, true);
2919 SU->BotReadyCycle = std::max(SU->BotReadyCycle, Bot.getCurrCycle());
2921 if (SU->hasPhysRegDefs)
2922 reschedulePhysRegCopies(SU, false);
2926 /// Create the standard converging machine scheduler. This will be used as the
2927 /// default scheduler if the target does not set a default.
2928 static ScheduleDAGInstrs *createGenericSchedLive(MachineSchedContext *C) {
2929 ScheduleDAGMILive *DAG = new ScheduleDAGMILive(C, make_unique<GenericScheduler>(C));
2930 // Register DAG post-processors.
2932 // FIXME: extend the mutation API to allow earlier mutations to instantiate
2933 // data and pass it to later mutations. Have a single mutation that gathers
2934 // the interesting nodes in one pass.
2935 DAG->addMutation(make_unique<CopyConstrain>(DAG->TII, DAG->TRI));
2936 if (EnableLoadCluster && DAG->TII->enableClusterLoads())
2937 DAG->addMutation(make_unique<LoadClusterMutation>(DAG->TII, DAG->TRI));
2938 if (EnableMacroFusion)
2939 DAG->addMutation(make_unique<MacroFusion>(*DAG->TII, *DAG->TRI));
2943 static MachineSchedRegistry
2944 GenericSchedRegistry("converge", "Standard converging scheduler.",
2945 createGenericSchedLive);
2947 //===----------------------------------------------------------------------===//
2948 // PostGenericScheduler - Generic PostRA implementation of MachineSchedStrategy.
2949 //===----------------------------------------------------------------------===//
2951 void PostGenericScheduler::initialize(ScheduleDAGMI *Dag) {
2953 SchedModel = DAG->getSchedModel();
2956 Rem.init(DAG, SchedModel);
2957 Top.init(DAG, SchedModel, &Rem);
2960 // Initialize the HazardRecognizers. If itineraries don't exist, are empty,
2961 // or are disabled, then these HazardRecs will be disabled.
2962 const InstrItineraryData *Itin = SchedModel->getInstrItineraries();
2963 if (!Top.HazardRec) {
2965 DAG->MF.getSubtarget().getInstrInfo()->CreateTargetMIHazardRecognizer(
2971 void PostGenericScheduler::registerRoots() {
2972 Rem.CriticalPath = DAG->ExitSU.getDepth();
2974 // Some roots may not feed into ExitSU. Check all of them in case.
2975 for (SmallVectorImpl<SUnit*>::const_iterator
2976 I = BotRoots.begin(), E = BotRoots.end(); I != E; ++I) {
2977 if ((*I)->getDepth() > Rem.CriticalPath)
2978 Rem.CriticalPath = (*I)->getDepth();
2980 DEBUG(dbgs() << "Critical Path: (PGS-RR) " << Rem.CriticalPath << '\n');
2981 if (DumpCriticalPathLength) {
2982 errs() << "Critical Path(PGS-RR ): " << Rem.CriticalPath << " \n";
2986 /// Apply a set of heursitics to a new candidate for PostRA scheduling.
2988 /// \param Cand provides the policy and current best candidate.
2989 /// \param TryCand refers to the next SUnit candidate, otherwise uninitialized.
2990 void PostGenericScheduler::tryCandidate(SchedCandidate &Cand,
2991 SchedCandidate &TryCand) {
2993 // Initialize the candidate if needed.
2994 if (!Cand.isValid()) {
2995 TryCand.Reason = NodeOrder;
2999 // Prioritize instructions that read unbuffered resources by stall cycles.
3000 if (tryLess(Top.getLatencyStallCycles(TryCand.SU),
3001 Top.getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall))
3004 // Avoid critical resource consumption and balance the schedule.
3005 if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
3006 TryCand, Cand, ResourceReduce))
3008 if (tryGreater(TryCand.ResDelta.DemandedResources,
3009 Cand.ResDelta.DemandedResources,
3010 TryCand, Cand, ResourceDemand))
3013 // Avoid serializing long latency dependence chains.
3014 if (Cand.Policy.ReduceLatency && tryLatency(TryCand, Cand, Top)) {
3018 // Fall through to original instruction order.
3019 if (TryCand.SU->NodeNum < Cand.SU->NodeNum)
3020 TryCand.Reason = NodeOrder;
3023 void PostGenericScheduler::pickNodeFromQueue(SchedCandidate &Cand) {
3024 ReadyQueue &Q = Top.Available;
3028 for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
3029 SchedCandidate TryCand(Cand.Policy);
3031 TryCand.initResourceDelta(DAG, SchedModel);
3032 tryCandidate(Cand, TryCand);
3033 if (TryCand.Reason != NoCand) {
3034 Cand.setBest(TryCand);
3035 DEBUG(traceCandidate(Cand));
3040 /// Pick the next node to schedule.
3041 SUnit *PostGenericScheduler::pickNode(bool &IsTopNode) {
3042 if (DAG->top() == DAG->bottom()) {
3043 assert(Top.Available.empty() && Top.Pending.empty() && "ReadyQ garbage");
3048 SU = Top.pickOnlyChoice();
3050 CandPolicy NoPolicy;
3051 SchedCandidate TopCand(NoPolicy);
3052 // Set the top-down policy based on the state of the current top zone and
3053 // the instructions outside the zone, including the bottom zone.
3054 setPolicy(TopCand.Policy, /*IsPostRA=*/true, Top, nullptr);
3055 pickNodeFromQueue(TopCand);
3056 assert(TopCand.Reason != NoCand && "failed to find a candidate");
3057 tracePick(TopCand, true);
3060 } while (SU->isScheduled);
3063 Top.removeReady(SU);
3065 DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr());
3069 /// Called after ScheduleDAGMI has scheduled an instruction and updated
3070 /// scheduled/remaining flags in the DAG nodes.
3071 void PostGenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
3072 SU->TopReadyCycle = std::max(SU->TopReadyCycle, Top.getCurrCycle());
3076 /// Create a generic scheduler with no vreg liveness or DAG mutation passes.
3077 static ScheduleDAGInstrs *createGenericSchedPostRA(MachineSchedContext *C) {
3078 return new ScheduleDAGMI(C, make_unique<PostGenericScheduler>(C), /*IsPostRA=*/true);
3081 //===----------------------------------------------------------------------===//
3082 // ILP Scheduler. Currently for experimental analysis of heuristics.
3083 //===----------------------------------------------------------------------===//
3086 /// \brief Order nodes by the ILP metric.
3088 const SchedDFSResult *DFSResult;
3089 const BitVector *ScheduledTrees;
3092 ILPOrder(bool MaxILP)
3093 : DFSResult(nullptr), ScheduledTrees(nullptr), MaximizeILP(MaxILP) {}
3095 /// \brief Apply a less-than relation on node priority.
3097 /// (Return true if A comes after B in the Q.)
3098 bool operator()(const SUnit *A, const SUnit *B) const {
3099 unsigned SchedTreeA = DFSResult->getSubtreeID(A);
3100 unsigned SchedTreeB = DFSResult->getSubtreeID(B);
3101 if (SchedTreeA != SchedTreeB) {
3102 // Unscheduled trees have lower priority.
3103 if (ScheduledTrees->test(SchedTreeA) != ScheduledTrees->test(SchedTreeB))
3104 return ScheduledTrees->test(SchedTreeB);
3106 // Trees with shallower connections have have lower priority.
3107 if (DFSResult->getSubtreeLevel(SchedTreeA)
3108 != DFSResult->getSubtreeLevel(SchedTreeB)) {
3109 return DFSResult->getSubtreeLevel(SchedTreeA)
3110 < DFSResult->getSubtreeLevel(SchedTreeB);
3114 return DFSResult->getILP(A) < DFSResult->getILP(B);
3116 return DFSResult->getILP(A) > DFSResult->getILP(B);
3120 /// \brief Schedule based on the ILP metric.
3121 class ILPScheduler : public MachineSchedStrategy {
3122 ScheduleDAGMILive *DAG;
3125 std::vector<SUnit*> ReadyQ;
3127 ILPScheduler(bool MaximizeILP): DAG(nullptr), Cmp(MaximizeILP) {}
3129 void initialize(ScheduleDAGMI *dag) override {
3130 assert(dag->hasVRegLiveness() && "ILPScheduler needs vreg liveness");
3131 DAG = static_cast<ScheduleDAGMILive*>(dag);
3132 DAG->computeDFSResult();
3133 Cmp.DFSResult = DAG->getDFSResult();
3134 Cmp.ScheduledTrees = &DAG->getScheduledTrees();
3138 void registerRoots() override {
3139 // Restore the heap in ReadyQ with the updated DFS results.
3140 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3143 /// Implement MachineSchedStrategy interface.
3144 /// -----------------------------------------
3146 /// Callback to select the highest priority node from the ready Q.
3147 SUnit *pickNode(bool &IsTopNode) override {
3148 if (ReadyQ.empty()) return nullptr;
3149 std::pop_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3150 SUnit *SU = ReadyQ.back();
3153 DEBUG(dbgs() << "Pick node " << "SU(" << SU->NodeNum << ") "
3154 << " ILP: " << DAG->getDFSResult()->getILP(SU)
3155 << " Tree: " << DAG->getDFSResult()->getSubtreeID(SU) << " @"
3156 << DAG->getDFSResult()->getSubtreeLevel(
3157 DAG->getDFSResult()->getSubtreeID(SU)) << '\n'
3158 << "Scheduling " << *SU->getInstr());
3162 /// \brief Scheduler callback to notify that a new subtree is scheduled.
3163 void scheduleTree(unsigned SubtreeID) override {
3164 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3167 /// Callback after a node is scheduled. Mark a newly scheduled tree, notify
3168 /// DFSResults, and resort the priority Q.
3169 void schedNode(SUnit *SU, bool IsTopNode) override {
3170 assert(!IsTopNode && "SchedDFSResult needs bottom-up");
3173 void releaseTopNode(SUnit *) override { /*only called for top roots*/ }
3175 void releaseBottomNode(SUnit *SU) override {
3176 ReadyQ.push_back(SU);
3177 std::push_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3182 static ScheduleDAGInstrs *createILPMaxScheduler(MachineSchedContext *C) {
3183 return new ScheduleDAGMILive(C, make_unique<ILPScheduler>(true));
3185 static ScheduleDAGInstrs *createILPMinScheduler(MachineSchedContext *C) {
3186 return new ScheduleDAGMILive(C, make_unique<ILPScheduler>(false));
3188 static MachineSchedRegistry ILPMaxRegistry(
3189 "ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler);
3190 static MachineSchedRegistry ILPMinRegistry(
3191 "ilpmin", "Schedule bottom-up for min ILP", createILPMinScheduler);
3193 //===----------------------------------------------------------------------===//
3194 // Machine Instruction Shuffler for Correctness Testing
3195 //===----------------------------------------------------------------------===//
3199 /// Apply a less-than relation on the node order, which corresponds to the
3200 /// instruction order prior to scheduling. IsReverse implements greater-than.
3201 template<bool IsReverse>
3203 bool operator()(SUnit *A, SUnit *B) const {
3205 return A->NodeNum > B->NodeNum;
3207 return A->NodeNum < B->NodeNum;
3211 /// Reorder instructions as much as possible.
3212 class InstructionShuffler : public MachineSchedStrategy {
3216 // Using a less-than relation (SUnitOrder<false>) for the TopQ priority
3217 // gives nodes with a higher number higher priority causing the latest
3218 // instructions to be scheduled first.
3219 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false> >
3221 // When scheduling bottom-up, use greater-than as the queue priority.
3222 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true> >
3225 InstructionShuffler(bool alternate, bool topdown)
3226 : IsAlternating(alternate), IsTopDown(topdown) {}
3228 void initialize(ScheduleDAGMI*) override {
3233 /// Implement MachineSchedStrategy interface.
3234 /// -----------------------------------------
3236 SUnit *pickNode(bool &IsTopNode) override {
3240 if (TopQ.empty()) return nullptr;
3243 } while (SU->isScheduled);
3248 if (BottomQ.empty()) return nullptr;
3251 } while (SU->isScheduled);
3255 IsTopDown = !IsTopDown;
3259 void schedNode(SUnit *SU, bool IsTopNode) override {}
3261 void releaseTopNode(SUnit *SU) override {
3264 void releaseBottomNode(SUnit *SU) override {
3270 static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
3271 bool Alternate = !ForceTopDown && !ForceBottomUp;
3272 bool TopDown = !ForceBottomUp;
3273 assert((TopDown || !ForceTopDown) &&
3274 "-misched-topdown incompatible with -misched-bottomup");
3275 return new ScheduleDAGMILive(C, make_unique<InstructionShuffler>(Alternate, TopDown));
3277 static MachineSchedRegistry ShufflerRegistry(
3278 "shuffle", "Shuffle machine instructions alternating directions",
3279 createInstructionShuffler);
3282 //===----------------------------------------------------------------------===//
3283 // GraphWriter support for ScheduleDAGMILive.
3284 //===----------------------------------------------------------------------===//
3289 template<> struct GraphTraits<
3290 ScheduleDAGMI*> : public GraphTraits<ScheduleDAG*> {};
3293 struct DOTGraphTraits<ScheduleDAGMI*> : public DefaultDOTGraphTraits {
3295 DOTGraphTraits (bool isSimple=false) : DefaultDOTGraphTraits(isSimple) {}
3297 static std::string getGraphName(const ScheduleDAG *G) {
3298 return G->MF.getName();
3301 static bool renderGraphFromBottomUp() {
3305 static bool isNodeHidden(const SUnit *Node) {
3306 if (ViewMISchedCutoff == 0)
3308 return (Node->Preds.size() > ViewMISchedCutoff
3309 || Node->Succs.size() > ViewMISchedCutoff);
3312 /// If you want to override the dot attributes printed for a particular
3313 /// edge, override this method.
3314 static std::string getEdgeAttributes(const SUnit *Node,
3316 const ScheduleDAG *Graph) {
3317 if (EI.isArtificialDep())
3318 return "color=cyan,style=dashed";
3320 return "color=blue,style=dashed";
3324 static std::string getNodeLabel(const SUnit *SU, const ScheduleDAG *G) {
3326 raw_string_ostream SS(Str);
3327 const ScheduleDAGMI *DAG = static_cast<const ScheduleDAGMI*>(G);
3328 const SchedDFSResult *DFS = DAG->hasVRegLiveness() ?
3329 static_cast<const ScheduleDAGMILive*>(G)->getDFSResult() : nullptr;
3330 SS << "SU:" << SU->NodeNum;
3332 SS << " I:" << DFS->getNumInstrs(SU);
3335 static std::string getNodeDescription(const SUnit *SU, const ScheduleDAG *G) {
3336 return G->getGraphNodeLabel(SU);
3339 static std::string getNodeAttributes(const SUnit *N, const ScheduleDAG *G) {
3340 std::string Str("shape=Mrecord");
3341 const ScheduleDAGMI *DAG = static_cast<const ScheduleDAGMI*>(G);
3342 const SchedDFSResult *DFS = DAG->hasVRegLiveness() ?
3343 static_cast<const ScheduleDAGMILive*>(G)->getDFSResult() : nullptr;
3345 Str += ",style=filled,fillcolor=\"#";
3346 Str += DOT::getColorString(DFS->getSubtreeID(N));
3355 /// viewGraph - Pop up a ghostview window with the reachable parts of the DAG
3356 /// rendered using 'dot'.
3358 void ScheduleDAGMI::viewGraph(const Twine &Name, const Twine &Title) {
3360 ViewGraph(this, Name, false, Title);
3362 errs() << "ScheduleDAGMI::viewGraph is only available in debug builds on "
3363 << "systems with Graphviz or gv!\n";
3367 /// Out-of-line implementation with no arguments is handy for gdb.
3368 void ScheduleDAGMI::viewGraph() {
3369 viewGraph(getDAGName(), "Scheduling-Units Graph for " + getDAGName());