1 //===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MachineScheduler schedules machine instructions after phi elimination. It
11 // preserves LiveIntervals so it can be invoked before register allocation.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "misched"
17 #include "llvm/CodeGen/MachineScheduler.h"
18 #include "llvm/ADT/OwningPtr.h"
19 #include "llvm/ADT/PriorityQueue.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegisterClassInfo.h"
27 #include "llvm/CodeGen/ScheduleDFS.h"
28 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/GraphWriter.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetInstrInfo.h"
40 cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
41 cl::desc("Force top-down list scheduling"));
42 cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
43 cl::desc("Force bottom-up list scheduling"));
47 static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden,
48 cl::desc("Pop up a window to show MISched dags after they are processed"));
50 static cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden,
51 cl::desc("Stop scheduling after N instructions"), cl::init(~0U));
53 static bool ViewMISchedDAGs = false;
56 static cl::opt<bool> EnableRegPressure("misched-regpressure", cl::Hidden,
57 cl::desc("Enable register pressure scheduling."), cl::init(true));
59 static cl::opt<bool> EnableCyclicPath("misched-cyclicpath", cl::Hidden,
60 cl::desc("Enable cyclic critical path analysis."), cl::init(false));
62 static cl::opt<bool> EnableLoadCluster("misched-cluster", cl::Hidden,
63 cl::desc("Enable load clustering."), cl::init(true));
65 // Experimental heuristics
66 static cl::opt<bool> EnableMacroFusion("misched-fusion", cl::Hidden,
67 cl::desc("Enable scheduling for macro fusion."), cl::init(true));
69 static cl::opt<bool> VerifyScheduling("verify-misched", cl::Hidden,
70 cl::desc("Verify machine instrs before and after machine scheduling"));
72 // DAG subtrees must have at least this many nodes.
73 static const unsigned MinSubtreeSize = 8;
75 //===----------------------------------------------------------------------===//
76 // Machine Instruction Scheduling Pass and Registry
77 //===----------------------------------------------------------------------===//
79 MachineSchedContext::MachineSchedContext():
80 MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {
81 RegClassInfo = new RegisterClassInfo();
84 MachineSchedContext::~MachineSchedContext() {
89 /// MachineScheduler runs after coalescing and before register allocation.
90 class MachineScheduler : public MachineSchedContext,
91 public MachineFunctionPass {
95 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
97 virtual void releaseMemory() {}
99 virtual bool runOnMachineFunction(MachineFunction&);
101 virtual void print(raw_ostream &O, const Module* = 0) const;
103 static char ID; // Class identification, replacement for typeinfo
107 char MachineScheduler::ID = 0;
109 char &llvm::MachineSchedulerID = MachineScheduler::ID;
111 INITIALIZE_PASS_BEGIN(MachineScheduler, "misched",
112 "Machine Instruction Scheduler", false, false)
113 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
114 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
115 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
116 INITIALIZE_PASS_END(MachineScheduler, "misched",
117 "Machine Instruction Scheduler", false, false)
119 MachineScheduler::MachineScheduler()
120 : MachineFunctionPass(ID) {
121 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
124 void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
125 AU.setPreservesCFG();
126 AU.addRequiredID(MachineDominatorsID);
127 AU.addRequired<MachineLoopInfo>();
128 AU.addRequired<AliasAnalysis>();
129 AU.addRequired<TargetPassConfig>();
130 AU.addRequired<SlotIndexes>();
131 AU.addPreserved<SlotIndexes>();
132 AU.addRequired<LiveIntervals>();
133 AU.addPreserved<LiveIntervals>();
134 MachineFunctionPass::getAnalysisUsage(AU);
137 MachinePassRegistry MachineSchedRegistry::Registry;
139 /// A dummy default scheduler factory indicates whether the scheduler
140 /// is overridden on the command line.
141 static ScheduleDAGInstrs *useDefaultMachineSched(MachineSchedContext *C) {
145 /// MachineSchedOpt allows command line selection of the scheduler.
146 static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
147 RegisterPassParser<MachineSchedRegistry> >
148 MachineSchedOpt("misched",
149 cl::init(&useDefaultMachineSched), cl::Hidden,
150 cl::desc("Machine instruction scheduler to use"));
152 static MachineSchedRegistry
153 DefaultSchedRegistry("default", "Use the target's default scheduler choice.",
154 useDefaultMachineSched);
156 /// Forward declare the standard machine scheduler. This will be used as the
157 /// default scheduler if the target does not set a default.
158 static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C);
161 /// Decrement this iterator until reaching the top or a non-debug instr.
162 static MachineBasicBlock::const_iterator
163 priorNonDebug(MachineBasicBlock::const_iterator I,
164 MachineBasicBlock::const_iterator Beg) {
165 assert(I != Beg && "reached the top of the region, cannot decrement");
167 if (!I->isDebugValue())
173 /// Non-const version.
174 static MachineBasicBlock::iterator
175 priorNonDebug(MachineBasicBlock::iterator I,
176 MachineBasicBlock::const_iterator Beg) {
177 return const_cast<MachineInstr*>(
178 &*priorNonDebug(MachineBasicBlock::const_iterator(I), Beg));
181 /// If this iterator is a debug value, increment until reaching the End or a
182 /// non-debug instruction.
183 static MachineBasicBlock::const_iterator
184 nextIfDebug(MachineBasicBlock::const_iterator I,
185 MachineBasicBlock::const_iterator End) {
186 for(; I != End; ++I) {
187 if (!I->isDebugValue())
193 /// Non-const version.
194 static MachineBasicBlock::iterator
195 nextIfDebug(MachineBasicBlock::iterator I,
196 MachineBasicBlock::const_iterator End) {
197 // Cast the return value to nonconst MachineInstr, then cast to an
198 // instr_iterator, which does not check for null, finally return a
200 return MachineBasicBlock::instr_iterator(
201 const_cast<MachineInstr*>(
202 &*nextIfDebug(MachineBasicBlock::const_iterator(I), End)));
205 /// Top-level MachineScheduler pass driver.
207 /// Visit blocks in function order. Divide each block into scheduling regions
208 /// and visit them bottom-up. Visiting regions bottom-up is not required, but is
209 /// consistent with the DAG builder, which traverses the interior of the
210 /// scheduling regions bottom-up.
212 /// This design avoids exposing scheduling boundaries to the DAG builder,
213 /// simplifying the DAG builder's support for "special" target instructions.
214 /// At the same time the design allows target schedulers to operate across
215 /// scheduling boundaries, for example to bundle the boudary instructions
216 /// without reordering them. This creates complexity, because the target
217 /// scheduler must update the RegionBegin and RegionEnd positions cached by
218 /// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler
219 /// design would be to split blocks at scheduling boundaries, but LLVM has a
220 /// general bias against block splitting purely for implementation simplicity.
221 bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
222 DEBUG(dbgs() << "Before MISsched:\n"; mf.print(dbgs()));
224 // Initialize the context of the pass.
226 MLI = &getAnalysis<MachineLoopInfo>();
227 MDT = &getAnalysis<MachineDominatorTree>();
228 PassConfig = &getAnalysis<TargetPassConfig>();
229 AA = &getAnalysis<AliasAnalysis>();
231 LIS = &getAnalysis<LiveIntervals>();
232 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
234 if (VerifyScheduling) {
236 MF->verify(this, "Before machine scheduling.");
238 RegClassInfo->runOnMachineFunction(*MF);
240 // Select the scheduler, or set the default.
241 MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
242 if (Ctor == useDefaultMachineSched) {
243 // Get the default scheduler set by the target.
244 Ctor = MachineSchedRegistry::getDefault();
246 Ctor = createConvergingSched;
247 MachineSchedRegistry::setDefault(Ctor);
250 // Instantiate the selected scheduler.
251 OwningPtr<ScheduleDAGInstrs> Scheduler(Ctor(this));
253 // Visit all machine basic blocks.
255 // TODO: Visit blocks in global postorder or postorder within the bottom-up
256 // loop tree. Then we can optionally compute global RegPressure.
257 for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
258 MBB != MBBEnd; ++MBB) {
260 Scheduler->startBlock(MBB);
262 // Break the block into scheduling regions [I, RegionEnd), and schedule each
263 // region as soon as it is discovered. RegionEnd points the scheduling
264 // boundary at the bottom of the region. The DAG does not include RegionEnd,
265 // but the region does (i.e. the next RegionEnd is above the previous
266 // RegionBegin). If the current block has no terminator then RegionEnd ==
267 // MBB->end() for the bottom region.
269 // The Scheduler may insert instructions during either schedule() or
270 // exitRegion(), even for empty regions. So the local iterators 'I' and
271 // 'RegionEnd' are invalid across these calls.
272 unsigned RemainingInstrs = MBB->size();
273 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
274 RegionEnd != MBB->begin(); RegionEnd = Scheduler->begin()) {
276 // Avoid decrementing RegionEnd for blocks with no terminator.
277 if (RegionEnd != MBB->end()
278 || TII->isSchedulingBoundary(llvm::prior(RegionEnd), MBB, *MF)) {
280 // Count the boundary instruction.
284 // The next region starts above the previous region. Look backward in the
285 // instruction stream until we find the nearest boundary.
286 unsigned NumRegionInstrs = 0;
287 MachineBasicBlock::iterator I = RegionEnd;
288 for(;I != MBB->begin(); --I, --RemainingInstrs, ++NumRegionInstrs) {
289 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, *MF))
292 // Notify the scheduler of the region, even if we may skip scheduling
293 // it. Perhaps it still needs to be bundled.
294 Scheduler->enterRegion(MBB, I, RegionEnd, NumRegionInstrs);
296 // Skip empty scheduling regions (0 or 1 schedulable instructions).
297 if (I == RegionEnd || I == llvm::prior(RegionEnd)) {
298 // Close the current region. Bundle the terminator if needed.
299 // This invalidates 'RegionEnd' and 'I'.
300 Scheduler->exitRegion();
303 DEBUG(dbgs() << "********** MI Scheduling **********\n");
304 DEBUG(dbgs() << MF->getName()
305 << ":BB#" << MBB->getNumber() << " " << MBB->getName()
306 << "\n From: " << *I << " To: ";
307 if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
308 else dbgs() << "End";
309 dbgs() << " RegionInstrs: " << NumRegionInstrs
310 << " Remaining: " << RemainingInstrs << "\n");
312 // Schedule a region: possibly reorder instructions.
313 // This invalidates 'RegionEnd' and 'I'.
314 Scheduler->schedule();
316 // Close the current region.
317 Scheduler->exitRegion();
319 // Scheduling has invalidated the current iterator 'I'. Ask the
320 // scheduler for the top of it's scheduled region.
321 RegionEnd = Scheduler->begin();
323 assert(RemainingInstrs == 0 && "Instruction count mismatch!");
324 Scheduler->finishBlock();
326 Scheduler->finalizeSchedule();
328 if (VerifyScheduling)
329 MF->verify(this, "After machine scheduling.");
333 void MachineScheduler::print(raw_ostream &O, const Module* m) const {
337 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
338 void ReadyQueue::dump() {
339 dbgs() << Name << ": ";
340 for (unsigned i = 0, e = Queue.size(); i < e; ++i)
341 dbgs() << Queue[i]->NodeNum << " ";
346 //===----------------------------------------------------------------------===//
347 // ScheduleDAGMI - Base class for MachineInstr scheduling with LiveIntervals
349 //===----------------------------------------------------------------------===//
351 ScheduleDAGMI::~ScheduleDAGMI() {
353 DeleteContainerPointers(Mutations);
357 bool ScheduleDAGMI::canAddEdge(SUnit *SuccSU, SUnit *PredSU) {
358 return SuccSU == &ExitSU || !Topo.IsReachable(PredSU, SuccSU);
361 bool ScheduleDAGMI::addEdge(SUnit *SuccSU, const SDep &PredDep) {
362 if (SuccSU != &ExitSU) {
363 // Do not use WillCreateCycle, it assumes SD scheduling.
364 // If Pred is reachable from Succ, then the edge creates a cycle.
365 if (Topo.IsReachable(PredDep.getSUnit(), SuccSU))
367 Topo.AddPred(SuccSU, PredDep.getSUnit());
369 SuccSU->addPred(PredDep, /*Required=*/!PredDep.isArtificial());
370 // Return true regardless of whether a new edge needed to be inserted.
374 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
375 /// NumPredsLeft reaches zero, release the successor node.
377 /// FIXME: Adjust SuccSU height based on MinLatency.
378 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
379 SUnit *SuccSU = SuccEdge->getSUnit();
381 if (SuccEdge->isWeak()) {
382 --SuccSU->WeakPredsLeft;
383 if (SuccEdge->isCluster())
384 NextClusterSucc = SuccSU;
388 if (SuccSU->NumPredsLeft == 0) {
389 dbgs() << "*** Scheduling failed! ***\n";
391 dbgs() << " has been released too many times!\n";
395 --SuccSU->NumPredsLeft;
396 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
397 SchedImpl->releaseTopNode(SuccSU);
400 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
401 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
402 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
404 releaseSucc(SU, &*I);
408 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. When
409 /// NumSuccsLeft reaches zero, release the predecessor node.
411 /// FIXME: Adjust PredSU height based on MinLatency.
412 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
413 SUnit *PredSU = PredEdge->getSUnit();
415 if (PredEdge->isWeak()) {
416 --PredSU->WeakSuccsLeft;
417 if (PredEdge->isCluster())
418 NextClusterPred = PredSU;
422 if (PredSU->NumSuccsLeft == 0) {
423 dbgs() << "*** Scheduling failed! ***\n";
425 dbgs() << " has been released too many times!\n";
429 --PredSU->NumSuccsLeft;
430 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU)
431 SchedImpl->releaseBottomNode(PredSU);
434 /// releasePredecessors - Call releasePred on each of SU's predecessors.
435 void ScheduleDAGMI::releasePredecessors(SUnit *SU) {
436 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
438 releasePred(SU, &*I);
442 /// This is normally called from the main scheduler loop but may also be invoked
443 /// by the scheduling strategy to perform additional code motion.
444 void ScheduleDAGMI::moveInstruction(MachineInstr *MI,
445 MachineBasicBlock::iterator InsertPos) {
446 // Advance RegionBegin if the first instruction moves down.
447 if (&*RegionBegin == MI)
450 // Update the instruction stream.
451 BB->splice(InsertPos, BB, MI);
453 // Update LiveIntervals
454 LIS->handleMove(MI, /*UpdateFlags=*/true);
456 // Recede RegionBegin if an instruction moves above the first.
457 if (RegionBegin == InsertPos)
461 bool ScheduleDAGMI::checkSchedLimit() {
463 if (NumInstrsScheduled == MISchedCutoff && MISchedCutoff != ~0U) {
464 CurrentTop = CurrentBottom;
467 ++NumInstrsScheduled;
472 /// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
473 /// crossing a scheduling boundary. [begin, end) includes all instructions in
474 /// the region, including the boundary itself and single-instruction regions
475 /// that don't get scheduled.
476 void ScheduleDAGMI::enterRegion(MachineBasicBlock *bb,
477 MachineBasicBlock::iterator begin,
478 MachineBasicBlock::iterator end,
479 unsigned regioninstrs)
481 ScheduleDAGInstrs::enterRegion(bb, begin, end, regioninstrs);
483 ShouldTrackPressure = EnableRegPressure;
485 // For convenience remember the end of the liveness region.
487 (RegionEnd == bb->end()) ? RegionEnd : llvm::next(RegionEnd);
490 // Setup the register pressure trackers for the top scheduled top and bottom
491 // scheduled regions.
492 void ScheduleDAGMI::initRegPressure() {
493 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin);
494 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
496 // Close the RPTracker to finalize live ins.
497 RPTracker.closeRegion();
499 DEBUG(RPTracker.dump());
501 // Initialize the live ins and live outs.
502 TopRPTracker.addLiveRegs(RPTracker.getPressure().LiveInRegs);
503 BotRPTracker.addLiveRegs(RPTracker.getPressure().LiveOutRegs);
505 // Close one end of the tracker so we can call
506 // getMaxUpward/DownwardPressureDelta before advancing across any
507 // instructions. This converts currently live regs into live ins/outs.
508 TopRPTracker.closeTop();
509 BotRPTracker.closeBottom();
511 BotRPTracker.initLiveThru(RPTracker);
512 if (!BotRPTracker.getLiveThru().empty()) {
513 TopRPTracker.initLiveThru(BotRPTracker.getLiveThru());
514 DEBUG(dbgs() << "Live Thru: ";
515 dumpRegSetPressure(BotRPTracker.getLiveThru(), TRI));
518 // For each live out vreg reduce the pressure change associated with other
519 // uses of the same vreg below the live-out reaching def.
520 updatePressureDiffs(RPTracker.getPressure().LiveOutRegs);
522 // Account for liveness generated by the region boundary.
523 if (LiveRegionEnd != RegionEnd) {
524 SmallVector<unsigned, 8> LiveUses;
525 BotRPTracker.recede(&LiveUses);
526 updatePressureDiffs(LiveUses);
529 assert(BotRPTracker.getPos() == RegionEnd && "Can't find the region bottom");
531 // Cache the list of excess pressure sets in this region. This will also track
532 // the max pressure in the scheduled code for these sets.
533 RegionCriticalPSets.clear();
534 const std::vector<unsigned> &RegionPressure =
535 RPTracker.getPressure().MaxSetPressure;
536 for (unsigned i = 0, e = RegionPressure.size(); i < e; ++i) {
537 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i);
538 if (RegionPressure[i] > Limit) {
539 DEBUG(dbgs() << TRI->getRegPressureSetName(i)
540 << " Limit " << Limit
541 << " Actual " << RegionPressure[i] << "\n");
542 RegionCriticalPSets.push_back(PressureChange(i));
545 DEBUG(dbgs() << "Excess PSets: ";
546 for (unsigned i = 0, e = RegionCriticalPSets.size(); i != e; ++i)
547 dbgs() << TRI->getRegPressureSetName(
548 RegionCriticalPSets[i].getPSet()) << " ";
552 // FIXME: When the pressure tracker deals in pressure differences then we won't
553 // iterate over all RegionCriticalPSets[i].
555 updateScheduledPressure(const std::vector<unsigned> &NewMaxPressure) {
556 for (unsigned i = 0, e = RegionCriticalPSets.size(); i < e; ++i) {
557 unsigned ID = RegionCriticalPSets[i].getPSet();
558 if ((int)NewMaxPressure[ID] > RegionCriticalPSets[i].getUnitInc()
559 && NewMaxPressure[ID] <= INT16_MAX)
560 RegionCriticalPSets[i].setUnitInc(NewMaxPressure[ID]);
563 for (unsigned i = 0, e = NewMaxPressure.size(); i < e; ++i) {
564 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i);
565 if (NewMaxPressure[i] > Limit ) {
566 dbgs() << " " << TRI->getRegPressureSetName(i) << ": "
567 << NewMaxPressure[i] << " > " << Limit << "\n";
572 /// Update the PressureDiff array for liveness after scheduling this
574 void ScheduleDAGMI::updatePressureDiffs(ArrayRef<unsigned> LiveUses) {
575 for (unsigned LUIdx = 0, LUEnd = LiveUses.size(); LUIdx != LUEnd; ++LUIdx) {
576 /// FIXME: Currently assuming single-use physregs.
577 unsigned Reg = LiveUses[LUIdx];
578 if (!TRI->isVirtualRegister(Reg))
580 // This may be called before CurrentBottom has been initialized. However,
581 // BotRPTracker must have a valid position. We want the value live into the
582 // instruction or live out of the block, so ask for the previous
583 // instruction's live-out.
584 const LiveInterval &LI = LIS->getInterval(Reg);
586 MachineBasicBlock::const_iterator I =
587 nextIfDebug(BotRPTracker.getPos(), BB->end());
589 VNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
591 LiveRangeQuery LRQ(LI, LIS->getInstructionIndex(I));
594 // RegisterPressureTracker guarantees that readsReg is true for LiveUses.
595 assert(VNI && "No live value at use.");
596 for (VReg2UseMap::iterator
597 UI = VRegUses.find(Reg); UI != VRegUses.end(); ++UI) {
599 // If this use comes before the reaching def, it cannot be a last use, so
600 // descrease its pressure change.
601 if (!SU->isScheduled && SU != &ExitSU) {
602 LiveRangeQuery LRQ(LI, LIS->getInstructionIndex(SU->getInstr()));
603 if (LRQ.valueIn() == VNI)
604 getPressureDiff(SU).addPressureChange(Reg, true, &MRI);
610 /// schedule - Called back from MachineScheduler::runOnMachineFunction
611 /// after setting up the current scheduling region. [RegionBegin, RegionEnd)
612 /// only includes instructions that have DAG nodes, not scheduling boundaries.
614 /// This is a skeletal driver, with all the functionality pushed into helpers,
615 /// so that it can be easilly extended by experimental schedulers. Generally,
616 /// implementing MachineSchedStrategy should be sufficient to implement a new
617 /// scheduling algorithm. However, if a scheduler further subclasses
618 /// ScheduleDAGMI then it will want to override this virtual method in order to
619 /// update any specialized state.
620 void ScheduleDAGMI::schedule() {
621 buildDAGWithRegPressure();
623 Topo.InitDAGTopologicalSorting();
627 SmallVector<SUnit*, 8> TopRoots, BotRoots;
628 findRootsAndBiasEdges(TopRoots, BotRoots);
630 // Initialize the strategy before modifying the DAG.
631 // This may initialize a DFSResult to be used for queue priority.
632 SchedImpl->initialize(this);
634 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
635 SUnits[su].dumpAll(this));
636 if (ViewMISchedDAGs) viewGraph();
638 // Initialize ready queues now that the DAG and priority data are finalized.
639 initQueues(TopRoots, BotRoots);
641 bool IsTopNode = false;
642 while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) {
643 assert(!SU->isScheduled && "Node already scheduled");
644 if (!checkSchedLimit())
647 scheduleMI(SU, IsTopNode);
649 updateQueues(SU, IsTopNode);
651 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
656 unsigned BBNum = begin()->getParent()->getNumber();
657 dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
663 /// Build the DAG and setup three register pressure trackers.
664 void ScheduleDAGMI::buildDAGWithRegPressure() {
665 if (!ShouldTrackPressure) {
667 RegionCriticalPSets.clear();
672 // Initialize the register pressure tracker used by buildSchedGraph.
673 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd,
674 /*TrackUntiedDefs=*/true);
676 // Account for liveness generate by the region boundary.
677 if (LiveRegionEnd != RegionEnd)
680 // Build the DAG, and compute current register pressure.
681 buildSchedGraph(AA, &RPTracker, &SUPressureDiffs);
683 // Initialize top/bottom trackers after computing region pressure.
687 /// Apply each ScheduleDAGMutation step in order.
688 void ScheduleDAGMI::postprocessDAG() {
689 for (unsigned i = 0, e = Mutations.size(); i < e; ++i) {
690 Mutations[i]->apply(this);
694 void ScheduleDAGMI::computeDFSResult() {
696 DFSResult = new SchedDFSResult(/*BottomU*/true, MinSubtreeSize);
698 ScheduledTrees.clear();
699 DFSResult->resize(SUnits.size());
700 DFSResult->compute(SUnits);
701 ScheduledTrees.resize(DFSResult->getNumSubtrees());
704 void ScheduleDAGMI::findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots,
705 SmallVectorImpl<SUnit*> &BotRoots) {
706 for (std::vector<SUnit>::iterator
707 I = SUnits.begin(), E = SUnits.end(); I != E; ++I) {
709 assert(!SU->isBoundaryNode() && "Boundary node should not be in SUnits");
711 // Order predecessors so DFSResult follows the critical path.
712 SU->biasCriticalPath();
714 // A SUnit is ready to top schedule if it has no predecessors.
715 if (!I->NumPredsLeft)
716 TopRoots.push_back(SU);
717 // A SUnit is ready to bottom schedule if it has no successors.
718 if (!I->NumSuccsLeft)
719 BotRoots.push_back(SU);
721 ExitSU.biasCriticalPath();
724 /// Compute the max cyclic critical path through the DAG. The scheduling DAG
725 /// only provides the critical path for single block loops. To handle loops that
726 /// span blocks, we could use the vreg path latencies provided by
727 /// MachineTraceMetrics instead. However, MachineTraceMetrics is not currently
728 /// available for use in the scheduler.
730 /// The cyclic path estimation identifies a def-use pair that crosses the back
731 /// edge and considers the depth and height of the nodes. For example, consider
732 /// the following instruction sequence where each instruction has unit latency
733 /// and defines an epomymous virtual register:
735 /// a->b(a,c)->c(b)->d(c)->exit
737 /// The cyclic critical path is a two cycles: b->c->b
738 /// The acyclic critical path is four cycles: a->b->c->d->exit
739 /// LiveOutHeight = height(c) = len(c->d->exit) = 2
740 /// LiveOutDepth = depth(c) + 1 = len(a->b->c) + 1 = 3
741 /// LiveInHeight = height(b) + 1 = len(b->c->d->exit) + 1 = 4
742 /// LiveInDepth = depth(b) = len(a->b) = 1
744 /// LiveOutDepth - LiveInDepth = 3 - 1 = 2
745 /// LiveInHeight - LiveOutHeight = 4 - 2 = 2
746 /// CyclicCriticalPath = min(2, 2) = 2
747 unsigned ScheduleDAGMI::computeCyclicCriticalPath() {
748 // This only applies to single block loop.
749 if (!BB->isSuccessor(BB))
752 unsigned MaxCyclicLatency = 0;
753 // Visit each live out vreg def to find def/use pairs that cross iterations.
754 ArrayRef<unsigned> LiveOuts = RPTracker.getPressure().LiveOutRegs;
755 for (ArrayRef<unsigned>::iterator RI = LiveOuts.begin(), RE = LiveOuts.end();
758 if (!TRI->isVirtualRegister(Reg))
760 const LiveInterval &LI = LIS->getInterval(Reg);
761 const VNInfo *DefVNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
765 MachineInstr *DefMI = LIS->getInstructionFromIndex(DefVNI->def);
766 const SUnit *DefSU = getSUnit(DefMI);
770 unsigned LiveOutHeight = DefSU->getHeight();
771 unsigned LiveOutDepth = DefSU->getDepth() + DefSU->Latency;
772 // Visit all local users of the vreg def.
773 for (VReg2UseMap::iterator
774 UI = VRegUses.find(Reg); UI != VRegUses.end(); ++UI) {
775 if (UI->SU == &ExitSU)
778 // Only consider uses of the phi.
779 LiveRangeQuery LRQ(LI, LIS->getInstructionIndex(UI->SU->getInstr()));
780 if (!LRQ.valueIn()->isPHIDef())
783 // Assume that a path spanning two iterations is a cycle, which could
784 // overestimate in strange cases. This allows cyclic latency to be
785 // estimated as the minimum slack of the vreg's depth or height.
786 unsigned CyclicLatency = 0;
787 if (LiveOutDepth > UI->SU->getDepth())
788 CyclicLatency = LiveOutDepth - UI->SU->getDepth();
790 unsigned LiveInHeight = UI->SU->getHeight() + DefSU->Latency;
791 if (LiveInHeight > LiveOutHeight) {
792 if (LiveInHeight - LiveOutHeight < CyclicLatency)
793 CyclicLatency = LiveInHeight - LiveOutHeight;
798 DEBUG(dbgs() << "Cyclic Path: SU(" << DefSU->NodeNum << ") -> SU("
799 << UI->SU->NodeNum << ") = " << CyclicLatency << "c\n");
800 if (CyclicLatency > MaxCyclicLatency)
801 MaxCyclicLatency = CyclicLatency;
804 DEBUG(dbgs() << "Cyclic Critical Path: " << MaxCyclicLatency << "c\n");
805 return MaxCyclicLatency;
808 /// Identify DAG roots and setup scheduler queues.
809 void ScheduleDAGMI::initQueues(ArrayRef<SUnit*> TopRoots,
810 ArrayRef<SUnit*> BotRoots) {
811 NextClusterSucc = NULL;
812 NextClusterPred = NULL;
814 // Release all DAG roots for scheduling, not including EntrySU/ExitSU.
816 // Nodes with unreleased weak edges can still be roots.
817 // Release top roots in forward order.
818 for (SmallVectorImpl<SUnit*>::const_iterator
819 I = TopRoots.begin(), E = TopRoots.end(); I != E; ++I) {
820 SchedImpl->releaseTopNode(*I);
822 // Release bottom roots in reverse order so the higher priority nodes appear
823 // first. This is more natural and slightly more efficient.
824 for (SmallVectorImpl<SUnit*>::const_reverse_iterator
825 I = BotRoots.rbegin(), E = BotRoots.rend(); I != E; ++I) {
826 SchedImpl->releaseBottomNode(*I);
829 releaseSuccessors(&EntrySU);
830 releasePredecessors(&ExitSU);
832 SchedImpl->registerRoots();
834 // Advance past initial DebugValues.
835 CurrentTop = nextIfDebug(RegionBegin, RegionEnd);
836 CurrentBottom = RegionEnd;
838 if (ShouldTrackPressure) {
839 assert(TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker");
840 TopRPTracker.setPos(CurrentTop);
844 /// Move an instruction and update register pressure.
845 void ScheduleDAGMI::scheduleMI(SUnit *SU, bool IsTopNode) {
846 // Move the instruction to its new location in the instruction stream.
847 MachineInstr *MI = SU->getInstr();
850 assert(SU->isTopReady() && "node still has unscheduled dependencies");
851 if (&*CurrentTop == MI)
852 CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);
854 moveInstruction(MI, CurrentTop);
855 TopRPTracker.setPos(MI);
858 if (ShouldTrackPressure) {
859 // Update top scheduled pressure.
860 TopRPTracker.advance();
861 assert(TopRPTracker.getPos() == CurrentTop && "out of sync");
862 updateScheduledPressure(TopRPTracker.getPressure().MaxSetPressure);
866 assert(SU->isBottomReady() && "node still has unscheduled dependencies");
867 MachineBasicBlock::iterator priorII =
868 priorNonDebug(CurrentBottom, CurrentTop);
870 CurrentBottom = priorII;
872 if (&*CurrentTop == MI) {
873 CurrentTop = nextIfDebug(++CurrentTop, priorII);
874 TopRPTracker.setPos(CurrentTop);
876 moveInstruction(MI, CurrentBottom);
879 if (ShouldTrackPressure) {
880 // Update bottom scheduled pressure.
881 SmallVector<unsigned, 8> LiveUses;
882 BotRPTracker.recede(&LiveUses);
883 assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
884 updatePressureDiffs(LiveUses);
885 updateScheduledPressure(BotRPTracker.getPressure().MaxSetPressure);
890 /// Update scheduler queues after scheduling an instruction.
891 void ScheduleDAGMI::updateQueues(SUnit *SU, bool IsTopNode) {
892 // Release dependent instructions for scheduling.
894 releaseSuccessors(SU);
896 releasePredecessors(SU);
898 SU->isScheduled = true;
901 unsigned SubtreeID = DFSResult->getSubtreeID(SU);
902 if (!ScheduledTrees.test(SubtreeID)) {
903 ScheduledTrees.set(SubtreeID);
904 DFSResult->scheduleTree(SubtreeID);
905 SchedImpl->scheduleTree(SubtreeID);
909 // Notify the scheduling strategy after updating the DAG.
910 SchedImpl->schedNode(SU, IsTopNode);
913 /// Reinsert any remaining debug_values, just like the PostRA scheduler.
914 void ScheduleDAGMI::placeDebugValues() {
915 // If first instruction was a DBG_VALUE then put it back.
917 BB->splice(RegionBegin, BB, FirstDbgValue);
918 RegionBegin = FirstDbgValue;
921 for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
922 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
923 std::pair<MachineInstr *, MachineInstr *> P = *prior(DI);
924 MachineInstr *DbgValue = P.first;
925 MachineBasicBlock::iterator OrigPrevMI = P.second;
926 if (&*RegionBegin == DbgValue)
928 BB->splice(++OrigPrevMI, BB, DbgValue);
929 if (OrigPrevMI == llvm::prior(RegionEnd))
930 RegionEnd = DbgValue;
933 FirstDbgValue = NULL;
936 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
937 void ScheduleDAGMI::dumpSchedule() const {
938 for (MachineBasicBlock::iterator MI = begin(), ME = end(); MI != ME; ++MI) {
939 if (SUnit *SU = getSUnit(&(*MI)))
942 dbgs() << "Missing SUnit\n";
947 //===----------------------------------------------------------------------===//
948 // LoadClusterMutation - DAG post-processing to cluster loads.
949 //===----------------------------------------------------------------------===//
952 /// \brief Post-process the DAG to create cluster edges between neighboring
954 class LoadClusterMutation : public ScheduleDAGMutation {
959 LoadInfo(SUnit *su, unsigned reg, unsigned ofs)
960 : SU(su), BaseReg(reg), Offset(ofs) {}
962 static bool LoadInfoLess(const LoadClusterMutation::LoadInfo &LHS,
963 const LoadClusterMutation::LoadInfo &RHS);
965 const TargetInstrInfo *TII;
966 const TargetRegisterInfo *TRI;
968 LoadClusterMutation(const TargetInstrInfo *tii,
969 const TargetRegisterInfo *tri)
970 : TII(tii), TRI(tri) {}
972 virtual void apply(ScheduleDAGMI *DAG);
974 void clusterNeighboringLoads(ArrayRef<SUnit*> Loads, ScheduleDAGMI *DAG);
978 bool LoadClusterMutation::LoadInfoLess(
979 const LoadClusterMutation::LoadInfo &LHS,
980 const LoadClusterMutation::LoadInfo &RHS) {
981 if (LHS.BaseReg != RHS.BaseReg)
982 return LHS.BaseReg < RHS.BaseReg;
983 return LHS.Offset < RHS.Offset;
986 void LoadClusterMutation::clusterNeighboringLoads(ArrayRef<SUnit*> Loads,
987 ScheduleDAGMI *DAG) {
988 SmallVector<LoadClusterMutation::LoadInfo,32> LoadRecords;
989 for (unsigned Idx = 0, End = Loads.size(); Idx != End; ++Idx) {
990 SUnit *SU = Loads[Idx];
993 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
994 LoadRecords.push_back(LoadInfo(SU, BaseReg, Offset));
996 if (LoadRecords.size() < 2)
998 std::sort(LoadRecords.begin(), LoadRecords.end(), LoadInfoLess);
999 unsigned ClusterLength = 1;
1000 for (unsigned Idx = 0, End = LoadRecords.size(); Idx < (End - 1); ++Idx) {
1001 if (LoadRecords[Idx].BaseReg != LoadRecords[Idx+1].BaseReg) {
1006 SUnit *SUa = LoadRecords[Idx].SU;
1007 SUnit *SUb = LoadRecords[Idx+1].SU;
1008 if (TII->shouldClusterLoads(SUa->getInstr(), SUb->getInstr(), ClusterLength)
1009 && DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
1011 DEBUG(dbgs() << "Cluster loads SU(" << SUa->NodeNum << ") - SU("
1012 << SUb->NodeNum << ")\n");
1013 // Copy successor edges from SUa to SUb. Interleaving computation
1014 // dependent on SUa can prevent load combining due to register reuse.
1015 // Predecessor edges do not need to be copied from SUb to SUa since nearby
1016 // loads should have effectively the same inputs.
1017 for (SUnit::const_succ_iterator
1018 SI = SUa->Succs.begin(), SE = SUa->Succs.end(); SI != SE; ++SI) {
1019 if (SI->getSUnit() == SUb)
1021 DEBUG(dbgs() << " Copy Succ SU(" << SI->getSUnit()->NodeNum << ")\n");
1022 DAG->addEdge(SI->getSUnit(), SDep(SUb, SDep::Artificial));
1031 /// \brief Callback from DAG postProcessing to create cluster edges for loads.
1032 void LoadClusterMutation::apply(ScheduleDAGMI *DAG) {
1033 // Map DAG NodeNum to store chain ID.
1034 DenseMap<unsigned, unsigned> StoreChainIDs;
1035 // Map each store chain to a set of dependent loads.
1036 SmallVector<SmallVector<SUnit*,4>, 32> StoreChainDependents;
1037 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
1038 SUnit *SU = &DAG->SUnits[Idx];
1039 if (!SU->getInstr()->mayLoad())
1041 unsigned ChainPredID = DAG->SUnits.size();
1042 for (SUnit::const_pred_iterator
1043 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) {
1045 ChainPredID = PI->getSUnit()->NodeNum;
1049 // Check if this chain-like pred has been seen
1050 // before. ChainPredID==MaxNodeID for loads at the top of the schedule.
1051 unsigned NumChains = StoreChainDependents.size();
1052 std::pair<DenseMap<unsigned, unsigned>::iterator, bool> Result =
1053 StoreChainIDs.insert(std::make_pair(ChainPredID, NumChains));
1055 StoreChainDependents.resize(NumChains + 1);
1056 StoreChainDependents[Result.first->second].push_back(SU);
1058 // Iterate over the store chains.
1059 for (unsigned Idx = 0, End = StoreChainDependents.size(); Idx != End; ++Idx)
1060 clusterNeighboringLoads(StoreChainDependents[Idx], DAG);
1063 //===----------------------------------------------------------------------===//
1064 // MacroFusion - DAG post-processing to encourage fusion of macro ops.
1065 //===----------------------------------------------------------------------===//
1068 /// \brief Post-process the DAG to create cluster edges between instructions
1069 /// that may be fused by the processor into a single operation.
1070 class MacroFusion : public ScheduleDAGMutation {
1071 const TargetInstrInfo *TII;
1073 MacroFusion(const TargetInstrInfo *tii): TII(tii) {}
1075 virtual void apply(ScheduleDAGMI *DAG);
1079 /// \brief Callback from DAG postProcessing to create cluster edges to encourage
1080 /// fused operations.
1081 void MacroFusion::apply(ScheduleDAGMI *DAG) {
1082 // For now, assume targets can only fuse with the branch.
1083 MachineInstr *Branch = DAG->ExitSU.getInstr();
1087 for (unsigned Idx = DAG->SUnits.size(); Idx > 0;) {
1088 SUnit *SU = &DAG->SUnits[--Idx];
1089 if (!TII->shouldScheduleAdjacent(SU->getInstr(), Branch))
1092 // Create a single weak edge from SU to ExitSU. The only effect is to cause
1093 // bottom-up scheduling to heavily prioritize the clustered SU. There is no
1094 // need to copy predecessor edges from ExitSU to SU, since top-down
1095 // scheduling cannot prioritize ExitSU anyway. To defer top-down scheduling
1096 // of SU, we could create an artificial edge from the deepest root, but it
1097 // hasn't been needed yet.
1098 bool Success = DAG->addEdge(&DAG->ExitSU, SDep(SU, SDep::Cluster));
1100 assert(Success && "No DAG nodes should be reachable from ExitSU");
1102 DEBUG(dbgs() << "Macro Fuse SU(" << SU->NodeNum << ")\n");
1107 //===----------------------------------------------------------------------===//
1108 // CopyConstrain - DAG post-processing to encourage copy elimination.
1109 //===----------------------------------------------------------------------===//
1112 /// \brief Post-process the DAG to create weak edges from all uses of a copy to
1113 /// the one use that defines the copy's source vreg, most likely an induction
1114 /// variable increment.
1115 class CopyConstrain : public ScheduleDAGMutation {
1117 SlotIndex RegionBeginIdx;
1118 // RegionEndIdx is the slot index of the last non-debug instruction in the
1119 // scheduling region. So we may have RegionBeginIdx == RegionEndIdx.
1120 SlotIndex RegionEndIdx;
1122 CopyConstrain(const TargetInstrInfo *, const TargetRegisterInfo *) {}
1124 virtual void apply(ScheduleDAGMI *DAG);
1127 void constrainLocalCopy(SUnit *CopySU, ScheduleDAGMI *DAG);
1131 /// constrainLocalCopy handles two possibilities:
1136 /// I3: dst = src (copy)
1137 /// (create pred->succ edges I0->I1, I2->I1)
1140 /// I0: dst = src (copy)
1144 /// (create pred->succ edges I1->I2, I3->I2)
1146 /// Although the MachineScheduler is currently constrained to single blocks,
1147 /// this algorithm should handle extended blocks. An EBB is a set of
1148 /// contiguously numbered blocks such that the previous block in the EBB is
1149 /// always the single predecessor.
1150 void CopyConstrain::constrainLocalCopy(SUnit *CopySU, ScheduleDAGMI *DAG) {
1151 LiveIntervals *LIS = DAG->getLIS();
1152 MachineInstr *Copy = CopySU->getInstr();
1154 // Check for pure vreg copies.
1155 unsigned SrcReg = Copy->getOperand(1).getReg();
1156 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
1159 unsigned DstReg = Copy->getOperand(0).getReg();
1160 if (!TargetRegisterInfo::isVirtualRegister(DstReg))
1163 // Check if either the dest or source is local. If it's live across a back
1164 // edge, it's not local. Note that if both vregs are live across the back
1165 // edge, we cannot successfully contrain the copy without cyclic scheduling.
1166 unsigned LocalReg = DstReg;
1167 unsigned GlobalReg = SrcReg;
1168 LiveInterval *LocalLI = &LIS->getInterval(LocalReg);
1169 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx)) {
1172 LocalLI = &LIS->getInterval(LocalReg);
1173 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx))
1176 LiveInterval *GlobalLI = &LIS->getInterval(GlobalReg);
1178 // Find the global segment after the start of the local LI.
1179 LiveInterval::iterator GlobalSegment = GlobalLI->find(LocalLI->beginIndex());
1180 // If GlobalLI does not overlap LocalLI->start, then a copy directly feeds a
1181 // local live range. We could create edges from other global uses to the local
1182 // start, but the coalescer should have already eliminated these cases, so
1183 // don't bother dealing with it.
1184 if (GlobalSegment == GlobalLI->end())
1187 // If GlobalSegment is killed at the LocalLI->start, the call to find()
1188 // returned the next global segment. But if GlobalSegment overlaps with
1189 // LocalLI->start, then advance to the next segement. If a hole in GlobalLI
1190 // exists in LocalLI's vicinity, GlobalSegment will be the end of the hole.
1191 if (GlobalSegment->contains(LocalLI->beginIndex()))
1194 if (GlobalSegment == GlobalLI->end())
1197 // Check if GlobalLI contains a hole in the vicinity of LocalLI.
1198 if (GlobalSegment != GlobalLI->begin()) {
1199 // Two address defs have no hole.
1200 if (SlotIndex::isSameInstr(llvm::prior(GlobalSegment)->end,
1201 GlobalSegment->start)) {
1204 // If the prior global segment may be defined by the same two-address
1205 // instruction that also defines LocalLI, then can't make a hole here.
1206 if (SlotIndex::isSameInstr(llvm::prior(GlobalSegment)->start,
1207 LocalLI->beginIndex())) {
1210 // If GlobalLI has a prior segment, it must be live into the EBB. Otherwise
1211 // it would be a disconnected component in the live range.
1212 assert(llvm::prior(GlobalSegment)->start < LocalLI->beginIndex() &&
1213 "Disconnected LRG within the scheduling region.");
1215 MachineInstr *GlobalDef = LIS->getInstructionFromIndex(GlobalSegment->start);
1219 SUnit *GlobalSU = DAG->getSUnit(GlobalDef);
1223 // GlobalDef is the bottom of the GlobalLI hole. Open the hole by
1224 // constraining the uses of the last local def to precede GlobalDef.
1225 SmallVector<SUnit*,8> LocalUses;
1226 const VNInfo *LastLocalVN = LocalLI->getVNInfoBefore(LocalLI->endIndex());
1227 MachineInstr *LastLocalDef = LIS->getInstructionFromIndex(LastLocalVN->def);
1228 SUnit *LastLocalSU = DAG->getSUnit(LastLocalDef);
1229 for (SUnit::const_succ_iterator
1230 I = LastLocalSU->Succs.begin(), E = LastLocalSU->Succs.end();
1232 if (I->getKind() != SDep::Data || I->getReg() != LocalReg)
1234 if (I->getSUnit() == GlobalSU)
1236 if (!DAG->canAddEdge(GlobalSU, I->getSUnit()))
1238 LocalUses.push_back(I->getSUnit());
1240 // Open the top of the GlobalLI hole by constraining any earlier global uses
1241 // to precede the start of LocalLI.
1242 SmallVector<SUnit*,8> GlobalUses;
1243 MachineInstr *FirstLocalDef =
1244 LIS->getInstructionFromIndex(LocalLI->beginIndex());
1245 SUnit *FirstLocalSU = DAG->getSUnit(FirstLocalDef);
1246 for (SUnit::const_pred_iterator
1247 I = GlobalSU->Preds.begin(), E = GlobalSU->Preds.end(); I != E; ++I) {
1248 if (I->getKind() != SDep::Anti || I->getReg() != GlobalReg)
1250 if (I->getSUnit() == FirstLocalSU)
1252 if (!DAG->canAddEdge(FirstLocalSU, I->getSUnit()))
1254 GlobalUses.push_back(I->getSUnit());
1256 DEBUG(dbgs() << "Constraining copy SU(" << CopySU->NodeNum << ")\n");
1257 // Add the weak edges.
1258 for (SmallVectorImpl<SUnit*>::const_iterator
1259 I = LocalUses.begin(), E = LocalUses.end(); I != E; ++I) {
1260 DEBUG(dbgs() << " Local use SU(" << (*I)->NodeNum << ") -> SU("
1261 << GlobalSU->NodeNum << ")\n");
1262 DAG->addEdge(GlobalSU, SDep(*I, SDep::Weak));
1264 for (SmallVectorImpl<SUnit*>::const_iterator
1265 I = GlobalUses.begin(), E = GlobalUses.end(); I != E; ++I) {
1266 DEBUG(dbgs() << " Global use SU(" << (*I)->NodeNum << ") -> SU("
1267 << FirstLocalSU->NodeNum << ")\n");
1268 DAG->addEdge(FirstLocalSU, SDep(*I, SDep::Weak));
1272 /// \brief Callback from DAG postProcessing to create weak edges to encourage
1273 /// copy elimination.
1274 void CopyConstrain::apply(ScheduleDAGMI *DAG) {
1275 MachineBasicBlock::iterator FirstPos = nextIfDebug(DAG->begin(), DAG->end());
1276 if (FirstPos == DAG->end())
1278 RegionBeginIdx = DAG->getLIS()->getInstructionIndex(&*FirstPos);
1279 RegionEndIdx = DAG->getLIS()->getInstructionIndex(
1280 &*priorNonDebug(DAG->end(), DAG->begin()));
1282 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
1283 SUnit *SU = &DAG->SUnits[Idx];
1284 if (!SU->getInstr()->isCopy())
1287 constrainLocalCopy(SU, DAG);
1291 //===----------------------------------------------------------------------===//
1292 // ConvergingScheduler - Implementation of the generic MachineSchedStrategy.
1293 //===----------------------------------------------------------------------===//
1296 /// ConvergingScheduler shrinks the unscheduled zone using heuristics to balance
1298 class ConvergingScheduler : public MachineSchedStrategy {
1300 /// Represent the type of SchedCandidate found within a single queue.
1301 /// pickNodeBidirectional depends on these listed by decreasing priority.
1303 NoCand, PhysRegCopy, RegExcess, RegCritical, Cluster, Weak, RegMax,
1304 ResourceReduce, ResourceDemand, BotHeightReduce, BotPathReduce,
1305 TopDepthReduce, TopPathReduce, NextDefUse, NodeOrder};
1308 static const char *getReasonStr(ConvergingScheduler::CandReason Reason);
1311 /// Policy for scheduling the next instruction in the candidate's zone.
1314 unsigned ReduceResIdx;
1315 unsigned DemandResIdx;
1317 CandPolicy(): ReduceLatency(false), ReduceResIdx(0), DemandResIdx(0) {}
1320 /// Status of an instruction's critical resource consumption.
1321 struct SchedResourceDelta {
1322 // Count critical resources in the scheduled region required by SU.
1323 unsigned CritResources;
1325 // Count critical resources from another region consumed by SU.
1326 unsigned DemandedResources;
1328 SchedResourceDelta(): CritResources(0), DemandedResources(0) {}
1330 bool operator==(const SchedResourceDelta &RHS) const {
1331 return CritResources == RHS.CritResources
1332 && DemandedResources == RHS.DemandedResources;
1334 bool operator!=(const SchedResourceDelta &RHS) const {
1335 return !operator==(RHS);
1339 /// Store the state used by ConvergingScheduler heuristics, required for the
1340 /// lifetime of one invocation of pickNode().
1341 struct SchedCandidate {
1344 // The best SUnit candidate.
1347 // The reason for this candidate.
1350 // Set of reasons that apply to multiple candidates.
1351 uint32_t RepeatReasonSet;
1353 // Register pressure values for the best candidate.
1354 RegPressureDelta RPDelta;
1356 // Critical resource consumption of the best candidate.
1357 SchedResourceDelta ResDelta;
1359 SchedCandidate(const CandPolicy &policy)
1360 : Policy(policy), SU(NULL), Reason(NoCand), RepeatReasonSet(0) {}
1362 bool isValid() const { return SU; }
1364 // Copy the status of another candidate without changing policy.
1365 void setBest(SchedCandidate &Best) {
1366 assert(Best.Reason != NoCand && "uninitialized Sched candidate");
1368 Reason = Best.Reason;
1369 RPDelta = Best.RPDelta;
1370 ResDelta = Best.ResDelta;
1373 bool isRepeat(CandReason R) { return RepeatReasonSet & (1 << R); }
1374 void setRepeat(CandReason R) { RepeatReasonSet |= (1 << R); }
1376 void initResourceDelta(const ScheduleDAGMI *DAG,
1377 const TargetSchedModel *SchedModel);
1380 /// Summarize the unscheduled region.
1381 struct SchedRemainder {
1382 // Critical path through the DAG in expected latency.
1383 unsigned CriticalPath;
1384 unsigned CyclicCritPath;
1386 // Scaled count of micro-ops left to schedule.
1387 unsigned RemIssueCount;
1389 bool IsAcyclicLatencyLimited;
1391 // Unscheduled resources
1392 SmallVector<unsigned, 16> RemainingCounts;
1398 IsAcyclicLatencyLimited = false;
1399 RemainingCounts.clear();
1402 SchedRemainder() { reset(); }
1404 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
1407 /// Each Scheduling boundary is associated with ready queues. It tracks the
1408 /// current cycle in the direction of movement, and maintains the state
1409 /// of "hazards" and other interlocks at the current cycle.
1410 struct SchedBoundary {
1412 const TargetSchedModel *SchedModel;
1413 SchedRemainder *Rem;
1415 ReadyQueue Available;
1419 // For heuristics, keep a list of the nodes that immediately depend on the
1420 // most recently scheduled node.
1421 SmallPtrSet<const SUnit*, 8> NextSUs;
1423 ScheduleHazardRecognizer *HazardRec;
1425 /// Number of cycles it takes to issue the instructions scheduled in this
1426 /// zone. It is defined as: scheduled-micro-ops / issue-width + stalls.
1427 /// See getStalls().
1430 /// Micro-ops issued in the current cycle
1433 /// MinReadyCycle - Cycle of the soonest available instruction.
1434 unsigned MinReadyCycle;
1436 // The expected latency of the critical path in this scheduled zone.
1437 unsigned ExpectedLatency;
1439 // The latency of dependence chains leading into this zone.
1440 // For each node scheduled bottom-up: DLat = max DLat, N.Depth.
1441 // For each cycle scheduled: DLat -= 1.
1442 unsigned DependentLatency;
1444 /// Count the scheduled (issued) micro-ops that can be retired by
1445 /// time=CurrCycle assuming the first scheduled instr is retired at time=0.
1446 unsigned RetiredMOps;
1448 // Count scheduled resources that have been executed. Resources are
1449 // considered executed if they become ready in the time that it takes to
1450 // saturate any resource including the one in question. Counts are scaled
1451 // for direct comparison with other resources. Counts can be compared with
1452 // MOps * getMicroOpFactor and Latency * getLatencyFactor.
1453 SmallVector<unsigned, 16> ExecutedResCounts;
1455 /// Cache the max count for a single resource.
1456 unsigned MaxExecutedResCount;
1458 // Cache the critical resources ID in this scheduled zone.
1459 unsigned ZoneCritResIdx;
1461 // Is the scheduled region resource limited vs. latency limited.
1462 bool IsResourceLimited;
1465 // Remember the greatest operand latency as an upper bound on the number of
1466 // times we should retry the pending queue because of a hazard.
1467 unsigned MaxObservedLatency;
1471 // A new HazardRec is created for each DAG and owned by SchedBoundary.
1472 // Detroying and reconstructing it is very expensive though. So keep
1473 // invalid, placeholder HazardRecs.
1474 if (HazardRec && HazardRec->isEnabled()) {
1480 CheckPending = false;
1484 MinReadyCycle = UINT_MAX;
1485 ExpectedLatency = 0;
1486 DependentLatency = 0;
1488 MaxExecutedResCount = 0;
1490 IsResourceLimited = false;
1492 MaxObservedLatency = 0;
1494 // Reserve a zero-count for invalid CritResIdx.
1495 ExecutedResCounts.resize(1);
1496 assert(!ExecutedResCounts[0] && "nonzero count for bad resource");
1499 /// Pending queues extend the ready queues with the same ID and the
1500 /// PendingFlag set.
1501 SchedBoundary(unsigned ID, const Twine &Name):
1502 DAG(0), SchedModel(0), Rem(0), Available(ID, Name+".A"),
1503 Pending(ID << ConvergingScheduler::LogMaxQID, Name+".P"),
1508 ~SchedBoundary() { delete HazardRec; }
1510 void init(ScheduleDAGMI *dag, const TargetSchedModel *smodel,
1511 SchedRemainder *rem);
1513 bool isTop() const {
1514 return Available.getID() == ConvergingScheduler::TopQID;
1518 const char *getResourceName(unsigned PIdx) {
1521 return SchedModel->getProcResource(PIdx)->Name;
1525 /// Get the number of latency cycles "covered" by the scheduled
1526 /// instructions. This is the larger of the critical path within the zone
1527 /// and the number of cycles required to issue the instructions.
1528 unsigned getScheduledLatency() const {
1529 return std::max(ExpectedLatency, CurrCycle);
1532 unsigned getUnscheduledLatency(SUnit *SU) const {
1533 return isTop() ? SU->getHeight() : SU->getDepth();
1536 unsigned getResourceCount(unsigned ResIdx) const {
1537 return ExecutedResCounts[ResIdx];
1540 /// Get the scaled count of scheduled micro-ops and resources, including
1541 /// executed resources.
1542 unsigned getCriticalCount() const {
1543 if (!ZoneCritResIdx)
1544 return RetiredMOps * SchedModel->getMicroOpFactor();
1545 return getResourceCount(ZoneCritResIdx);
1548 /// Get a scaled count for the minimum execution time of the scheduled
1549 /// micro-ops that are ready to execute by getExecutedCount. Notice the
1551 unsigned getExecutedCount() const {
1552 return std::max(CurrCycle * SchedModel->getLatencyFactor(),
1553 MaxExecutedResCount);
1556 bool checkHazard(SUnit *SU);
1558 unsigned findMaxLatency(ArrayRef<SUnit*> ReadySUs);
1560 unsigned getOtherResourceCount(unsigned &OtherCritIdx);
1562 void setPolicy(CandPolicy &Policy, SchedBoundary &OtherZone);
1564 void releaseNode(SUnit *SU, unsigned ReadyCycle);
1566 void bumpCycle(unsigned NextCycle);
1568 void incExecutedResources(unsigned PIdx, unsigned Count);
1570 unsigned countResource(unsigned PIdx, unsigned Cycles, unsigned ReadyCycle);
1572 void bumpNode(SUnit *SU);
1574 void releasePending();
1576 void removeReady(SUnit *SU);
1578 SUnit *pickOnlyChoice();
1581 void dumpScheduledState();
1587 const TargetSchedModel *SchedModel;
1588 const TargetRegisterInfo *TRI;
1590 // State of the top and bottom scheduled instruction boundaries.
1596 /// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both)
1603 ConvergingScheduler():
1604 DAG(0), SchedModel(0), TRI(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
1606 virtual void initialize(ScheduleDAGMI *dag);
1608 virtual SUnit *pickNode(bool &IsTopNode);
1610 virtual void schedNode(SUnit *SU, bool IsTopNode);
1612 virtual void releaseTopNode(SUnit *SU);
1614 virtual void releaseBottomNode(SUnit *SU);
1616 virtual void registerRoots();
1619 void checkAcyclicLatency();
1621 void tryCandidate(SchedCandidate &Cand,
1622 SchedCandidate &TryCand,
1623 SchedBoundary &Zone,
1624 const RegPressureTracker &RPTracker,
1625 RegPressureTracker &TempTracker);
1627 SUnit *pickNodeBidirectional(bool &IsTopNode);
1629 void pickNodeFromQueue(SchedBoundary &Zone,
1630 const RegPressureTracker &RPTracker,
1631 SchedCandidate &Candidate);
1633 void reschedulePhysRegCopies(SUnit *SU, bool isTop);
1636 void traceCandidate(const SchedCandidate &Cand);
1641 void ConvergingScheduler::SchedRemainder::
1642 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) {
1644 if (!SchedModel->hasInstrSchedModel())
1646 RemainingCounts.resize(SchedModel->getNumProcResourceKinds());
1647 for (std::vector<SUnit>::iterator
1648 I = DAG->SUnits.begin(), E = DAG->SUnits.end(); I != E; ++I) {
1649 const MCSchedClassDesc *SC = DAG->getSchedClass(&*I);
1650 RemIssueCount += SchedModel->getNumMicroOps(I->getInstr(), SC)
1651 * SchedModel->getMicroOpFactor();
1652 for (TargetSchedModel::ProcResIter
1653 PI = SchedModel->getWriteProcResBegin(SC),
1654 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1655 unsigned PIdx = PI->ProcResourceIdx;
1656 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1657 RemainingCounts[PIdx] += (Factor * PI->Cycles);
1662 void ConvergingScheduler::SchedBoundary::
1663 init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem) {
1666 SchedModel = smodel;
1668 if (SchedModel->hasInstrSchedModel())
1669 ExecutedResCounts.resize(SchedModel->getNumProcResourceKinds());
1672 void ConvergingScheduler::initialize(ScheduleDAGMI *dag) {
1674 SchedModel = DAG->getSchedModel();
1677 Rem.init(DAG, SchedModel);
1678 Top.init(DAG, SchedModel, &Rem);
1679 Bot.init(DAG, SchedModel, &Rem);
1681 // Initialize resource counts.
1683 // Initialize the HazardRecognizers. If itineraries don't exist, are empty, or
1684 // are disabled, then these HazardRecs will be disabled.
1685 const InstrItineraryData *Itin = SchedModel->getInstrItineraries();
1686 const TargetMachine &TM = DAG->MF.getTarget();
1687 if (!Top.HazardRec) {
1689 TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
1691 if (!Bot.HazardRec) {
1693 TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
1695 assert((!ForceTopDown || !ForceBottomUp) &&
1696 "-misched-topdown incompatible with -misched-bottomup");
1699 void ConvergingScheduler::releaseTopNode(SUnit *SU) {
1700 if (SU->isScheduled)
1703 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1707 unsigned PredReadyCycle = I->getSUnit()->TopReadyCycle;
1708 unsigned Latency = I->getLatency();
1710 Top.MaxObservedLatency = std::max(Latency, Top.MaxObservedLatency);
1712 if (SU->TopReadyCycle < PredReadyCycle + Latency)
1713 SU->TopReadyCycle = PredReadyCycle + Latency;
1715 Top.releaseNode(SU, SU->TopReadyCycle);
1718 void ConvergingScheduler::releaseBottomNode(SUnit *SU) {
1719 if (SU->isScheduled)
1722 assert(SU->getInstr() && "Scheduled SUnit must have instr");
1724 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1728 unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle;
1729 unsigned Latency = I->getLatency();
1731 Bot.MaxObservedLatency = std::max(Latency, Bot.MaxObservedLatency);
1733 if (SU->BotReadyCycle < SuccReadyCycle + Latency)
1734 SU->BotReadyCycle = SuccReadyCycle + Latency;
1736 Bot.releaseNode(SU, SU->BotReadyCycle);
1739 /// Set IsAcyclicLatencyLimited if the acyclic path is longer than the cyclic
1740 /// critical path by more cycles than it takes to drain the instruction buffer.
1741 /// We estimate an upper bounds on in-flight instructions as:
1743 /// CyclesPerIteration = max( CyclicPath, Loop-Resource-Height )
1744 /// InFlightIterations = AcyclicPath / CyclesPerIteration
1745 /// InFlightResources = InFlightIterations * LoopResources
1747 /// TODO: Check execution resources in addition to IssueCount.
1748 void ConvergingScheduler::checkAcyclicLatency() {
1749 if (Rem.CyclicCritPath == 0 || Rem.CyclicCritPath >= Rem.CriticalPath)
1752 // Scaled number of cycles per loop iteration.
1753 unsigned IterCount =
1754 std::max(Rem.CyclicCritPath * SchedModel->getLatencyFactor(),
1756 // Scaled acyclic critical path.
1757 unsigned AcyclicCount = Rem.CriticalPath * SchedModel->getLatencyFactor();
1758 // InFlightCount = (AcyclicPath / IterCycles) * InstrPerLoop
1759 unsigned InFlightCount =
1760 (AcyclicCount * Rem.RemIssueCount + IterCount-1) / IterCount;
1761 unsigned BufferLimit =
1762 SchedModel->getMicroOpBufferSize() * SchedModel->getMicroOpFactor();
1764 Rem.IsAcyclicLatencyLimited = InFlightCount > BufferLimit;
1766 DEBUG(dbgs() << "IssueCycles="
1767 << Rem.RemIssueCount / SchedModel->getLatencyFactor() << "c "
1768 << "IterCycles=" << IterCount / SchedModel->getLatencyFactor()
1769 << "c NumIters=" << (AcyclicCount + IterCount-1) / IterCount
1770 << " InFlight=" << InFlightCount / SchedModel->getMicroOpFactor()
1771 << "m BufferLim=" << SchedModel->getMicroOpBufferSize() << "m\n";
1772 if (Rem.IsAcyclicLatencyLimited)
1773 dbgs() << " ACYCLIC LATENCY LIMIT\n");
1776 void ConvergingScheduler::registerRoots() {
1777 Rem.CriticalPath = DAG->ExitSU.getDepth();
1779 // Some roots may not feed into ExitSU. Check all of them in case.
1780 for (std::vector<SUnit*>::const_iterator
1781 I = Bot.Available.begin(), E = Bot.Available.end(); I != E; ++I) {
1782 if ((*I)->getDepth() > Rem.CriticalPath)
1783 Rem.CriticalPath = (*I)->getDepth();
1785 DEBUG(dbgs() << "Critical Path: " << Rem.CriticalPath << '\n');
1787 if (EnableCyclicPath) {
1788 Rem.CyclicCritPath = DAG->computeCyclicCriticalPath();
1789 checkAcyclicLatency();
1793 /// Does this SU have a hazard within the current instruction group.
1795 /// The scheduler supports two modes of hazard recognition. The first is the
1796 /// ScheduleHazardRecognizer API. It is a fully general hazard recognizer that
1797 /// supports highly complicated in-order reservation tables
1798 /// (ScoreboardHazardRecognizer) and arbitraty target-specific logic.
1800 /// The second is a streamlined mechanism that checks for hazards based on
1801 /// simple counters that the scheduler itself maintains. It explicitly checks
1802 /// for instruction dispatch limitations, including the number of micro-ops that
1803 /// can dispatch per cycle.
1805 /// TODO: Also check whether the SU must start a new group.
1806 bool ConvergingScheduler::SchedBoundary::checkHazard(SUnit *SU) {
1807 if (HazardRec->isEnabled())
1808 return HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard;
1810 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
1811 if ((CurrMOps > 0) && (CurrMOps + uops > SchedModel->getIssueWidth())) {
1812 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") uops="
1813 << SchedModel->getNumMicroOps(SU->getInstr()) << '\n');
1819 // Find the unscheduled node in ReadySUs with the highest latency.
1820 unsigned ConvergingScheduler::SchedBoundary::
1821 findMaxLatency(ArrayRef<SUnit*> ReadySUs) {
1823 unsigned RemLatency = 0;
1824 for (ArrayRef<SUnit*>::iterator I = ReadySUs.begin(), E = ReadySUs.end();
1826 unsigned L = getUnscheduledLatency(*I);
1827 if (L > RemLatency) {
1833 DEBUG(dbgs() << Available.getName() << " RemLatency SU("
1834 << LateSU->NodeNum << ") " << RemLatency << "c\n");
1839 // Count resources in this zone and the remaining unscheduled
1840 // instruction. Return the max count, scaled. Set OtherCritIdx to the critical
1841 // resource index, or zero if the zone is issue limited.
1842 unsigned ConvergingScheduler::SchedBoundary::
1843 getOtherResourceCount(unsigned &OtherCritIdx) {
1845 if (!SchedModel->hasInstrSchedModel())
1848 unsigned OtherCritCount = Rem->RemIssueCount
1849 + (RetiredMOps * SchedModel->getMicroOpFactor());
1850 DEBUG(dbgs() << " " << Available.getName() << " + Remain MOps: "
1851 << OtherCritCount / SchedModel->getMicroOpFactor() << '\n');
1852 for (unsigned PIdx = 1, PEnd = SchedModel->getNumProcResourceKinds();
1853 PIdx != PEnd; ++PIdx) {
1854 unsigned OtherCount = getResourceCount(PIdx) + Rem->RemainingCounts[PIdx];
1855 if (OtherCount > OtherCritCount) {
1856 OtherCritCount = OtherCount;
1857 OtherCritIdx = PIdx;
1861 DEBUG(dbgs() << " " << Available.getName() << " + Remain CritRes: "
1862 << OtherCritCount / SchedModel->getResourceFactor(OtherCritIdx)
1863 << " " << getResourceName(OtherCritIdx) << "\n");
1865 return OtherCritCount;
1868 /// Set the CandPolicy for this zone given the current resources and latencies
1869 /// inside and outside the zone.
1870 void ConvergingScheduler::SchedBoundary::setPolicy(CandPolicy &Policy,
1871 SchedBoundary &OtherZone) {
1872 // Now that potential stalls have been considered, apply preemptive heuristics
1873 // based on the the total latency and resources inside and outside this
1876 // Compute remaining latency. We need this both to determine whether the
1877 // overall schedule has become latency-limited and whether the instructions
1878 // outside this zone are resource or latency limited.
1880 // The "dependent" latency is updated incrementally during scheduling as the
1881 // max height/depth of scheduled nodes minus the cycles since it was
1883 // DLat = max (N.depth - (CurrCycle - N.ReadyCycle) for N in Zone
1885 // The "independent" latency is the max ready queue depth:
1886 // ILat = max N.depth for N in Available|Pending
1888 // RemainingLatency is the greater of independent and dependent latency.
1889 unsigned RemLatency = DependentLatency;
1890 RemLatency = std::max(RemLatency, findMaxLatency(Available.elements()));
1891 RemLatency = std::max(RemLatency, findMaxLatency(Pending.elements()));
1893 // Compute the critical resource outside the zone.
1894 unsigned OtherCritIdx;
1895 unsigned OtherCount = OtherZone.getOtherResourceCount(OtherCritIdx);
1897 bool OtherResLimited = false;
1898 if (SchedModel->hasInstrSchedModel()) {
1899 unsigned LFactor = SchedModel->getLatencyFactor();
1900 OtherResLimited = (int)(OtherCount - (RemLatency * LFactor)) > (int)LFactor;
1902 if (!OtherResLimited && (RemLatency + CurrCycle > Rem->CriticalPath)) {
1903 Policy.ReduceLatency |= true;
1904 DEBUG(dbgs() << " " << Available.getName() << " RemainingLatency "
1905 << RemLatency << " + " << CurrCycle << "c > CritPath "
1906 << Rem->CriticalPath << "\n");
1908 // If the same resource is limiting inside and outside the zone, do nothing.
1909 if (ZoneCritResIdx == OtherCritIdx)
1913 if (IsResourceLimited) {
1914 dbgs() << " " << Available.getName() << " ResourceLimited: "
1915 << getResourceName(ZoneCritResIdx) << "\n";
1917 if (OtherResLimited)
1918 dbgs() << " RemainingLimit: " << getResourceName(OtherCritIdx) << "\n";
1919 if (!IsResourceLimited && !OtherResLimited)
1920 dbgs() << " Latency limited both directions.\n");
1922 if (IsResourceLimited && !Policy.ReduceResIdx)
1923 Policy.ReduceResIdx = ZoneCritResIdx;
1925 if (OtherResLimited)
1926 Policy.DemandResIdx = OtherCritIdx;
1929 void ConvergingScheduler::SchedBoundary::releaseNode(SUnit *SU,
1930 unsigned ReadyCycle) {
1931 if (ReadyCycle < MinReadyCycle)
1932 MinReadyCycle = ReadyCycle;
1934 // Check for interlocks first. For the purpose of other heuristics, an
1935 // instruction that cannot issue appears as if it's not in the ReadyQueue.
1936 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
1937 if ((!IsBuffered && ReadyCycle > CurrCycle) || checkHazard(SU))
1942 // Record this node as an immediate dependent of the scheduled node.
1946 /// Move the boundary of scheduled code by one cycle.
1947 void ConvergingScheduler::SchedBoundary::bumpCycle(unsigned NextCycle) {
1948 if (SchedModel->getMicroOpBufferSize() == 0) {
1949 assert(MinReadyCycle < UINT_MAX && "MinReadyCycle uninitialized");
1950 if (MinReadyCycle > NextCycle)
1951 NextCycle = MinReadyCycle;
1953 // Update the current micro-ops, which will issue in the next cycle.
1954 unsigned DecMOps = SchedModel->getIssueWidth() * (NextCycle - CurrCycle);
1955 CurrMOps = (CurrMOps <= DecMOps) ? 0 : CurrMOps - DecMOps;
1957 // Decrement DependentLatency based on the next cycle.
1958 if ((NextCycle - CurrCycle) > DependentLatency)
1959 DependentLatency = 0;
1961 DependentLatency -= (NextCycle - CurrCycle);
1963 if (!HazardRec->isEnabled()) {
1964 // Bypass HazardRec virtual calls.
1965 CurrCycle = NextCycle;
1968 // Bypass getHazardType calls in case of long latency.
1969 for (; CurrCycle != NextCycle; ++CurrCycle) {
1971 HazardRec->AdvanceCycle();
1973 HazardRec->RecedeCycle();
1976 CheckPending = true;
1977 unsigned LFactor = SchedModel->getLatencyFactor();
1979 (int)(getCriticalCount() - (getScheduledLatency() * LFactor))
1982 DEBUG(dbgs() << "Cycle: " << CurrCycle << ' ' << Available.getName() << '\n');
1985 void ConvergingScheduler::SchedBoundary::incExecutedResources(unsigned PIdx,
1987 ExecutedResCounts[PIdx] += Count;
1988 if (ExecutedResCounts[PIdx] > MaxExecutedResCount)
1989 MaxExecutedResCount = ExecutedResCounts[PIdx];
1992 /// Add the given processor resource to this scheduled zone.
1994 /// \param Cycles indicates the number of consecutive (non-pipelined) cycles
1995 /// during which this resource is consumed.
1997 /// \return the next cycle at which the instruction may execute without
1998 /// oversubscribing resources.
1999 unsigned ConvergingScheduler::SchedBoundary::
2000 countResource(unsigned PIdx, unsigned Cycles, unsigned ReadyCycle) {
2001 unsigned Factor = SchedModel->getResourceFactor(PIdx);
2002 unsigned Count = Factor * Cycles;
2003 DEBUG(dbgs() << " " << getResourceName(PIdx)
2004 << " +" << Cycles << "x" << Factor << "u\n");
2006 // Update Executed resources counts.
2007 incExecutedResources(PIdx, Count);
2008 assert(Rem->RemainingCounts[PIdx] >= Count && "resource double counted");
2009 Rem->RemainingCounts[PIdx] -= Count;
2011 // Check if this resource exceeds the current critical resource. If so, it
2012 // becomes the critical resource.
2013 if (ZoneCritResIdx != PIdx && (getResourceCount(PIdx) > getCriticalCount())) {
2014 ZoneCritResIdx = PIdx;
2015 DEBUG(dbgs() << " *** Critical resource "
2016 << getResourceName(PIdx) << ": "
2017 << getResourceCount(PIdx) / SchedModel->getLatencyFactor() << "c\n");
2019 // TODO: We don't yet model reserved resources. It's not hard though.
2023 /// Move the boundary of scheduled code by one SUnit.
2024 void ConvergingScheduler::SchedBoundary::bumpNode(SUnit *SU) {
2025 // Update the reservation table.
2026 if (HazardRec->isEnabled()) {
2027 if (!isTop() && SU->isCall) {
2028 // Calls are scheduled with their preceding instructions. For bottom-up
2029 // scheduling, clear the pipeline state before emitting.
2032 HazardRec->EmitInstruction(SU);
2034 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
2035 unsigned IncMOps = SchedModel->getNumMicroOps(SU->getInstr());
2036 CurrMOps += IncMOps;
2037 // checkHazard prevents scheduling multiple instructions per cycle that exceed
2038 // issue width. However, we commonly reach the maximum. In this case
2039 // opportunistically bump the cycle to avoid uselessly checking everything in
2040 // the readyQ. Furthermore, a single instruction may produce more than one
2041 // cycle's worth of micro-ops.
2043 // TODO: Also check if this SU must end a dispatch group.
2044 unsigned NextCycle = CurrCycle;
2045 if (CurrMOps >= SchedModel->getIssueWidth()) {
2047 DEBUG(dbgs() << " *** Max MOps " << CurrMOps
2048 << " at cycle " << CurrCycle << '\n');
2050 unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle);
2051 DEBUG(dbgs() << " Ready @" << ReadyCycle << "c\n");
2053 switch (SchedModel->getMicroOpBufferSize()) {
2055 assert(ReadyCycle <= CurrCycle && "Broken PendingQueue");
2058 if (ReadyCycle > NextCycle) {
2059 NextCycle = ReadyCycle;
2060 DEBUG(dbgs() << " *** Stall until: " << ReadyCycle << "\n");
2064 // We don't currently model the OOO reorder buffer, so consider all
2065 // scheduled MOps to be "retired".
2068 RetiredMOps += IncMOps;
2070 // Update resource counts and critical resource.
2071 if (SchedModel->hasInstrSchedModel()) {
2072 unsigned DecRemIssue = IncMOps * SchedModel->getMicroOpFactor();
2073 assert(Rem->RemIssueCount >= DecRemIssue && "MOps double counted");
2074 Rem->RemIssueCount -= DecRemIssue;
2075 if (ZoneCritResIdx) {
2076 // Scale scheduled micro-ops for comparing with the critical resource.
2077 unsigned ScaledMOps =
2078 RetiredMOps * SchedModel->getMicroOpFactor();
2080 // If scaled micro-ops are now more than the previous critical resource by
2081 // a full cycle, then micro-ops issue becomes critical.
2082 if ((int)(ScaledMOps - getResourceCount(ZoneCritResIdx))
2083 >= (int)SchedModel->getLatencyFactor()) {
2085 DEBUG(dbgs() << " *** Critical resource NumMicroOps: "
2086 << ScaledMOps / SchedModel->getLatencyFactor() << "c\n");
2089 for (TargetSchedModel::ProcResIter
2090 PI = SchedModel->getWriteProcResBegin(SC),
2091 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
2093 countResource(PI->ProcResourceIdx, PI->Cycles, ReadyCycle);
2094 if (RCycle > NextCycle)
2098 // Update ExpectedLatency and DependentLatency.
2099 unsigned &TopLatency = isTop() ? ExpectedLatency : DependentLatency;
2100 unsigned &BotLatency = isTop() ? DependentLatency : ExpectedLatency;
2101 if (SU->getDepth() > TopLatency) {
2102 TopLatency = SU->getDepth();
2103 DEBUG(dbgs() << " " << Available.getName()
2104 << " TopLatency SU(" << SU->NodeNum << ") " << TopLatency << "c\n");
2106 if (SU->getHeight() > BotLatency) {
2107 BotLatency = SU->getHeight();
2108 DEBUG(dbgs() << " " << Available.getName()
2109 << " BotLatency SU(" << SU->NodeNum << ") " << BotLatency << "c\n");
2111 // If we stall for any reason, bump the cycle.
2112 if (NextCycle > CurrCycle) {
2113 bumpCycle(NextCycle);
2116 // After updating ZoneCritResIdx and ExpectedLatency, check if we're
2117 // resource limited. If a stall occured, bumpCycle does this.
2118 unsigned LFactor = SchedModel->getLatencyFactor();
2120 (int)(getCriticalCount() - (getScheduledLatency() * LFactor))
2123 DEBUG(dumpScheduledState());
2126 /// Release pending ready nodes in to the available queue. This makes them
2127 /// visible to heuristics.
2128 void ConvergingScheduler::SchedBoundary::releasePending() {
2129 // If the available queue is empty, it is safe to reset MinReadyCycle.
2130 if (Available.empty())
2131 MinReadyCycle = UINT_MAX;
2133 // Check to see if any of the pending instructions are ready to issue. If
2134 // so, add them to the available queue.
2135 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
2136 for (unsigned i = 0, e = Pending.size(); i != e; ++i) {
2137 SUnit *SU = *(Pending.begin()+i);
2138 unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle;
2140 if (ReadyCycle < MinReadyCycle)
2141 MinReadyCycle = ReadyCycle;
2143 if (!IsBuffered && ReadyCycle > CurrCycle)
2146 if (checkHazard(SU))
2150 Pending.remove(Pending.begin()+i);
2153 DEBUG(if (!Pending.empty()) Pending.dump());
2154 CheckPending = false;
2157 /// Remove SU from the ready set for this boundary.
2158 void ConvergingScheduler::SchedBoundary::removeReady(SUnit *SU) {
2159 if (Available.isInQueue(SU))
2160 Available.remove(Available.find(SU));
2162 assert(Pending.isInQueue(SU) && "bad ready count");
2163 Pending.remove(Pending.find(SU));
2167 /// If this queue only has one ready candidate, return it. As a side effect,
2168 /// defer any nodes that now hit a hazard, and advance the cycle until at least
2169 /// one node is ready. If multiple instructions are ready, return NULL.
2170 SUnit *ConvergingScheduler::SchedBoundary::pickOnlyChoice() {
2175 // Defer any ready instrs that now have a hazard.
2176 for (ReadyQueue::iterator I = Available.begin(); I != Available.end();) {
2177 if (checkHazard(*I)) {
2179 I = Available.remove(I);
2185 for (unsigned i = 0; Available.empty(); ++i) {
2186 assert(i <= (HazardRec->getMaxLookAhead() + MaxObservedLatency) &&
2187 "permanent hazard"); (void)i;
2188 bumpCycle(CurrCycle + 1);
2191 if (Available.size() == 1)
2192 return *Available.begin();
2197 // This is useful information to dump after bumpNode.
2198 // Note that the Queue contents are more useful before pickNodeFromQueue.
2199 void ConvergingScheduler::SchedBoundary::dumpScheduledState() {
2202 if (ZoneCritResIdx) {
2203 ResFactor = SchedModel->getResourceFactor(ZoneCritResIdx);
2204 ResCount = getResourceCount(ZoneCritResIdx);
2207 ResFactor = SchedModel->getMicroOpFactor();
2208 ResCount = RetiredMOps * SchedModel->getMicroOpFactor();
2210 unsigned LFactor = SchedModel->getLatencyFactor();
2211 dbgs() << Available.getName() << " @" << CurrCycle << "c\n"
2212 << " Retired: " << RetiredMOps;
2213 dbgs() << "\n Executed: " << getExecutedCount() / LFactor << "c";
2214 dbgs() << "\n Critical: " << ResCount / LFactor << "c, "
2215 << ResCount / ResFactor << " " << getResourceName(ZoneCritResIdx)
2216 << "\n ExpectedLatency: " << ExpectedLatency << "c\n"
2217 << (IsResourceLimited ? " - Resource" : " - Latency")
2222 void ConvergingScheduler::SchedCandidate::
2223 initResourceDelta(const ScheduleDAGMI *DAG,
2224 const TargetSchedModel *SchedModel) {
2225 if (!Policy.ReduceResIdx && !Policy.DemandResIdx)
2228 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
2229 for (TargetSchedModel::ProcResIter
2230 PI = SchedModel->getWriteProcResBegin(SC),
2231 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
2232 if (PI->ProcResourceIdx == Policy.ReduceResIdx)
2233 ResDelta.CritResources += PI->Cycles;
2234 if (PI->ProcResourceIdx == Policy.DemandResIdx)
2235 ResDelta.DemandedResources += PI->Cycles;
2240 /// Return true if this heuristic determines order.
2241 static bool tryLess(int TryVal, int CandVal,
2242 ConvergingScheduler::SchedCandidate &TryCand,
2243 ConvergingScheduler::SchedCandidate &Cand,
2244 ConvergingScheduler::CandReason Reason) {
2245 if (TryVal < CandVal) {
2246 TryCand.Reason = Reason;
2249 if (TryVal > CandVal) {
2250 if (Cand.Reason > Reason)
2251 Cand.Reason = Reason;
2254 Cand.setRepeat(Reason);
2258 static bool tryGreater(int TryVal, int CandVal,
2259 ConvergingScheduler::SchedCandidate &TryCand,
2260 ConvergingScheduler::SchedCandidate &Cand,
2261 ConvergingScheduler::CandReason Reason) {
2262 if (TryVal > CandVal) {
2263 TryCand.Reason = Reason;
2266 if (TryVal < CandVal) {
2267 if (Cand.Reason > Reason)
2268 Cand.Reason = Reason;
2271 Cand.setRepeat(Reason);
2275 static bool tryPressure(const PressureChange &TryP,
2276 const PressureChange &CandP,
2277 ConvergingScheduler::SchedCandidate &TryCand,
2278 ConvergingScheduler::SchedCandidate &Cand,
2279 ConvergingScheduler::CandReason Reason) {
2280 int TryRank = TryP.getPSetOrMax();
2281 int CandRank = CandP.getPSetOrMax();
2282 // If both candidates affect the same set, go with the smallest increase.
2283 if (TryRank == CandRank) {
2284 return tryLess(TryP.getUnitInc(), CandP.getUnitInc(), TryCand, Cand,
2287 // If one candidate decreases and the other increases, go with it.
2288 // Invalid candidates have UnitInc==0.
2289 if (tryLess(TryP.getUnitInc() < 0, CandP.getUnitInc() < 0, TryCand, Cand,
2293 // If the candidates are decreasing pressure, reverse priority.
2294 if (TryP.getUnitInc() < 0)
2295 std::swap(TryRank, CandRank);
2296 return tryGreater(TryRank, CandRank, TryCand, Cand, Reason);
2299 static unsigned getWeakLeft(const SUnit *SU, bool isTop) {
2300 return (isTop) ? SU->WeakPredsLeft : SU->WeakSuccsLeft;
2303 /// Minimize physical register live ranges. Regalloc wants them adjacent to
2304 /// their physreg def/use.
2306 /// FIXME: This is an unnecessary check on the critical path. Most are root/leaf
2307 /// copies which can be prescheduled. The rest (e.g. x86 MUL) could be bundled
2308 /// with the operation that produces or consumes the physreg. We'll do this when
2309 /// regalloc has support for parallel copies.
2310 static int biasPhysRegCopy(const SUnit *SU, bool isTop) {
2311 const MachineInstr *MI = SU->getInstr();
2315 unsigned ScheduledOper = isTop ? 1 : 0;
2316 unsigned UnscheduledOper = isTop ? 0 : 1;
2317 // If we have already scheduled the physreg produce/consumer, immediately
2318 // schedule the copy.
2319 if (TargetRegisterInfo::isPhysicalRegister(
2320 MI->getOperand(ScheduledOper).getReg()))
2322 // If the physreg is at the boundary, defer it. Otherwise schedule it
2323 // immediately to free the dependent. We can hoist the copy later.
2324 bool AtBoundary = isTop ? !SU->NumSuccsLeft : !SU->NumPredsLeft;
2325 if (TargetRegisterInfo::isPhysicalRegister(
2326 MI->getOperand(UnscheduledOper).getReg()))
2327 return AtBoundary ? -1 : 1;
2331 static bool tryLatency(ConvergingScheduler::SchedCandidate &TryCand,
2332 ConvergingScheduler::SchedCandidate &Cand,
2333 ConvergingScheduler::SchedBoundary &Zone) {
2335 if (Cand.SU->getDepth() > Zone.getScheduledLatency()) {
2336 if (tryLess(TryCand.SU->getDepth(), Cand.SU->getDepth(),
2337 TryCand, Cand, ConvergingScheduler::TopDepthReduce))
2340 if (tryGreater(TryCand.SU->getHeight(), Cand.SU->getHeight(),
2341 TryCand, Cand, ConvergingScheduler::TopPathReduce))
2345 if (Cand.SU->getHeight() > Zone.getScheduledLatency()) {
2346 if (tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(),
2347 TryCand, Cand, ConvergingScheduler::BotHeightReduce))
2350 if (tryGreater(TryCand.SU->getDepth(), Cand.SU->getDepth(),
2351 TryCand, Cand, ConvergingScheduler::BotPathReduce))
2357 /// Apply a set of heursitics to a new candidate. Heuristics are currently
2358 /// hierarchical. This may be more efficient than a graduated cost model because
2359 /// we don't need to evaluate all aspects of the model for each node in the
2360 /// queue. But it's really done to make the heuristics easier to debug and
2361 /// statistically analyze.
2363 /// \param Cand provides the policy and current best candidate.
2364 /// \param TryCand refers to the next SUnit candidate, otherwise uninitialized.
2365 /// \param Zone describes the scheduled zone that we are extending.
2366 /// \param RPTracker describes reg pressure within the scheduled zone.
2367 /// \param TempTracker is a scratch pressure tracker to reuse in queries.
2368 void ConvergingScheduler::tryCandidate(SchedCandidate &Cand,
2369 SchedCandidate &TryCand,
2370 SchedBoundary &Zone,
2371 const RegPressureTracker &RPTracker,
2372 RegPressureTracker &TempTracker) {
2374 if (DAG->shouldTrackPressure()) {
2375 // Always initialize TryCand's RPDelta.
2377 TempTracker.getMaxDownwardPressureDelta(
2378 TryCand.SU->getInstr(),
2380 DAG->getRegionCriticalPSets(),
2381 DAG->getRegPressure().MaxSetPressure);
2384 if (VerifyScheduling) {
2385 TempTracker.getMaxUpwardPressureDelta(
2386 TryCand.SU->getInstr(),
2387 &DAG->getPressureDiff(TryCand.SU),
2389 DAG->getRegionCriticalPSets(),
2390 DAG->getRegPressure().MaxSetPressure);
2393 RPTracker.getUpwardPressureDelta(
2394 TryCand.SU->getInstr(),
2395 DAG->getPressureDiff(TryCand.SU),
2397 DAG->getRegionCriticalPSets(),
2398 DAG->getRegPressure().MaxSetPressure);
2403 // Initialize the candidate if needed.
2404 if (!Cand.isValid()) {
2405 TryCand.Reason = NodeOrder;
2409 if (tryGreater(biasPhysRegCopy(TryCand.SU, Zone.isTop()),
2410 biasPhysRegCopy(Cand.SU, Zone.isTop()),
2411 TryCand, Cand, PhysRegCopy))
2414 // Avoid exceeding the target's limit. If signed PSetID is negative, it is
2415 // invalid; convert it to INT_MAX to give it lowest priority.
2416 if (DAG->shouldTrackPressure() && tryPressure(TryCand.RPDelta.Excess,
2417 Cand.RPDelta.Excess,
2418 TryCand, Cand, RegExcess))
2421 // For loops that are acyclic path limited, aggressively schedule for latency.
2422 if (Rem.IsAcyclicLatencyLimited && tryLatency(TryCand, Cand, Zone))
2425 // Avoid increasing the max critical pressure in the scheduled region.
2426 if (DAG->shouldTrackPressure() && tryPressure(TryCand.RPDelta.CriticalMax,
2427 Cand.RPDelta.CriticalMax,
2428 TryCand, Cand, RegCritical))
2431 // Keep clustered nodes together to encourage downstream peephole
2432 // optimizations which may reduce resource requirements.
2434 // This is a best effort to set things up for a post-RA pass. Optimizations
2435 // like generating loads of multiple registers should ideally be done within
2436 // the scheduler pass by combining the loads during DAG postprocessing.
2437 const SUnit *NextClusterSU =
2438 Zone.isTop() ? DAG->getNextClusterSucc() : DAG->getNextClusterPred();
2439 if (tryGreater(TryCand.SU == NextClusterSU, Cand.SU == NextClusterSU,
2440 TryCand, Cand, Cluster))
2443 // Weak edges are for clustering and other constraints.
2444 if (tryLess(getWeakLeft(TryCand.SU, Zone.isTop()),
2445 getWeakLeft(Cand.SU, Zone.isTop()),
2446 TryCand, Cand, Weak)) {
2449 // Avoid increasing the max pressure of the entire region.
2450 if (DAG->shouldTrackPressure() && tryPressure(TryCand.RPDelta.CurrentMax,
2451 Cand.RPDelta.CurrentMax,
2452 TryCand, Cand, RegMax))
2455 // Avoid critical resource consumption and balance the schedule.
2456 TryCand.initResourceDelta(DAG, SchedModel);
2457 if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
2458 TryCand, Cand, ResourceReduce))
2460 if (tryGreater(TryCand.ResDelta.DemandedResources,
2461 Cand.ResDelta.DemandedResources,
2462 TryCand, Cand, ResourceDemand))
2465 // Avoid serializing long latency dependence chains.
2466 // For acyclic path limited loops, latency was already checked above.
2467 if (Cand.Policy.ReduceLatency && !Rem.IsAcyclicLatencyLimited
2468 && tryLatency(TryCand, Cand, Zone)) {
2472 // Prefer immediate defs/users of the last scheduled instruction. This is a
2473 // local pressure avoidance strategy that also makes the machine code
2475 if (tryGreater(Zone.NextSUs.count(TryCand.SU), Zone.NextSUs.count(Cand.SU),
2476 TryCand, Cand, NextDefUse))
2479 // Fall through to original instruction order.
2480 if ((Zone.isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum)
2481 || (!Zone.isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) {
2482 TryCand.Reason = NodeOrder;
2487 const char *ConvergingScheduler::getReasonStr(
2488 ConvergingScheduler::CandReason Reason) {
2490 case NoCand: return "NOCAND ";
2491 case PhysRegCopy: return "PREG-COPY";
2492 case RegExcess: return "REG-EXCESS";
2493 case RegCritical: return "REG-CRIT ";
2494 case Cluster: return "CLUSTER ";
2495 case Weak: return "WEAK ";
2496 case RegMax: return "REG-MAX ";
2497 case ResourceReduce: return "RES-REDUCE";
2498 case ResourceDemand: return "RES-DEMAND";
2499 case TopDepthReduce: return "TOP-DEPTH ";
2500 case TopPathReduce: return "TOP-PATH ";
2501 case BotHeightReduce:return "BOT-HEIGHT";
2502 case BotPathReduce: return "BOT-PATH ";
2503 case NextDefUse: return "DEF-USE ";
2504 case NodeOrder: return "ORDER ";
2506 llvm_unreachable("Unknown reason!");
2509 void ConvergingScheduler::traceCandidate(const SchedCandidate &Cand) {
2511 unsigned ResIdx = 0;
2512 unsigned Latency = 0;
2513 switch (Cand.Reason) {
2517 P = Cand.RPDelta.Excess;
2520 P = Cand.RPDelta.CriticalMax;
2523 P = Cand.RPDelta.CurrentMax;
2525 case ResourceReduce:
2526 ResIdx = Cand.Policy.ReduceResIdx;
2528 case ResourceDemand:
2529 ResIdx = Cand.Policy.DemandResIdx;
2531 case TopDepthReduce:
2532 Latency = Cand.SU->getDepth();
2535 Latency = Cand.SU->getHeight();
2537 case BotHeightReduce:
2538 Latency = Cand.SU->getHeight();
2541 Latency = Cand.SU->getDepth();
2544 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason);
2546 dbgs() << " " << TRI->getRegPressureSetName(P.getPSet())
2547 << ":" << P.getUnitInc() << " ";
2551 dbgs() << " " << SchedModel->getProcResource(ResIdx)->Name << " ";
2555 dbgs() << " " << Latency << " cycles ";
2562 /// Pick the best candidate from the top queue.
2564 /// TODO: getMaxPressureDelta results can be mostly cached for each SUnit during
2565 /// DAG building. To adjust for the current scheduling location we need to
2566 /// maintain the number of vreg uses remaining to be top-scheduled.
2567 void ConvergingScheduler::pickNodeFromQueue(SchedBoundary &Zone,
2568 const RegPressureTracker &RPTracker,
2569 SchedCandidate &Cand) {
2570 ReadyQueue &Q = Zone.Available;
2574 // getMaxPressureDelta temporarily modifies the tracker.
2575 RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker);
2577 for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
2579 SchedCandidate TryCand(Cand.Policy);
2581 tryCandidate(Cand, TryCand, Zone, RPTracker, TempTracker);
2582 if (TryCand.Reason != NoCand) {
2583 // Initialize resource delta if needed in case future heuristics query it.
2584 if (TryCand.ResDelta == SchedResourceDelta())
2585 TryCand.initResourceDelta(DAG, SchedModel);
2586 Cand.setBest(TryCand);
2587 DEBUG(traceCandidate(Cand));
2592 static void tracePick(const ConvergingScheduler::SchedCandidate &Cand,
2594 DEBUG(dbgs() << "Pick " << (IsTop ? "Top " : "Bot ")
2595 << ConvergingScheduler::getReasonStr(Cand.Reason) << '\n');
2598 /// Pick the best candidate node from either the top or bottom queue.
2599 SUnit *ConvergingScheduler::pickNodeBidirectional(bool &IsTopNode) {
2600 // Schedule as far as possible in the direction of no choice. This is most
2601 // efficient, but also provides the best heuristics for CriticalPSets.
2602 if (SUnit *SU = Bot.pickOnlyChoice()) {
2604 DEBUG(dbgs() << "Pick Bot NOCAND\n");
2607 if (SUnit *SU = Top.pickOnlyChoice()) {
2609 DEBUG(dbgs() << "Pick Top NOCAND\n");
2612 CandPolicy NoPolicy;
2613 SchedCandidate BotCand(NoPolicy);
2614 SchedCandidate TopCand(NoPolicy);
2615 Bot.setPolicy(BotCand.Policy, Top);
2616 Top.setPolicy(TopCand.Policy, Bot);
2618 // Prefer bottom scheduling when heuristics are silent.
2619 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2620 assert(BotCand.Reason != NoCand && "failed to find the first candidate");
2622 // If either Q has a single candidate that provides the least increase in
2623 // Excess pressure, we can immediately schedule from that Q.
2625 // RegionCriticalPSets summarizes the pressure within the scheduled region and
2626 // affects picking from either Q. If scheduling in one direction must
2627 // increase pressure for one of the excess PSets, then schedule in that
2628 // direction first to provide more freedom in the other direction.
2629 if ((BotCand.Reason == RegExcess && !BotCand.isRepeat(RegExcess))
2630 || (BotCand.Reason == RegCritical
2631 && !BotCand.isRepeat(RegCritical)))
2634 tracePick(BotCand, IsTopNode);
2637 // Check if the top Q has a better candidate.
2638 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2639 assert(TopCand.Reason != NoCand && "failed to find the first candidate");
2641 // Choose the queue with the most important (lowest enum) reason.
2642 if (TopCand.Reason < BotCand.Reason) {
2644 tracePick(TopCand, IsTopNode);
2647 // Otherwise prefer the bottom candidate, in node order if all else failed.
2649 tracePick(BotCand, IsTopNode);
2653 /// Pick the best node to balance the schedule. Implements MachineSchedStrategy.
2654 SUnit *ConvergingScheduler::pickNode(bool &IsTopNode) {
2655 if (DAG->top() == DAG->bottom()) {
2656 assert(Top.Available.empty() && Top.Pending.empty() &&
2657 Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage");
2663 SU = Top.pickOnlyChoice();
2665 CandPolicy NoPolicy;
2666 SchedCandidate TopCand(NoPolicy);
2667 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2668 assert(TopCand.Reason != NoCand && "failed to find the first candidate");
2673 else if (ForceBottomUp) {
2674 SU = Bot.pickOnlyChoice();
2676 CandPolicy NoPolicy;
2677 SchedCandidate BotCand(NoPolicy);
2678 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2679 assert(BotCand.Reason != NoCand && "failed to find the first candidate");
2685 SU = pickNodeBidirectional(IsTopNode);
2687 } while (SU->isScheduled);
2689 if (SU->isTopReady())
2690 Top.removeReady(SU);
2691 if (SU->isBottomReady())
2692 Bot.removeReady(SU);
2694 DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr());
2698 void ConvergingScheduler::reschedulePhysRegCopies(SUnit *SU, bool isTop) {
2700 MachineBasicBlock::iterator InsertPos = SU->getInstr();
2703 SmallVectorImpl<SDep> &Deps = isTop ? SU->Preds : SU->Succs;
2705 // Find already scheduled copies with a single physreg dependence and move
2706 // them just above the scheduled instruction.
2707 for (SmallVectorImpl<SDep>::iterator I = Deps.begin(), E = Deps.end();
2709 if (I->getKind() != SDep::Data || !TRI->isPhysicalRegister(I->getReg()))
2711 SUnit *DepSU = I->getSUnit();
2712 if (isTop ? DepSU->Succs.size() > 1 : DepSU->Preds.size() > 1)
2714 MachineInstr *Copy = DepSU->getInstr();
2715 if (!Copy->isCopy())
2717 DEBUG(dbgs() << " Rescheduling physreg copy ";
2718 I->getSUnit()->dump(DAG));
2719 DAG->moveInstruction(Copy, InsertPos);
2723 /// Update the scheduler's state after scheduling a node. This is the same node
2724 /// that was just returned by pickNode(). However, ScheduleDAGMI needs to update
2725 /// it's state based on the current cycle before MachineSchedStrategy does.
2727 /// FIXME: Eventually, we may bundle physreg copies rather than rescheduling
2728 /// them here. See comments in biasPhysRegCopy.
2729 void ConvergingScheduler::schedNode(SUnit *SU, bool IsTopNode) {
2731 SU->TopReadyCycle = std::max(SU->TopReadyCycle, Top.CurrCycle);
2733 if (SU->hasPhysRegUses)
2734 reschedulePhysRegCopies(SU, true);
2737 SU->BotReadyCycle = std::max(SU->BotReadyCycle, Bot.CurrCycle);
2739 if (SU->hasPhysRegDefs)
2740 reschedulePhysRegCopies(SU, false);
2744 /// Create the standard converging machine scheduler. This will be used as the
2745 /// default scheduler if the target does not set a default.
2746 static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C) {
2747 assert((!ForceTopDown || !ForceBottomUp) &&
2748 "-misched-topdown incompatible with -misched-bottomup");
2749 ScheduleDAGMI *DAG = new ScheduleDAGMI(C, new ConvergingScheduler());
2750 // Register DAG post-processors.
2752 // FIXME: extend the mutation API to allow earlier mutations to instantiate
2753 // data and pass it to later mutations. Have a single mutation that gathers
2754 // the interesting nodes in one pass.
2755 DAG->addMutation(new CopyConstrain(DAG->TII, DAG->TRI));
2756 if (EnableLoadCluster && DAG->TII->enableClusterLoads())
2757 DAG->addMutation(new LoadClusterMutation(DAG->TII, DAG->TRI));
2758 if (EnableMacroFusion)
2759 DAG->addMutation(new MacroFusion(DAG->TII));
2762 static MachineSchedRegistry
2763 ConvergingSchedRegistry("converge", "Standard converging scheduler.",
2764 createConvergingSched);
2766 //===----------------------------------------------------------------------===//
2767 // ILP Scheduler. Currently for experimental analysis of heuristics.
2768 //===----------------------------------------------------------------------===//
2771 /// \brief Order nodes by the ILP metric.
2773 const SchedDFSResult *DFSResult;
2774 const BitVector *ScheduledTrees;
2777 ILPOrder(bool MaxILP): DFSResult(0), ScheduledTrees(0), MaximizeILP(MaxILP) {}
2779 /// \brief Apply a less-than relation on node priority.
2781 /// (Return true if A comes after B in the Q.)
2782 bool operator()(const SUnit *A, const SUnit *B) const {
2783 unsigned SchedTreeA = DFSResult->getSubtreeID(A);
2784 unsigned SchedTreeB = DFSResult->getSubtreeID(B);
2785 if (SchedTreeA != SchedTreeB) {
2786 // Unscheduled trees have lower priority.
2787 if (ScheduledTrees->test(SchedTreeA) != ScheduledTrees->test(SchedTreeB))
2788 return ScheduledTrees->test(SchedTreeB);
2790 // Trees with shallower connections have have lower priority.
2791 if (DFSResult->getSubtreeLevel(SchedTreeA)
2792 != DFSResult->getSubtreeLevel(SchedTreeB)) {
2793 return DFSResult->getSubtreeLevel(SchedTreeA)
2794 < DFSResult->getSubtreeLevel(SchedTreeB);
2798 return DFSResult->getILP(A) < DFSResult->getILP(B);
2800 return DFSResult->getILP(A) > DFSResult->getILP(B);
2804 /// \brief Schedule based on the ILP metric.
2805 class ILPScheduler : public MachineSchedStrategy {
2806 /// In case all subtrees are eventually connected to a common root through
2807 /// data dependence (e.g. reduction), place an upper limit on their size.
2809 /// FIXME: A subtree limit is generally good, but in the situation commented
2810 /// above, where multiple similar subtrees feed a common root, we should
2811 /// only split at a point where the resulting subtrees will be balanced.
2812 /// (a motivating test case must be found).
2813 static const unsigned SubtreeLimit = 16;
2818 std::vector<SUnit*> ReadyQ;
2820 ILPScheduler(bool MaximizeILP): DAG(0), Cmp(MaximizeILP) {}
2822 virtual void initialize(ScheduleDAGMI *dag) {
2824 DAG->computeDFSResult();
2825 Cmp.DFSResult = DAG->getDFSResult();
2826 Cmp.ScheduledTrees = &DAG->getScheduledTrees();
2830 virtual void registerRoots() {
2831 // Restore the heap in ReadyQ with the updated DFS results.
2832 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
2835 /// Implement MachineSchedStrategy interface.
2836 /// -----------------------------------------
2838 /// Callback to select the highest priority node from the ready Q.
2839 virtual SUnit *pickNode(bool &IsTopNode) {
2840 if (ReadyQ.empty()) return NULL;
2841 std::pop_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
2842 SUnit *SU = ReadyQ.back();
2845 DEBUG(dbgs() << "Pick node " << "SU(" << SU->NodeNum << ") "
2846 << " ILP: " << DAG->getDFSResult()->getILP(SU)
2847 << " Tree: " << DAG->getDFSResult()->getSubtreeID(SU) << " @"
2848 << DAG->getDFSResult()->getSubtreeLevel(
2849 DAG->getDFSResult()->getSubtreeID(SU)) << '\n'
2850 << "Scheduling " << *SU->getInstr());
2854 /// \brief Scheduler callback to notify that a new subtree is scheduled.
2855 virtual void scheduleTree(unsigned SubtreeID) {
2856 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
2859 /// Callback after a node is scheduled. Mark a newly scheduled tree, notify
2860 /// DFSResults, and resort the priority Q.
2861 virtual void schedNode(SUnit *SU, bool IsTopNode) {
2862 assert(!IsTopNode && "SchedDFSResult needs bottom-up");
2865 virtual void releaseTopNode(SUnit *) { /*only called for top roots*/ }
2867 virtual void releaseBottomNode(SUnit *SU) {
2868 ReadyQ.push_back(SU);
2869 std::push_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
2874 static ScheduleDAGInstrs *createILPMaxScheduler(MachineSchedContext *C) {
2875 return new ScheduleDAGMI(C, new ILPScheduler(true));
2877 static ScheduleDAGInstrs *createILPMinScheduler(MachineSchedContext *C) {
2878 return new ScheduleDAGMI(C, new ILPScheduler(false));
2880 static MachineSchedRegistry ILPMaxRegistry(
2881 "ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler);
2882 static MachineSchedRegistry ILPMinRegistry(
2883 "ilpmin", "Schedule bottom-up for min ILP", createILPMinScheduler);
2885 //===----------------------------------------------------------------------===//
2886 // Machine Instruction Shuffler for Correctness Testing
2887 //===----------------------------------------------------------------------===//
2891 /// Apply a less-than relation on the node order, which corresponds to the
2892 /// instruction order prior to scheduling. IsReverse implements greater-than.
2893 template<bool IsReverse>
2895 bool operator()(SUnit *A, SUnit *B) const {
2897 return A->NodeNum > B->NodeNum;
2899 return A->NodeNum < B->NodeNum;
2903 /// Reorder instructions as much as possible.
2904 class InstructionShuffler : public MachineSchedStrategy {
2908 // Using a less-than relation (SUnitOrder<false>) for the TopQ priority
2909 // gives nodes with a higher number higher priority causing the latest
2910 // instructions to be scheduled first.
2911 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false> >
2913 // When scheduling bottom-up, use greater-than as the queue priority.
2914 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true> >
2917 InstructionShuffler(bool alternate, bool topdown)
2918 : IsAlternating(alternate), IsTopDown(topdown) {}
2920 virtual void initialize(ScheduleDAGMI *) {
2925 /// Implement MachineSchedStrategy interface.
2926 /// -----------------------------------------
2928 virtual SUnit *pickNode(bool &IsTopNode) {
2932 if (TopQ.empty()) return NULL;
2935 } while (SU->isScheduled);
2940 if (BottomQ.empty()) return NULL;
2943 } while (SU->isScheduled);
2947 IsTopDown = !IsTopDown;
2951 virtual void schedNode(SUnit *SU, bool IsTopNode) {}
2953 virtual void releaseTopNode(SUnit *SU) {
2956 virtual void releaseBottomNode(SUnit *SU) {
2962 static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
2963 bool Alternate = !ForceTopDown && !ForceBottomUp;
2964 bool TopDown = !ForceBottomUp;
2965 assert((TopDown || !ForceTopDown) &&
2966 "-misched-topdown incompatible with -misched-bottomup");
2967 return new ScheduleDAGMI(C, new InstructionShuffler(Alternate, TopDown));
2969 static MachineSchedRegistry ShufflerRegistry(
2970 "shuffle", "Shuffle machine instructions alternating directions",
2971 createInstructionShuffler);
2974 //===----------------------------------------------------------------------===//
2975 // GraphWriter support for ScheduleDAGMI.
2976 //===----------------------------------------------------------------------===//
2981 template<> struct GraphTraits<
2982 ScheduleDAGMI*> : public GraphTraits<ScheduleDAG*> {};
2985 struct DOTGraphTraits<ScheduleDAGMI*> : public DefaultDOTGraphTraits {
2987 DOTGraphTraits (bool isSimple=false) : DefaultDOTGraphTraits(isSimple) {}
2989 static std::string getGraphName(const ScheduleDAG *G) {
2990 return G->MF.getName();
2993 static bool renderGraphFromBottomUp() {
2997 static bool isNodeHidden(const SUnit *Node) {
2998 return (Node->NumPreds > 10 || Node->NumSuccs > 10);
3001 static bool hasNodeAddressLabel(const SUnit *Node,
3002 const ScheduleDAG *Graph) {
3006 /// If you want to override the dot attributes printed for a particular
3007 /// edge, override this method.
3008 static std::string getEdgeAttributes(const SUnit *Node,
3010 const ScheduleDAG *Graph) {
3011 if (EI.isArtificialDep())
3012 return "color=cyan,style=dashed";
3014 return "color=blue,style=dashed";
3018 static std::string getNodeLabel(const SUnit *SU, const ScheduleDAG *G) {
3020 raw_string_ostream SS(Str);
3021 SS << "SU(" << SU->NodeNum << ')';
3024 static std::string getNodeDescription(const SUnit *SU, const ScheduleDAG *G) {
3025 return G->getGraphNodeLabel(SU);
3028 static std::string getNodeAttributes(const SUnit *N,
3029 const ScheduleDAG *Graph) {
3030 std::string Str("shape=Mrecord");
3031 const SchedDFSResult *DFS =
3032 static_cast<const ScheduleDAGMI*>(Graph)->getDFSResult();
3034 Str += ",style=filled,fillcolor=\"#";
3035 Str += DOT::getColorString(DFS->getSubtreeID(N));
3044 /// viewGraph - Pop up a ghostview window with the reachable parts of the DAG
3045 /// rendered using 'dot'.
3047 void ScheduleDAGMI::viewGraph(const Twine &Name, const Twine &Title) {
3049 ViewGraph(this, Name, false, Title);
3051 errs() << "ScheduleDAGMI::viewGraph is only available in debug builds on "
3052 << "systems with Graphviz or gv!\n";
3056 /// Out-of-line implementation with no arguments is handy for gdb.
3057 void ScheduleDAGMI::viewGraph() {
3058 viewGraph(getDAGName(), "Scheduling-Units Graph for " + getDAGName());