1 //===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MachineScheduler schedules machine instructions after phi elimination. It
11 // preserves LiveIntervals so it can be invoked before register allocation.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "misched"
17 #include "RegisterClassInfo.h"
18 #include "RegisterPressure.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/MachineScheduler.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/OwningPtr.h"
30 #include "llvm/ADT/PriorityQueue.h"
36 static cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
37 cl::desc("Force top-down list scheduling"));
38 static cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
39 cl::desc("Force bottom-up list scheduling"));
42 static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden,
43 cl::desc("Pop up a window to show MISched dags after they are processed"));
45 static cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden,
46 cl::desc("Stop scheduling after N instructions"), cl::init(~0U));
48 static bool ViewMISchedDAGs = false;
51 //===----------------------------------------------------------------------===//
52 // Machine Instruction Scheduling Pass and Registry
53 //===----------------------------------------------------------------------===//
55 MachineSchedContext::MachineSchedContext():
56 MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {
57 RegClassInfo = new RegisterClassInfo();
60 MachineSchedContext::~MachineSchedContext() {
65 /// MachineScheduler runs after coalescing and before register allocation.
66 class MachineScheduler : public MachineSchedContext,
67 public MachineFunctionPass {
71 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
73 virtual void releaseMemory() {}
75 virtual bool runOnMachineFunction(MachineFunction&);
77 virtual void print(raw_ostream &O, const Module* = 0) const;
79 static char ID; // Class identification, replacement for typeinfo
83 char MachineScheduler::ID = 0;
85 char &llvm::MachineSchedulerID = MachineScheduler::ID;
87 INITIALIZE_PASS_BEGIN(MachineScheduler, "misched",
88 "Machine Instruction Scheduler", false, false)
89 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
90 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
91 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
92 INITIALIZE_PASS_END(MachineScheduler, "misched",
93 "Machine Instruction Scheduler", false, false)
95 MachineScheduler::MachineScheduler()
96 : MachineFunctionPass(ID) {
97 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
100 void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
101 AU.setPreservesCFG();
102 AU.addRequiredID(MachineDominatorsID);
103 AU.addRequired<MachineLoopInfo>();
104 AU.addRequired<AliasAnalysis>();
105 AU.addRequired<TargetPassConfig>();
106 AU.addRequired<SlotIndexes>();
107 AU.addPreserved<SlotIndexes>();
108 AU.addRequired<LiveIntervals>();
109 AU.addPreserved<LiveIntervals>();
110 MachineFunctionPass::getAnalysisUsage(AU);
113 MachinePassRegistry MachineSchedRegistry::Registry;
115 /// A dummy default scheduler factory indicates whether the scheduler
116 /// is overridden on the command line.
117 static ScheduleDAGInstrs *useDefaultMachineSched(MachineSchedContext *C) {
121 /// MachineSchedOpt allows command line selection of the scheduler.
122 static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
123 RegisterPassParser<MachineSchedRegistry> >
124 MachineSchedOpt("misched",
125 cl::init(&useDefaultMachineSched), cl::Hidden,
126 cl::desc("Machine instruction scheduler to use"));
128 static MachineSchedRegistry
129 DefaultSchedRegistry("default", "Use the target's default scheduler choice.",
130 useDefaultMachineSched);
132 /// Forward declare the standard machine scheduler. This will be used as the
133 /// default scheduler if the target does not set a default.
134 static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C);
137 /// Decrement this iterator until reaching the top or a non-debug instr.
138 static MachineBasicBlock::iterator
139 priorNonDebug(MachineBasicBlock::iterator I, MachineBasicBlock::iterator Beg) {
140 assert(I != Beg && "reached the top of the region, cannot decrement");
142 if (!I->isDebugValue())
148 /// If this iterator is a debug value, increment until reaching the End or a
149 /// non-debug instruction.
150 static MachineBasicBlock::iterator
151 nextIfDebug(MachineBasicBlock::iterator I, MachineBasicBlock::iterator End) {
152 for(; I != End; ++I) {
153 if (!I->isDebugValue())
159 /// Top-level MachineScheduler pass driver.
161 /// Visit blocks in function order. Divide each block into scheduling regions
162 /// and visit them bottom-up. Visiting regions bottom-up is not required, but is
163 /// consistent with the DAG builder, which traverses the interior of the
164 /// scheduling regions bottom-up.
166 /// This design avoids exposing scheduling boundaries to the DAG builder,
167 /// simplifying the DAG builder's support for "special" target instructions.
168 /// At the same time the design allows target schedulers to operate across
169 /// scheduling boundaries, for example to bundle the boudary instructions
170 /// without reordering them. This creates complexity, because the target
171 /// scheduler must update the RegionBegin and RegionEnd positions cached by
172 /// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler
173 /// design would be to split blocks at scheduling boundaries, but LLVM has a
174 /// general bias against block splitting purely for implementation simplicity.
175 bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
176 DEBUG(dbgs() << "Before MISsched:\n"; mf.print(dbgs()));
178 // Initialize the context of the pass.
180 MLI = &getAnalysis<MachineLoopInfo>();
181 MDT = &getAnalysis<MachineDominatorTree>();
182 PassConfig = &getAnalysis<TargetPassConfig>();
183 AA = &getAnalysis<AliasAnalysis>();
185 LIS = &getAnalysis<LiveIntervals>();
186 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
188 RegClassInfo->runOnMachineFunction(*MF);
190 // Select the scheduler, or set the default.
191 MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
192 if (Ctor == useDefaultMachineSched) {
193 // Get the default scheduler set by the target.
194 Ctor = MachineSchedRegistry::getDefault();
196 Ctor = createConvergingSched;
197 MachineSchedRegistry::setDefault(Ctor);
200 // Instantiate the selected scheduler.
201 OwningPtr<ScheduleDAGInstrs> Scheduler(Ctor(this));
203 // Visit all machine basic blocks.
205 // TODO: Visit blocks in global postorder or postorder within the bottom-up
206 // loop tree. Then we can optionally compute global RegPressure.
207 for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
208 MBB != MBBEnd; ++MBB) {
210 Scheduler->startBlock(MBB);
212 // Break the block into scheduling regions [I, RegionEnd), and schedule each
213 // region as soon as it is discovered. RegionEnd points the the scheduling
214 // boundary at the bottom of the region. The DAG does not include RegionEnd,
215 // but the region does (i.e. the next RegionEnd is above the previous
216 // RegionBegin). If the current block has no terminator then RegionEnd ==
217 // MBB->end() for the bottom region.
219 // The Scheduler may insert instructions during either schedule() or
220 // exitRegion(), even for empty regions. So the local iterators 'I' and
221 // 'RegionEnd' are invalid across these calls.
222 unsigned RemainingCount = MBB->size();
223 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
224 RegionEnd != MBB->begin(); RegionEnd = Scheduler->begin()) {
226 // Avoid decrementing RegionEnd for blocks with no terminator.
227 if (RegionEnd != MBB->end()
228 || TII->isSchedulingBoundary(llvm::prior(RegionEnd), MBB, *MF)) {
230 // Count the boundary instruction.
234 // The next region starts above the previous region. Look backward in the
235 // instruction stream until we find the nearest boundary.
236 MachineBasicBlock::iterator I = RegionEnd;
237 for(;I != MBB->begin(); --I, --RemainingCount) {
238 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, *MF))
241 // Notify the scheduler of the region, even if we may skip scheduling
242 // it. Perhaps it still needs to be bundled.
243 Scheduler->enterRegion(MBB, I, RegionEnd, RemainingCount);
245 // Skip empty scheduling regions (0 or 1 schedulable instructions).
246 if (I == RegionEnd || I == llvm::prior(RegionEnd)) {
247 // Close the current region. Bundle the terminator if needed.
248 // This invalidates 'RegionEnd' and 'I'.
249 Scheduler->exitRegion();
252 DEBUG(dbgs() << "MachineScheduling " << MF->getFunction()->getName()
253 << ":BB#" << MBB->getNumber() << "\n From: " << *I << " To: ";
254 if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
255 else dbgs() << "End";
256 dbgs() << " Remaining: " << RemainingCount << "\n");
258 // Schedule a region: possibly reorder instructions.
259 // This invalidates 'RegionEnd' and 'I'.
260 Scheduler->schedule();
262 // Close the current region.
263 Scheduler->exitRegion();
265 // Scheduling has invalidated the current iterator 'I'. Ask the
266 // scheduler for the top of it's scheduled region.
267 RegionEnd = Scheduler->begin();
269 assert(RemainingCount == 0 && "Instruction count mismatch!");
270 Scheduler->finishBlock();
272 Scheduler->finalizeSchedule();
273 DEBUG(LIS->print(dbgs()));
277 void MachineScheduler::print(raw_ostream &O, const Module* m) const {
281 //===----------------------------------------------------------------------===//
282 // MachineSchedStrategy - Interface to a machine scheduling algorithm.
283 //===----------------------------------------------------------------------===//
288 /// MachineSchedStrategy - Interface used by ScheduleDAGMI to drive the selected
289 /// scheduling algorithm.
291 /// If this works well and targets wish to reuse ScheduleDAGMI, we may expose it
292 /// in ScheduleDAGInstrs.h
293 class MachineSchedStrategy {
295 virtual ~MachineSchedStrategy() {}
297 /// Initialize the strategy after building the DAG for a new region.
298 virtual void initialize(ScheduleDAGMI *DAG) = 0;
300 /// Pick the next node to schedule, or return NULL. Set IsTopNode to true to
301 /// schedule the node at the top of the unscheduled region. Otherwise it will
302 /// be scheduled at the bottom.
303 virtual SUnit *pickNode(bool &IsTopNode) = 0;
305 /// When all predecessor dependencies have been resolved, free this node for
306 /// top-down scheduling.
307 virtual void releaseTopNode(SUnit *SU) = 0;
308 /// When all successor dependencies have been resolved, free this node for
309 /// bottom-up scheduling.
310 virtual void releaseBottomNode(SUnit *SU) = 0;
314 //===----------------------------------------------------------------------===//
315 // ScheduleDAGMI - Base class for MachineInstr scheduling with LiveIntervals
317 //===----------------------------------------------------------------------===//
320 /// ScheduleDAGMI is an implementation of ScheduleDAGInstrs that schedules
321 /// machine instructions while updating LiveIntervals.
322 class ScheduleDAGMI : public ScheduleDAGInstrs {
324 RegisterClassInfo *RegClassInfo;
325 MachineSchedStrategy *SchedImpl;
327 MachineBasicBlock::iterator LiveRegionEnd;
329 // Register pressure in this region computed by buildSchedGraph.
330 IntervalPressure RegPressure;
331 RegPressureTracker RPTracker;
333 /// The top of the unscheduled zone.
334 MachineBasicBlock::iterator CurrentTop;
335 IntervalPressure TopPressure;
336 RegPressureTracker TopRPTracker;
338 /// The bottom of the unscheduled zone.
339 MachineBasicBlock::iterator CurrentBottom;
340 IntervalPressure BotPressure;
341 RegPressureTracker BotRPTracker;
343 /// The number of instructions scheduled so far. Used to cut off the
344 /// scheduler at the point determined by misched-cutoff.
345 unsigned NumInstrsScheduled;
347 ScheduleDAGMI(MachineSchedContext *C, MachineSchedStrategy *S):
348 ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
349 AA(C->AA), RegClassInfo(C->RegClassInfo), SchedImpl(S),
350 RPTracker(RegPressure), CurrentTop(), TopRPTracker(TopPressure),
351 CurrentBottom(), BotRPTracker(BotPressure), NumInstrsScheduled(0) {}
357 MachineBasicBlock::iterator top() const { return CurrentTop; }
358 MachineBasicBlock::iterator bottom() const { return CurrentBottom; }
360 /// Implement the ScheduleDAGInstrs interface for handling the next scheduling
361 /// region. This covers all instructions in a block, while schedule() may only
363 void enterRegion(MachineBasicBlock *bb,
364 MachineBasicBlock::iterator begin,
365 MachineBasicBlock::iterator end,
368 /// Implement ScheduleDAGInstrs interface for scheduling a sequence of
369 /// reorderable instructions.
372 /// Get current register pressure for the top scheduled instructions.
373 const IntervalPressure &getTopPressure() const { return TopPressure; }
374 const RegPressureTracker &getTopRPTracker() const { return TopRPTracker; }
376 /// Get current register pressure for the bottom scheduled instructions.
377 const IntervalPressure &getBotPressure() const { return BotPressure; }
378 const RegPressureTracker &getBotRPTracker() const { return BotRPTracker; }
380 /// Get register pressure for the entire scheduling region before scheduling.
381 const IntervalPressure &getRegPressure() const { return RegPressure; }
384 void initRegPressure();
386 void moveInstruction(MachineInstr *MI, MachineBasicBlock::iterator InsertPos);
387 bool checkSchedLimit();
389 void releaseSucc(SUnit *SU, SDep *SuccEdge);
390 void releaseSuccessors(SUnit *SU);
391 void releasePred(SUnit *SU, SDep *PredEdge);
392 void releasePredecessors(SUnit *SU);
394 void placeDebugValues();
398 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
399 /// NumPredsLeft reaches zero, release the successor node.
400 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
401 SUnit *SuccSU = SuccEdge->getSUnit();
404 if (SuccSU->NumPredsLeft == 0) {
405 dbgs() << "*** Scheduling failed! ***\n";
407 dbgs() << " has been released too many times!\n";
411 --SuccSU->NumPredsLeft;
412 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
413 SchedImpl->releaseTopNode(SuccSU);
416 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
417 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
418 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
420 releaseSucc(SU, &*I);
424 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. When
425 /// NumSuccsLeft reaches zero, release the predecessor node.
426 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
427 SUnit *PredSU = PredEdge->getSUnit();
430 if (PredSU->NumSuccsLeft == 0) {
431 dbgs() << "*** Scheduling failed! ***\n";
433 dbgs() << " has been released too many times!\n";
437 --PredSU->NumSuccsLeft;
438 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU)
439 SchedImpl->releaseBottomNode(PredSU);
442 /// releasePredecessors - Call releasePred on each of SU's predecessors.
443 void ScheduleDAGMI::releasePredecessors(SUnit *SU) {
444 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
446 releasePred(SU, &*I);
450 void ScheduleDAGMI::moveInstruction(MachineInstr *MI,
451 MachineBasicBlock::iterator InsertPos) {
452 // Advance RegionBegin if the first instruction moves down.
453 if (&*RegionBegin == MI)
456 // Update the instruction stream.
457 BB->splice(InsertPos, BB, MI);
459 // Update LiveIntervals
462 // Recede RegionBegin if an instruction moves above the first.
463 if (RegionBegin == InsertPos)
467 bool ScheduleDAGMI::checkSchedLimit() {
469 if (NumInstrsScheduled == MISchedCutoff && MISchedCutoff != ~0U) {
470 CurrentTop = CurrentBottom;
473 ++NumInstrsScheduled;
478 /// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
479 /// crossing a scheduling boundary. [begin, end) includes all instructions in
480 /// the region, including the boundary itself and single-instruction regions
481 /// that don't get scheduled.
482 void ScheduleDAGMI::enterRegion(MachineBasicBlock *bb,
483 MachineBasicBlock::iterator begin,
484 MachineBasicBlock::iterator end,
487 ScheduleDAGInstrs::enterRegion(bb, begin, end, endcount);
489 // For convenience remember the end of the liveness region.
491 (RegionEnd == bb->end()) ? RegionEnd : llvm::next(RegionEnd);
494 // Setup the register pressure trackers for the top scheduled top and bottom
495 // scheduled regions.
496 void ScheduleDAGMI::initRegPressure() {
497 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin);
498 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
500 // Close the RPTracker to finalize live ins.
501 RPTracker.closeRegion();
503 // Initialize the live ins and live outs.
504 TopRPTracker.addLiveRegs(RPTracker.getPressure().LiveInRegs);
505 BotRPTracker.addLiveRegs(RPTracker.getPressure().LiveOutRegs);
507 // Close one end of the tracker so we can call
508 // getMaxUpward/DownwardPressureDelta before advancing across any
509 // instructions. This converts currently live regs into live ins/outs.
510 TopRPTracker.closeTop();
511 BotRPTracker.closeBottom();
513 // Account for liveness generated by the region boundary.
514 if (LiveRegionEnd != RegionEnd)
515 BotRPTracker.recede();
517 assert(BotRPTracker.getPos() == RegionEnd && "Can't find the region bottom");
520 /// schedule - Called back from MachineScheduler::runOnMachineFunction
521 /// after setting up the current scheduling region. [RegionBegin, RegionEnd)
522 /// only includes instructions that have DAG nodes, not scheduling boundaries.
523 void ScheduleDAGMI::schedule() {
524 // Initialize the register pressure tracker used by buildSchedGraph.
525 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
527 // Account for liveness generate by the region boundary.
528 if (LiveRegionEnd != RegionEnd)
531 // Build the DAG, and compute current register pressure.
532 buildSchedGraph(AA, &RPTracker);
534 // Initialize top/bottom trackers after computing region pressure.
537 DEBUG(dbgs() << "********** MI Scheduling **********\n");
538 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
539 SUnits[su].dumpAll(this));
541 if (ViewMISchedDAGs) viewGraph();
543 SchedImpl->initialize(this);
545 // Release edges from the special Entry node or to the special Exit node.
546 releaseSuccessors(&EntrySU);
547 releasePredecessors(&ExitSU);
549 // Release all DAG roots for scheduling.
550 for (std::vector<SUnit>::iterator I = SUnits.begin(), E = SUnits.end();
552 // A SUnit is ready to top schedule if it has no predecessors.
553 if (I->Preds.empty())
554 SchedImpl->releaseTopNode(&(*I));
555 // A SUnit is ready to bottom schedule if it has no successors.
556 if (I->Succs.empty())
557 SchedImpl->releaseBottomNode(&(*I));
560 CurrentTop = nextIfDebug(RegionBegin, RegionEnd);
561 CurrentBottom = RegionEnd;
562 bool IsTopNode = false;
563 while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) {
564 DEBUG(dbgs() << "*** " << (IsTopNode ? "Top" : "Bottom")
565 << " Scheduling Instruction:\n"; SU->dump(this));
566 if (!checkSchedLimit())
569 // Move the instruction to its new location in the instruction stream.
570 MachineInstr *MI = SU->getInstr();
573 assert(SU->isTopReady() && "node still has unscheduled dependencies");
574 if (&*CurrentTop == MI)
575 CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);
577 moveInstruction(MI, CurrentTop);
578 TopRPTracker.setPos(MI);
581 // Update top scheduled pressure.
582 TopRPTracker.advance();
583 assert(TopRPTracker.getPos() == CurrentTop && "out of sync");
585 // Release dependent instructions for scheduling.
586 releaseSuccessors(SU);
589 assert(SU->isBottomReady() && "node still has unscheduled dependencies");
590 MachineBasicBlock::iterator priorII =
591 priorNonDebug(CurrentBottom, CurrentTop);
593 CurrentBottom = priorII;
595 if (&*CurrentTop == MI) {
596 CurrentTop = nextIfDebug(++CurrentTop, priorII);
597 TopRPTracker.setPos(CurrentTop);
599 moveInstruction(MI, CurrentBottom);
602 // Update bottom scheduled pressure.
603 BotRPTracker.recede();
604 assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
606 // Release dependent instructions for scheduling.
607 releasePredecessors(SU);
609 SU->isScheduled = true;
611 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
616 /// Reinsert any remaining debug_values, just like the PostRA scheduler.
617 void ScheduleDAGMI::placeDebugValues() {
618 // If first instruction was a DBG_VALUE then put it back.
620 BB->splice(RegionBegin, BB, FirstDbgValue);
621 RegionBegin = FirstDbgValue;
624 for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
625 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
626 std::pair<MachineInstr *, MachineInstr *> P = *prior(DI);
627 MachineInstr *DbgValue = P.first;
628 MachineBasicBlock::iterator OrigPrevMI = P.second;
629 BB->splice(++OrigPrevMI, BB, DbgValue);
630 if (OrigPrevMI == llvm::prior(RegionEnd))
631 RegionEnd = DbgValue;
634 FirstDbgValue = NULL;
637 //===----------------------------------------------------------------------===//
638 // ConvergingScheduler - Implementation of the standard MachineSchedStrategy.
639 //===----------------------------------------------------------------------===//
642 /// Wrapper around a vector of SUnits with some basic convenience methods.
644 typedef std::vector<SUnit*>::iterator iterator;
647 std::vector<SUnit*> Queue;
649 ReadyQ(unsigned id): ID(id) {}
651 bool isInQueue(SUnit *SU) const {
652 return SU->NodeQueueId & ID;
655 bool empty() const { return Queue.empty(); }
657 iterator begin() { return Queue.begin(); }
659 iterator end() { return Queue.end(); }
661 iterator find(SUnit *SU) {
662 return std::find(Queue.begin(), Queue.end(), SU);
665 void push(SUnit *SU) {
667 SU->NodeQueueId |= ID;
670 void remove(iterator I) {
671 (*I)->NodeQueueId &= ~ID;
677 /// ConvergingScheduler shrinks the unscheduled zone using heuristics to balance
679 class ConvergingScheduler : public MachineSchedStrategy {
681 /// Store the state used by ConvergingScheduler heuristics, required for the
682 /// lifetime of one invocation of pickNode().
683 struct SchedCandidate {
684 // The best SUnit candidate.
687 // Register pressure values for the best candidate.
688 RegPressureDelta RPDelta;
690 SchedCandidate(): SU(NULL) {}
694 const TargetRegisterInfo *TRI;
700 /// SUnit::NodeQueueId = 0 (none), = 1 (top), = 2 (bottom), = 3 (both)
706 ConvergingScheduler(): DAG(0), TRI(0), TopQueue(TopQID), BotQueue(BotQID) {}
708 static const char *getQName(unsigned ID) {
710 default: return "NoQ";
711 case TopQID: return "TopQ";
712 case BotQID: return "BotQ";
716 virtual void initialize(ScheduleDAGMI *dag) {
720 assert((!ForceTopDown || !ForceBottomUp) &&
721 "-misched-topdown incompatible with -misched-bottomup");
724 virtual SUnit *pickNode(bool &IsTopNode);
726 virtual void releaseTopNode(SUnit *SU) {
727 if (!SU->isScheduled)
730 virtual void releaseBottomNode(SUnit *SU) {
731 if (!SU->isScheduled)
736 void traceCandidate(const char *Label, unsigned QID, SUnit *SU,
737 int RPDiff, unsigned PSetID);
739 bool pickNodeFromQueue(ReadyQ &Q, const RegPressureTracker &RPTracker,
740 SchedCandidate &Candidate);
745 void ConvergingScheduler::
746 traceCandidate(const char *Label, unsigned QID, SUnit *SU,
747 int RPDiff, unsigned PSetID) {
748 dbgs() << Label << getQName(QID) << " ";
750 dbgs() << TRI->getRegPressureSetName(PSetID) << ":" << RPDiff << " ";
757 /// Pick the best candidate from the top queue.
759 /// TODO: getMaxPressureDelta results can be mostly cached for each SUnit during
760 /// DAG building. To adjust for the current scheduling location we need to
761 /// maintain the number of vreg uses remaining to be top-scheduled.
762 bool ConvergingScheduler::pickNodeFromQueue(ReadyQ &Q,
763 const RegPressureTracker &RPTracker,
764 SchedCandidate &Candidate) {
765 // getMaxPressureDelta temporarily modifies the tracker.
766 RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker);
768 // BestSU remains NULL if no top candidates beat the best existing candidate.
769 bool FoundCandidate = false;
770 for (ReadyQ::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
772 RegPressureDelta RPDelta;
773 TempTracker.getMaxPressureDelta((*I)->getInstr(), RPDelta);
775 // Avoid exceeding the target's limit.
776 if (!Candidate.SU || RPDelta.ExcessUnits < Candidate.RPDelta.ExcessUnits) {
777 DEBUG(traceCandidate(Candidate.SU ? "PCAND" : "ACAND", Q.ID, *I,
778 RPDelta.ExcessUnits, RPDelta.ExcessSetID));
780 Candidate.RPDelta = RPDelta;
781 FoundCandidate = true;
784 if (RPDelta.ExcessUnits > Candidate.RPDelta.ExcessUnits)
787 // Avoid increasing the max pressure.
788 if (RPDelta.MaxUnitIncrease < Candidate.RPDelta.MaxUnitIncrease) {
789 DEBUG(traceCandidate("MCAND", Q.ID, *I,
790 RPDelta.ExcessUnits, RPDelta.ExcessSetID));
792 Candidate.RPDelta = RPDelta;
793 FoundCandidate = true;
796 if (RPDelta.MaxUnitIncrease > Candidate.RPDelta.MaxUnitIncrease)
799 // Fall through to original instruction order.
800 // Only consider node order if BestSU was chosen from this Q.
804 if ((Q.ID == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum)
805 || (Q.ID == BotQID && (*I)->NodeNum > Candidate.SU->NodeNum)) {
806 DEBUG(traceCandidate("NCAND", Q.ID, *I, 0, 0));
808 Candidate.RPDelta = RPDelta;
809 FoundCandidate = true;
812 return FoundCandidate;
815 /// Pick the best node from either the top or bottom queue to balance the
817 SUnit *ConvergingScheduler::pickNode(bool &IsTopNode) {
818 if (DAG->top() == DAG->bottom()) {
819 assert(TopQueue.empty() && BotQueue.empty() && "ReadyQ garbage");
822 // As an initial placeholder heuristic, schedule in the direction that has
823 // the fewest choices.
826 SU = DAG->getSUnit(DAG->top());
829 else if (ForceBottomUp) {
830 SU = DAG->getSUnit(priorNonDebug(DAG->bottom(), DAG->top()));
834 SchedCandidate Candidate;
835 // Prefer picking from the bottom.
836 pickNodeFromQueue(BotQueue, DAG->getBotRPTracker(), Candidate);
838 pickNodeFromQueue(TopQueue, DAG->getTopRPTracker(), Candidate);
841 if (SU->isTopReady()) {
842 assert(!TopQueue.empty() && "bad ready count");
843 TopQueue.remove(TopQueue.find(SU));
845 if (SU->isBottomReady()) {
846 assert(!BotQueue.empty() && "bad ready count");
847 BotQueue.remove(BotQueue.find(SU));
852 /// Create the standard converging machine scheduler. This will be used as the
853 /// default scheduler if the target does not set a default.
854 static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C) {
855 assert((!ForceTopDown || !ForceBottomUp) &&
856 "-misched-topdown incompatible with -misched-bottomup");
857 return new ScheduleDAGMI(C, new ConvergingScheduler());
859 static MachineSchedRegistry
860 ConvergingSchedRegistry("converge", "Standard converging scheduler.",
861 createConvergingSched);
863 //===----------------------------------------------------------------------===//
864 // Machine Instruction Shuffler for Correctness Testing
865 //===----------------------------------------------------------------------===//
869 /// Apply a less-than relation on the node order, which corresponds to the
870 /// instruction order prior to scheduling. IsReverse implements greater-than.
871 template<bool IsReverse>
873 bool operator()(SUnit *A, SUnit *B) const {
875 return A->NodeNum > B->NodeNum;
877 return A->NodeNum < B->NodeNum;
881 /// Reorder instructions as much as possible.
882 class InstructionShuffler : public MachineSchedStrategy {
886 // Using a less-than relation (SUnitOrder<false>) for the TopQ priority
887 // gives nodes with a higher number higher priority causing the latest
888 // instructions to be scheduled first.
889 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false> >
891 // When scheduling bottom-up, use greater-than as the queue priority.
892 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true> >
895 InstructionShuffler(bool alternate, bool topdown)
896 : IsAlternating(alternate), IsTopDown(topdown) {}
898 virtual void initialize(ScheduleDAGMI *) {
903 /// Implement MachineSchedStrategy interface.
904 /// -----------------------------------------
906 virtual SUnit *pickNode(bool &IsTopNode) {
910 if (TopQ.empty()) return NULL;
913 } while (SU->isScheduled);
918 if (BottomQ.empty()) return NULL;
921 } while (SU->isScheduled);
925 IsTopDown = !IsTopDown;
929 virtual void releaseTopNode(SUnit *SU) {
932 virtual void releaseBottomNode(SUnit *SU) {
938 static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
939 bool Alternate = !ForceTopDown && !ForceBottomUp;
940 bool TopDown = !ForceBottomUp;
941 assert((TopDown || !ForceTopDown) &&
942 "-misched-topdown incompatible with -misched-bottomup");
943 return new ScheduleDAGMI(C, new InstructionShuffler(Alternate, TopDown));
945 static MachineSchedRegistry ShufflerRegistry(
946 "shuffle", "Shuffle machine instructions alternating directions",
947 createInstructionShuffler);