1 //===-- MachineSink.cpp - Sinking for machine instructions ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass moves instructions into successor blocks when possible, so that
11 // they aren't executed on paths where their results aren't needed.
13 // This pass is not intended to be a replacement or a complete alternative
14 // for an LLVM-IR-level sinking pass. It is only designed to sink simple
15 // constructs that are not exposed before lowering and instruction selection.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "machine-sink"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/ADT/SmallSet.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineLoopInfo.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/raw_ostream.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
36 SplitEdges("machine-sink-split",
37 cl::desc("Split critical edges during machine sinking"),
38 cl::init(true), cl::Hidden);
40 STATISTIC(NumSunk, "Number of machine instructions sunk");
41 STATISTIC(NumSplit, "Number of critical edges split");
42 STATISTIC(NumCoalesces, "Number of copies coalesced");
45 class MachineSinking : public MachineFunctionPass {
46 const TargetInstrInfo *TII;
47 const TargetRegisterInfo *TRI;
48 MachineRegisterInfo *MRI; // Machine register information
49 MachineDominatorTree *DT; // Machine dominator tree
53 // Remember which edges have been considered for breaking.
54 SmallSet<std::pair<MachineBasicBlock*,MachineBasicBlock*>, 8>
58 static char ID; // Pass identification
59 MachineSinking() : MachineFunctionPass(ID) {
60 initializeMachineSinkingPass(*PassRegistry::getPassRegistry());
63 bool runOnMachineFunction(MachineFunction &MF) override;
65 void getAnalysisUsage(AnalysisUsage &AU) const override {
67 MachineFunctionPass::getAnalysisUsage(AU);
68 AU.addRequired<AliasAnalysis>();
69 AU.addRequired<MachineDominatorTree>();
70 AU.addRequired<MachineLoopInfo>();
71 AU.addPreserved<MachineDominatorTree>();
72 AU.addPreserved<MachineLoopInfo>();
75 void releaseMemory() override {
76 CEBCandidates.clear();
80 bool ProcessBlock(MachineBasicBlock &MBB);
81 bool isWorthBreakingCriticalEdge(MachineInstr *MI,
82 MachineBasicBlock *From,
83 MachineBasicBlock *To);
84 MachineBasicBlock *SplitCriticalEdge(MachineInstr *MI,
85 MachineBasicBlock *From,
86 MachineBasicBlock *To,
88 bool SinkInstruction(MachineInstr *MI, bool &SawStore);
89 bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB,
90 MachineBasicBlock *DefMBB,
91 bool &BreakPHIEdge, bool &LocalUse) const;
92 MachineBasicBlock *FindSuccToSinkTo(MachineInstr *MI, MachineBasicBlock *MBB,
94 bool isProfitableToSinkTo(unsigned Reg, MachineInstr *MI,
95 MachineBasicBlock *MBB,
96 MachineBasicBlock *SuccToSinkTo);
98 bool PerformTrivialForwardCoalescing(MachineInstr *MI,
99 MachineBasicBlock *MBB);
101 } // end anonymous namespace
103 char MachineSinking::ID = 0;
104 char &llvm::MachineSinkingID = MachineSinking::ID;
105 INITIALIZE_PASS_BEGIN(MachineSinking, "machine-sink",
106 "Machine code sinking", false, false)
107 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
108 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
109 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
110 INITIALIZE_PASS_END(MachineSinking, "machine-sink",
111 "Machine code sinking", false, false)
113 bool MachineSinking::PerformTrivialForwardCoalescing(MachineInstr *MI,
114 MachineBasicBlock *MBB) {
118 unsigned SrcReg = MI->getOperand(1).getReg();
119 unsigned DstReg = MI->getOperand(0).getReg();
120 if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
121 !TargetRegisterInfo::isVirtualRegister(DstReg) ||
122 !MRI->hasOneNonDBGUse(SrcReg))
125 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
126 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg);
130 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
131 if (DefMI->isCopyLike())
133 DEBUG(dbgs() << "Coalescing: " << *DefMI);
134 DEBUG(dbgs() << "*** to: " << *MI);
135 MRI->replaceRegWith(DstReg, SrcReg);
136 MI->eraseFromParent();
141 /// AllUsesDominatedByBlock - Return true if all uses of the specified register
142 /// occur in blocks dominated by the specified block. If any use is in the
143 /// definition block, then return false since it is never legal to move def
146 MachineSinking::AllUsesDominatedByBlock(unsigned Reg,
147 MachineBasicBlock *MBB,
148 MachineBasicBlock *DefMBB,
150 bool &LocalUse) const {
151 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
152 "Only makes sense for vregs");
154 // Ignore debug uses because debug info doesn't affect the code.
155 if (MRI->use_nodbg_empty(Reg))
158 // BreakPHIEdge is true if all the uses are in the successor MBB being sunken
159 // into and they are all PHI nodes. In this case, machine-sink must break
160 // the critical edge first. e.g.
162 // BB#1: derived from LLVM BB %bb4.preheader
163 // Predecessors according to CFG: BB#0
165 // %reg16385<def> = DEC64_32r %reg16437, %EFLAGS<imp-def,dead>
167 // JE_4 <BB#37>, %EFLAGS<imp-use>
168 // Successors according to CFG: BB#37 BB#2
170 // BB#2: derived from LLVM BB %bb.nph
171 // Predecessors according to CFG: BB#0 BB#1
172 // %reg16386<def> = PHI %reg16434, <BB#0>, %reg16385, <BB#1>
174 for (MachineRegisterInfo::use_nodbg_iterator
175 I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end();
177 MachineInstr *UseInst = &*I;
178 MachineBasicBlock *UseBlock = UseInst->getParent();
179 if (!(UseBlock == MBB && UseInst->isPHI() &&
180 UseInst->getOperand(I.getOperandNo()+1).getMBB() == DefMBB)) {
181 BreakPHIEdge = false;
188 for (MachineRegisterInfo::use_nodbg_iterator
189 I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end();
191 // Determine the block of the use.
192 MachineInstr *UseInst = &*I;
193 MachineBasicBlock *UseBlock = UseInst->getParent();
194 if (UseInst->isPHI()) {
195 // PHI nodes use the operand in the predecessor block, not the block with
197 UseBlock = UseInst->getOperand(I.getOperandNo()+1).getMBB();
198 } else if (UseBlock == DefMBB) {
203 // Check that it dominates.
204 if (!DT->dominates(MBB, UseBlock))
211 bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
212 DEBUG(dbgs() << "******** Machine Sinking ********\n");
214 const TargetMachine &TM = MF.getTarget();
215 TII = TM.getInstrInfo();
216 TRI = TM.getRegisterInfo();
217 MRI = &MF.getRegInfo();
218 DT = &getAnalysis<MachineDominatorTree>();
219 LI = &getAnalysis<MachineLoopInfo>();
220 AA = &getAnalysis<AliasAnalysis>();
222 bool EverMadeChange = false;
225 bool MadeChange = false;
227 // Process all basic blocks.
228 CEBCandidates.clear();
229 for (MachineFunction::iterator I = MF.begin(), E = MF.end();
231 MadeChange |= ProcessBlock(*I);
233 // If this iteration over the code changed anything, keep iterating.
234 if (!MadeChange) break;
235 EverMadeChange = true;
237 return EverMadeChange;
240 bool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) {
241 // Can't sink anything out of a block that has less than two successors.
242 if (MBB.succ_size() <= 1 || MBB.empty()) return false;
244 // Don't bother sinking code out of unreachable blocks. In addition to being
245 // unprofitable, it can also lead to infinite looping, because in an
246 // unreachable loop there may be nowhere to stop.
247 if (!DT->isReachableFromEntry(&MBB)) return false;
249 bool MadeChange = false;
251 // Walk the basic block bottom-up. Remember if we saw a store.
252 MachineBasicBlock::iterator I = MBB.end();
254 bool ProcessedBegin, SawStore = false;
256 MachineInstr *MI = I; // The instruction to sink.
258 // Predecrement I (if it's not begin) so that it isn't invalidated by
260 ProcessedBegin = I == MBB.begin();
264 if (MI->isDebugValue())
267 bool Joined = PerformTrivialForwardCoalescing(MI, &MBB);
273 if (SinkInstruction(MI, SawStore))
274 ++NumSunk, MadeChange = true;
276 // If we just processed the first instruction in the block, we're done.
277 } while (!ProcessedBegin);
282 bool MachineSinking::isWorthBreakingCriticalEdge(MachineInstr *MI,
283 MachineBasicBlock *From,
284 MachineBasicBlock *To) {
285 // FIXME: Need much better heuristics.
287 // If the pass has already considered breaking this edge (during this pass
288 // through the function), then let's go ahead and break it. This means
289 // sinking multiple "cheap" instructions into the same block.
290 if (!CEBCandidates.insert(std::make_pair(From, To)))
293 if (!MI->isCopy() && !MI->isAsCheapAsAMove())
296 // MI is cheap, we probably don't want to break the critical edge for it.
297 // However, if this would allow some definitions of its source operands
298 // to be sunk then it's probably worth it.
299 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
300 const MachineOperand &MO = MI->getOperand(i);
301 if (!MO.isReg() || !MO.isUse())
303 unsigned Reg = MO.getReg();
307 // We don't move live definitions of physical registers,
308 // so sinking their uses won't enable any opportunities.
309 if (TargetRegisterInfo::isPhysicalRegister(Reg))
312 // If this instruction is the only user of a virtual register,
313 // check if breaking the edge will enable sinking
314 // both this instruction and the defining instruction.
315 if (MRI->hasOneNonDBGUse(Reg)) {
316 // If the definition resides in same MBB,
317 // claim it's likely we can sink these together.
318 // If definition resides elsewhere, we aren't
319 // blocking it from being sunk so don't break the edge.
320 MachineInstr *DefMI = MRI->getVRegDef(Reg);
321 if (DefMI->getParent() == MI->getParent())
329 MachineBasicBlock *MachineSinking::SplitCriticalEdge(MachineInstr *MI,
330 MachineBasicBlock *FromBB,
331 MachineBasicBlock *ToBB,
333 if (!isWorthBreakingCriticalEdge(MI, FromBB, ToBB))
336 // Avoid breaking back edge. From == To means backedge for single BB loop.
337 if (!SplitEdges || FromBB == ToBB)
340 // Check for backedges of more "complex" loops.
341 if (LI->getLoopFor(FromBB) == LI->getLoopFor(ToBB) &&
342 LI->isLoopHeader(ToBB))
345 // It's not always legal to break critical edges and sink the computation
353 // ... no uses of v1024
359 // If BB#1 -> BB#3 edge is broken and computation of v1024 is inserted:
368 // ... no uses of v1024
374 // This is incorrect since v1024 is not computed along the BB#1->BB#2->BB#3
375 // flow. We need to ensure the new basic block where the computation is
376 // sunk to dominates all the uses.
377 // It's only legal to break critical edge and sink the computation to the
378 // new block if all the predecessors of "To", except for "From", are
379 // not dominated by "From". Given SSA property, this means these
380 // predecessors are dominated by "To".
382 // There is no need to do this check if all the uses are PHI nodes. PHI
383 // sources are only defined on the specific predecessor edges.
385 for (MachineBasicBlock::pred_iterator PI = ToBB->pred_begin(),
386 E = ToBB->pred_end(); PI != E; ++PI) {
389 if (!DT->dominates(ToBB, *PI))
394 return FromBB->SplitCriticalEdge(ToBB, this);
397 static bool AvoidsSinking(MachineInstr *MI, MachineRegisterInfo *MRI) {
398 return MI->isInsertSubreg() || MI->isSubregToReg() || MI->isRegSequence();
401 /// collectDebgValues - Scan instructions following MI and collect any
402 /// matching DBG_VALUEs.
403 static void collectDebugValues(MachineInstr *MI,
404 SmallVectorImpl<MachineInstr *> &DbgValues) {
406 if (!MI->getOperand(0).isReg())
409 MachineBasicBlock::iterator DI = MI; ++DI;
410 for (MachineBasicBlock::iterator DE = MI->getParent()->end();
412 if (!DI->isDebugValue())
414 if (DI->getOperand(0).isReg() &&
415 DI->getOperand(0).getReg() == MI->getOperand(0).getReg())
416 DbgValues.push_back(DI);
420 /// isPostDominatedBy - Return true if A is post dominated by B.
421 static bool isPostDominatedBy(MachineBasicBlock *A, MachineBasicBlock *B) {
423 // FIXME - Use real post dominator.
424 if (A->succ_size() != 2)
426 MachineBasicBlock::succ_iterator I = A->succ_begin();
429 MachineBasicBlock *OtherSuccBlock = *I;
430 if (OtherSuccBlock->succ_size() != 1 ||
431 *(OtherSuccBlock->succ_begin()) != B)
437 /// isProfitableToSinkTo - Return true if it is profitable to sink MI.
438 bool MachineSinking::isProfitableToSinkTo(unsigned Reg, MachineInstr *MI,
439 MachineBasicBlock *MBB,
440 MachineBasicBlock *SuccToSinkTo) {
441 assert (MI && "Invalid MachineInstr!");
442 assert (SuccToSinkTo && "Invalid SinkTo Candidate BB");
444 if (MBB == SuccToSinkTo)
447 // It is profitable if SuccToSinkTo does not post dominate current block.
448 if (!isPostDominatedBy(MBB, SuccToSinkTo))
451 // Check if only use in post dominated block is PHI instruction.
452 bool NonPHIUse = false;
453 for (MachineRegisterInfo::use_nodbg_iterator
454 I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end();
456 MachineInstr *UseInst = &*I;
457 MachineBasicBlock *UseBlock = UseInst->getParent();
458 if (UseBlock == SuccToSinkTo && !UseInst->isPHI())
464 // If SuccToSinkTo post dominates then also it may be profitable if MI
465 // can further profitably sinked into another block in next round.
466 bool BreakPHIEdge = false;
467 // FIXME - If finding successor is compile time expensive then catch results.
468 if (MachineBasicBlock *MBB2 = FindSuccToSinkTo(MI, SuccToSinkTo, BreakPHIEdge))
469 return isProfitableToSinkTo(Reg, MI, SuccToSinkTo, MBB2);
471 // If SuccToSinkTo is final destination and it is a post dominator of current
472 // block then it is not profitable to sink MI into SuccToSinkTo block.
476 /// FindSuccToSinkTo - Find a successor to sink this instruction to.
477 MachineBasicBlock *MachineSinking::FindSuccToSinkTo(MachineInstr *MI,
478 MachineBasicBlock *MBB,
479 bool &BreakPHIEdge) {
481 assert (MI && "Invalid MachineInstr!");
482 assert (MBB && "Invalid MachineBasicBlock!");
484 // Loop over all the operands of the specified instruction. If there is
485 // anything we can't handle, bail out.
487 // SuccToSinkTo - This is the successor to sink this instruction to, once we
489 MachineBasicBlock *SuccToSinkTo = 0;
490 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
491 const MachineOperand &MO = MI->getOperand(i);
492 if (!MO.isReg()) continue; // Ignore non-register operands.
494 unsigned Reg = MO.getReg();
495 if (Reg == 0) continue;
497 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
499 // If the physreg has no defs anywhere, it's just an ambient register
500 // and we can freely move its uses. Alternatively, if it's allocatable,
501 // it could get allocated to something with a def during allocation.
502 if (!MRI->isConstantPhysReg(Reg, *MBB->getParent()))
504 } else if (!MO.isDead()) {
505 // A def that isn't dead. We can't move it.
509 // Virtual register uses are always safe to sink.
510 if (MO.isUse()) continue;
512 // If it's not safe to move defs of the register class, then abort.
513 if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg)))
516 // FIXME: This picks a successor to sink into based on having one
517 // successor that dominates all the uses. However, there are cases where
518 // sinking can happen but where the sink point isn't a successor. For
525 // the instruction could be sunk over the whole diamond for the
526 // if/then/else (or loop, etc), allowing it to be sunk into other blocks
529 // Virtual register defs can only be sunk if all their uses are in blocks
530 // dominated by one of the successors.
532 // If a previous operand picked a block to sink to, then this operand
533 // must be sinkable to the same block.
534 bool LocalUse = false;
535 if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo, MBB,
536 BreakPHIEdge, LocalUse))
542 // Otherwise, we should look at all the successors and decide which one
543 // we should sink to.
544 // We give successors with smaller loop depth higher priority.
545 SmallVector<MachineBasicBlock*, 4> Succs(MBB->succ_begin(), MBB->succ_end());
546 // Sort Successors according to their loop depth.
548 Succs.begin(), Succs.end(),
549 [this](const MachineBasicBlock *LHS, const MachineBasicBlock *RHS) {
550 return LI->getLoopDepth(LHS) < LI->getLoopDepth(RHS);
552 for (SmallVectorImpl<MachineBasicBlock *>::iterator SI = Succs.begin(),
553 E = Succs.end(); SI != E; ++SI) {
554 MachineBasicBlock *SuccBlock = *SI;
555 bool LocalUse = false;
556 if (AllUsesDominatedByBlock(Reg, SuccBlock, MBB,
557 BreakPHIEdge, LocalUse)) {
558 SuccToSinkTo = SuccBlock;
562 // Def is used locally, it's never safe to move this def.
566 // If we couldn't find a block to sink to, ignore this instruction.
567 if (SuccToSinkTo == 0)
569 else if (!isProfitableToSinkTo(Reg, MI, MBB, SuccToSinkTo))
574 // It is not possible to sink an instruction into its own block. This can
575 // happen with loops.
576 if (MBB == SuccToSinkTo)
579 // It's not safe to sink instructions to EH landing pad. Control flow into
580 // landing pad is implicitly defined.
581 if (SuccToSinkTo && SuccToSinkTo->isLandingPad())
587 /// SinkInstruction - Determine whether it is safe to sink the specified machine
588 /// instruction out of its current block into a successor.
589 bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) {
590 // Don't sink insert_subreg, subreg_to_reg, reg_sequence. These are meant to
591 // be close to the source to make it easier to coalesce.
592 if (AvoidsSinking(MI, MRI))
595 // Check if it's safe to move the instruction.
596 if (!MI->isSafeToMove(TII, AA, SawStore))
599 // FIXME: This should include support for sinking instructions within the
600 // block they are currently in to shorten the live ranges. We often get
601 // instructions sunk into the top of a large block, but it would be better to
602 // also sink them down before their first use in the block. This xform has to
603 // be careful not to *increase* register pressure though, e.g. sinking
604 // "x = y + z" down if it kills y and z would increase the live ranges of y
605 // and z and only shrink the live range of x.
607 bool BreakPHIEdge = false;
608 MachineBasicBlock *ParentBlock = MI->getParent();
609 MachineBasicBlock *SuccToSinkTo = FindSuccToSinkTo(MI, ParentBlock, BreakPHIEdge);
611 // If there are no outputs, it must have side-effects.
612 if (SuccToSinkTo == 0)
616 // If the instruction to move defines a dead physical register which is live
617 // when leaving the basic block, don't move it because it could turn into a
618 // "zombie" define of that preg. E.g., EFLAGS. (<rdar://problem/8030636>)
619 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
620 const MachineOperand &MO = MI->getOperand(I);
621 if (!MO.isReg()) continue;
622 unsigned Reg = MO.getReg();
623 if (Reg == 0 || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
624 if (SuccToSinkTo->isLiveIn(Reg))
628 DEBUG(dbgs() << "Sink instr " << *MI << "\tinto block " << *SuccToSinkTo);
630 // If the block has multiple predecessors, this is a critical edge.
631 // Decide if we can sink along it or need to break the edge.
632 if (SuccToSinkTo->pred_size() > 1) {
633 // We cannot sink a load across a critical edge - there may be stores in
635 bool TryBreak = false;
637 if (!MI->isSafeToMove(TII, AA, store)) {
638 DEBUG(dbgs() << " *** NOTE: Won't sink load along critical edge.\n");
642 // We don't want to sink across a critical edge if we don't dominate the
643 // successor. We could be introducing calculations to new code paths.
644 if (!TryBreak && !DT->dominates(ParentBlock, SuccToSinkTo)) {
645 DEBUG(dbgs() << " *** NOTE: Critical edge found\n");
649 // Don't sink instructions into a loop.
650 if (!TryBreak && LI->isLoopHeader(SuccToSinkTo)) {
651 DEBUG(dbgs() << " *** NOTE: Loop header found\n");
655 // Otherwise we are OK with sinking along a critical edge.
657 DEBUG(dbgs() << "Sinking along critical edge.\n");
659 MachineBasicBlock *NewSucc =
660 SplitCriticalEdge(MI, ParentBlock, SuccToSinkTo, BreakPHIEdge);
662 DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to "
663 "break critical edge\n");
666 DEBUG(dbgs() << " *** Splitting critical edge:"
667 " BB#" << ParentBlock->getNumber()
668 << " -- BB#" << NewSucc->getNumber()
669 << " -- BB#" << SuccToSinkTo->getNumber() << '\n');
670 SuccToSinkTo = NewSucc;
672 BreakPHIEdge = false;
678 // BreakPHIEdge is true if all the uses are in the successor MBB being
679 // sunken into and they are all PHI nodes. In this case, machine-sink must
680 // break the critical edge first.
681 MachineBasicBlock *NewSucc = SplitCriticalEdge(MI, ParentBlock,
682 SuccToSinkTo, BreakPHIEdge);
684 DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to "
685 "break critical edge\n");
689 DEBUG(dbgs() << " *** Splitting critical edge:"
690 " BB#" << ParentBlock->getNumber()
691 << " -- BB#" << NewSucc->getNumber()
692 << " -- BB#" << SuccToSinkTo->getNumber() << '\n');
693 SuccToSinkTo = NewSucc;
697 // Determine where to insert into. Skip phi nodes.
698 MachineBasicBlock::iterator InsertPos = SuccToSinkTo->begin();
699 while (InsertPos != SuccToSinkTo->end() && InsertPos->isPHI())
702 // collect matching debug values.
703 SmallVector<MachineInstr *, 2> DbgValuesToSink;
704 collectDebugValues(MI, DbgValuesToSink);
706 // Move the instruction.
707 SuccToSinkTo->splice(InsertPos, ParentBlock, MI,
708 ++MachineBasicBlock::iterator(MI));
710 // Move debug values.
711 for (SmallVectorImpl<MachineInstr *>::iterator DBI = DbgValuesToSink.begin(),
712 DBE = DbgValuesToSink.end(); DBI != DBE; ++DBI) {
713 MachineInstr *DbgMI = *DBI;
714 SuccToSinkTo->splice(InsertPos, ParentBlock, DbgMI,
715 ++MachineBasicBlock::iterator(DbgMI));
718 // Conservatively, clear any kill flags, since it's possible that they are no