1 //===-- MachineSink.cpp - Sinking for machine instructions ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass moves instructions into successor blocks when possible, so that
11 // they aren't executed on paths where their results aren't needed.
13 // This pass is not intended to be a replacement or a complete alternative
14 // for an LLVM-IR-level sinking pass. It is only designed to sink simple
15 // constructs that are not exposed before lowering and instruction selection.
17 //===----------------------------------------------------------------------===//
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/ADT/SetVector.h"
21 #include "llvm/ADT/SmallSet.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineLoopInfo.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
33 #include "llvm/Target/TargetSubtargetInfo.h"
36 #define DEBUG_TYPE "machine-sink"
39 SplitEdges("machine-sink-split",
40 cl::desc("Split critical edges during machine sinking"),
41 cl::init(true), cl::Hidden);
44 UseBlockFreqInfo("machine-sink-bfi",
45 cl::desc("Use block frequency info to find successors to sink"),
46 cl::init(true), cl::Hidden);
49 STATISTIC(NumSunk, "Number of machine instructions sunk");
50 STATISTIC(NumSplit, "Number of critical edges split");
51 STATISTIC(NumCoalesces, "Number of copies coalesced");
54 class MachineSinking : public MachineFunctionPass {
55 const TargetInstrInfo *TII;
56 const TargetRegisterInfo *TRI;
57 MachineRegisterInfo *MRI; // Machine register information
58 MachineDominatorTree *DT; // Machine dominator tree
60 const MachineBlockFrequencyInfo *MBFI;
63 // Remember which edges have been considered for breaking.
64 SmallSet<std::pair<MachineBasicBlock*,MachineBasicBlock*>, 8>
66 // Remember which edges we are about to split.
67 // This is different from CEBCandidates since those edges
69 SetVector<std::pair<MachineBasicBlock*,MachineBasicBlock*> > ToSplit;
72 static char ID; // Pass identification
73 MachineSinking() : MachineFunctionPass(ID) {
74 initializeMachineSinkingPass(*PassRegistry::getPassRegistry());
77 bool runOnMachineFunction(MachineFunction &MF) override;
79 void getAnalysisUsage(AnalysisUsage &AU) const override {
81 MachineFunctionPass::getAnalysisUsage(AU);
82 AU.addRequired<AliasAnalysis>();
83 AU.addRequired<MachineDominatorTree>();
84 AU.addRequired<MachineLoopInfo>();
85 AU.addPreserved<MachineDominatorTree>();
86 AU.addPreserved<MachineLoopInfo>();
88 AU.addRequired<MachineBlockFrequencyInfo>();
91 void releaseMemory() override {
92 CEBCandidates.clear();
96 bool ProcessBlock(MachineBasicBlock &MBB);
97 bool isWorthBreakingCriticalEdge(MachineInstr *MI,
98 MachineBasicBlock *From,
99 MachineBasicBlock *To);
100 /// \brief Postpone the splitting of the given critical
101 /// edge (\p From, \p To).
103 /// We do not split the edges on the fly. Indeed, this invalidates
104 /// the dominance information and thus triggers a lot of updates
105 /// of that information underneath.
106 /// Instead, we postpone all the splits after each iteration of
107 /// the main loop. That way, the information is at least valid
108 /// for the lifetime of an iteration.
110 /// \return True if the edge is marked as toSplit, false otherwise.
111 /// False can be retruned if, for instance, this is not profitable.
112 bool PostponeSplitCriticalEdge(MachineInstr *MI,
113 MachineBasicBlock *From,
114 MachineBasicBlock *To,
116 bool SinkInstruction(MachineInstr *MI, bool &SawStore);
117 bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB,
118 MachineBasicBlock *DefMBB,
119 bool &BreakPHIEdge, bool &LocalUse) const;
120 MachineBasicBlock *FindSuccToSinkTo(MachineInstr *MI, MachineBasicBlock *MBB,
122 bool isProfitableToSinkTo(unsigned Reg, MachineInstr *MI,
123 MachineBasicBlock *MBB,
124 MachineBasicBlock *SuccToSinkTo);
126 bool PerformTrivialForwardCoalescing(MachineInstr *MI,
127 MachineBasicBlock *MBB);
129 } // end anonymous namespace
131 char MachineSinking::ID = 0;
132 char &llvm::MachineSinkingID = MachineSinking::ID;
133 INITIALIZE_PASS_BEGIN(MachineSinking, "machine-sink",
134 "Machine code sinking", false, false)
135 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
136 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
137 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
138 INITIALIZE_PASS_END(MachineSinking, "machine-sink",
139 "Machine code sinking", false, false)
141 bool MachineSinking::PerformTrivialForwardCoalescing(MachineInstr *MI,
142 MachineBasicBlock *MBB) {
146 unsigned SrcReg = MI->getOperand(1).getReg();
147 unsigned DstReg = MI->getOperand(0).getReg();
148 if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
149 !TargetRegisterInfo::isVirtualRegister(DstReg) ||
150 !MRI->hasOneNonDBGUse(SrcReg))
153 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
154 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg);
158 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
159 if (DefMI->isCopyLike())
161 DEBUG(dbgs() << "Coalescing: " << *DefMI);
162 DEBUG(dbgs() << "*** to: " << *MI);
163 MRI->replaceRegWith(DstReg, SrcReg);
164 MI->eraseFromParent();
166 // Conservatively, clear any kill flags, since it's possible that they are no
168 MRI->clearKillFlags(SrcReg);
174 /// AllUsesDominatedByBlock - Return true if all uses of the specified register
175 /// occur in blocks dominated by the specified block. If any use is in the
176 /// definition block, then return false since it is never legal to move def
179 MachineSinking::AllUsesDominatedByBlock(unsigned Reg,
180 MachineBasicBlock *MBB,
181 MachineBasicBlock *DefMBB,
183 bool &LocalUse) const {
184 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
185 "Only makes sense for vregs");
187 // Ignore debug uses because debug info doesn't affect the code.
188 if (MRI->use_nodbg_empty(Reg))
191 // BreakPHIEdge is true if all the uses are in the successor MBB being sunken
192 // into and they are all PHI nodes. In this case, machine-sink must break
193 // the critical edge first. e.g.
195 // BB#1: derived from LLVM BB %bb4.preheader
196 // Predecessors according to CFG: BB#0
198 // %reg16385<def> = DEC64_32r %reg16437, %EFLAGS<imp-def,dead>
200 // JE_4 <BB#37>, %EFLAGS<imp-use>
201 // Successors according to CFG: BB#37 BB#2
203 // BB#2: derived from LLVM BB %bb.nph
204 // Predecessors according to CFG: BB#0 BB#1
205 // %reg16386<def> = PHI %reg16434, <BB#0>, %reg16385, <BB#1>
207 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
208 MachineInstr *UseInst = MO.getParent();
209 unsigned OpNo = &MO - &UseInst->getOperand(0);
210 MachineBasicBlock *UseBlock = UseInst->getParent();
211 if (!(UseBlock == MBB && UseInst->isPHI() &&
212 UseInst->getOperand(OpNo+1).getMBB() == DefMBB)) {
213 BreakPHIEdge = false;
220 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
221 // Determine the block of the use.
222 MachineInstr *UseInst = MO.getParent();
223 unsigned OpNo = &MO - &UseInst->getOperand(0);
224 MachineBasicBlock *UseBlock = UseInst->getParent();
225 if (UseInst->isPHI()) {
226 // PHI nodes use the operand in the predecessor block, not the block with
228 UseBlock = UseInst->getOperand(OpNo+1).getMBB();
229 } else if (UseBlock == DefMBB) {
234 // Check that it dominates.
235 if (!DT->dominates(MBB, UseBlock))
242 bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
243 if (skipOptnoneFunction(*MF.getFunction()))
246 DEBUG(dbgs() << "******** Machine Sinking ********\n");
248 TII = MF.getSubtarget().getInstrInfo();
249 TRI = MF.getSubtarget().getRegisterInfo();
250 MRI = &MF.getRegInfo();
251 DT = &getAnalysis<MachineDominatorTree>();
252 LI = &getAnalysis<MachineLoopInfo>();
253 MBFI = UseBlockFreqInfo ? &getAnalysis<MachineBlockFrequencyInfo>() : nullptr;
254 AA = &getAnalysis<AliasAnalysis>();
256 bool EverMadeChange = false;
259 bool MadeChange = false;
261 // Process all basic blocks.
262 CEBCandidates.clear();
264 for (MachineFunction::iterator I = MF.begin(), E = MF.end();
266 MadeChange |= ProcessBlock(*I);
268 // If we have anything we marked as toSplit, split it now.
269 for (auto &Pair : ToSplit) {
270 auto NewSucc = Pair.first->SplitCriticalEdge(Pair.second, this);
271 if (NewSucc != nullptr) {
272 DEBUG(dbgs() << " *** Splitting critical edge:"
273 " BB#" << Pair.first->getNumber()
274 << " -- BB#" << NewSucc->getNumber()
275 << " -- BB#" << Pair.second->getNumber() << '\n');
279 DEBUG(dbgs() << " *** Not legal to break critical edge\n");
281 // If this iteration over the code changed anything, keep iterating.
282 if (!MadeChange) break;
283 EverMadeChange = true;
285 return EverMadeChange;
288 bool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) {
289 // Can't sink anything out of a block that has less than two successors.
290 if (MBB.succ_size() <= 1 || MBB.empty()) return false;
292 // Don't bother sinking code out of unreachable blocks. In addition to being
293 // unprofitable, it can also lead to infinite looping, because in an
294 // unreachable loop there may be nowhere to stop.
295 if (!DT->isReachableFromEntry(&MBB)) return false;
297 bool MadeChange = false;
299 // Walk the basic block bottom-up. Remember if we saw a store.
300 MachineBasicBlock::iterator I = MBB.end();
302 bool ProcessedBegin, SawStore = false;
304 MachineInstr *MI = I; // The instruction to sink.
306 // Predecrement I (if it's not begin) so that it isn't invalidated by
308 ProcessedBegin = I == MBB.begin();
312 if (MI->isDebugValue())
315 bool Joined = PerformTrivialForwardCoalescing(MI, &MBB);
321 if (SinkInstruction(MI, SawStore))
322 ++NumSunk, MadeChange = true;
324 // If we just processed the first instruction in the block, we're done.
325 } while (!ProcessedBegin);
330 bool MachineSinking::isWorthBreakingCriticalEdge(MachineInstr *MI,
331 MachineBasicBlock *From,
332 MachineBasicBlock *To) {
333 // FIXME: Need much better heuristics.
335 // If the pass has already considered breaking this edge (during this pass
336 // through the function), then let's go ahead and break it. This means
337 // sinking multiple "cheap" instructions into the same block.
338 if (!CEBCandidates.insert(std::make_pair(From, To)))
341 if (!MI->isCopy() && !TII->isAsCheapAsAMove(MI))
344 // MI is cheap, we probably don't want to break the critical edge for it.
345 // However, if this would allow some definitions of its source operands
346 // to be sunk then it's probably worth it.
347 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
348 const MachineOperand &MO = MI->getOperand(i);
349 if (!MO.isReg() || !MO.isUse())
351 unsigned Reg = MO.getReg();
355 // We don't move live definitions of physical registers,
356 // so sinking their uses won't enable any opportunities.
357 if (TargetRegisterInfo::isPhysicalRegister(Reg))
360 // If this instruction is the only user of a virtual register,
361 // check if breaking the edge will enable sinking
362 // both this instruction and the defining instruction.
363 if (MRI->hasOneNonDBGUse(Reg)) {
364 // If the definition resides in same MBB,
365 // claim it's likely we can sink these together.
366 // If definition resides elsewhere, we aren't
367 // blocking it from being sunk so don't break the edge.
368 MachineInstr *DefMI = MRI->getVRegDef(Reg);
369 if (DefMI->getParent() == MI->getParent())
377 bool MachineSinking::PostponeSplitCriticalEdge(MachineInstr *MI,
378 MachineBasicBlock *FromBB,
379 MachineBasicBlock *ToBB,
381 if (!isWorthBreakingCriticalEdge(MI, FromBB, ToBB))
384 // Avoid breaking back edge. From == To means backedge for single BB loop.
385 if (!SplitEdges || FromBB == ToBB)
388 // Check for backedges of more "complex" loops.
389 if (LI->getLoopFor(FromBB) == LI->getLoopFor(ToBB) &&
390 LI->isLoopHeader(ToBB))
393 // It's not always legal to break critical edges and sink the computation
401 // ... no uses of v1024
407 // If BB#1 -> BB#3 edge is broken and computation of v1024 is inserted:
416 // ... no uses of v1024
422 // This is incorrect since v1024 is not computed along the BB#1->BB#2->BB#3
423 // flow. We need to ensure the new basic block where the computation is
424 // sunk to dominates all the uses.
425 // It's only legal to break critical edge and sink the computation to the
426 // new block if all the predecessors of "To", except for "From", are
427 // not dominated by "From". Given SSA property, this means these
428 // predecessors are dominated by "To".
430 // There is no need to do this check if all the uses are PHI nodes. PHI
431 // sources are only defined on the specific predecessor edges.
433 for (MachineBasicBlock::pred_iterator PI = ToBB->pred_begin(),
434 E = ToBB->pred_end(); PI != E; ++PI) {
437 if (!DT->dominates(ToBB, *PI))
442 ToSplit.insert(std::make_pair(FromBB, ToBB));
447 static bool AvoidsSinking(MachineInstr *MI, MachineRegisterInfo *MRI) {
448 return MI->isInsertSubreg() || MI->isSubregToReg() || MI->isRegSequence();
451 /// collectDebgValues - Scan instructions following MI and collect any
452 /// matching DBG_VALUEs.
453 static void collectDebugValues(MachineInstr *MI,
454 SmallVectorImpl<MachineInstr *> &DbgValues) {
456 if (!MI->getOperand(0).isReg())
459 MachineBasicBlock::iterator DI = MI; ++DI;
460 for (MachineBasicBlock::iterator DE = MI->getParent()->end();
462 if (!DI->isDebugValue())
464 if (DI->getOperand(0).isReg() &&
465 DI->getOperand(0).getReg() == MI->getOperand(0).getReg())
466 DbgValues.push_back(DI);
470 /// isPostDominatedBy - Return true if A is post dominated by B.
471 static bool isPostDominatedBy(MachineBasicBlock *A, MachineBasicBlock *B) {
473 // FIXME - Use real post dominator.
474 if (A->succ_size() != 2)
476 MachineBasicBlock::succ_iterator I = A->succ_begin();
479 MachineBasicBlock *OtherSuccBlock = *I;
480 if (OtherSuccBlock->succ_size() != 1 ||
481 *(OtherSuccBlock->succ_begin()) != B)
487 /// isProfitableToSinkTo - Return true if it is profitable to sink MI.
488 bool MachineSinking::isProfitableToSinkTo(unsigned Reg, MachineInstr *MI,
489 MachineBasicBlock *MBB,
490 MachineBasicBlock *SuccToSinkTo) {
491 assert (MI && "Invalid MachineInstr!");
492 assert (SuccToSinkTo && "Invalid SinkTo Candidate BB");
494 if (MBB == SuccToSinkTo)
497 // It is profitable if SuccToSinkTo does not post dominate current block.
498 if (!isPostDominatedBy(MBB, SuccToSinkTo))
501 // Check if only use in post dominated block is PHI instruction.
502 bool NonPHIUse = false;
503 for (MachineInstr &UseInst : MRI->use_nodbg_instructions(Reg)) {
504 MachineBasicBlock *UseBlock = UseInst.getParent();
505 if (UseBlock == SuccToSinkTo && !UseInst.isPHI())
511 // If SuccToSinkTo post dominates then also it may be profitable if MI
512 // can further profitably sinked into another block in next round.
513 bool BreakPHIEdge = false;
514 // FIXME - If finding successor is compile time expensive then catch results.
515 if (MachineBasicBlock *MBB2 = FindSuccToSinkTo(MI, SuccToSinkTo, BreakPHIEdge))
516 return isProfitableToSinkTo(Reg, MI, SuccToSinkTo, MBB2);
518 // If SuccToSinkTo is final destination and it is a post dominator of current
519 // block then it is not profitable to sink MI into SuccToSinkTo block.
523 /// FindSuccToSinkTo - Find a successor to sink this instruction to.
524 MachineBasicBlock *MachineSinking::FindSuccToSinkTo(MachineInstr *MI,
525 MachineBasicBlock *MBB,
526 bool &BreakPHIEdge) {
528 assert (MI && "Invalid MachineInstr!");
529 assert (MBB && "Invalid MachineBasicBlock!");
531 // Loop over all the operands of the specified instruction. If there is
532 // anything we can't handle, bail out.
534 // SuccToSinkTo - This is the successor to sink this instruction to, once we
536 MachineBasicBlock *SuccToSinkTo = nullptr;
537 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
538 const MachineOperand &MO = MI->getOperand(i);
539 if (!MO.isReg()) continue; // Ignore non-register operands.
541 unsigned Reg = MO.getReg();
542 if (Reg == 0) continue;
544 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
546 // If the physreg has no defs anywhere, it's just an ambient register
547 // and we can freely move its uses. Alternatively, if it's allocatable,
548 // it could get allocated to something with a def during allocation.
549 if (!MRI->isConstantPhysReg(Reg, *MBB->getParent()))
551 } else if (!MO.isDead()) {
552 // A def that isn't dead. We can't move it.
556 // Virtual register uses are always safe to sink.
557 if (MO.isUse()) continue;
559 // If it's not safe to move defs of the register class, then abort.
560 if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg)))
563 // FIXME: This picks a successor to sink into based on having one
564 // successor that dominates all the uses. However, there are cases where
565 // sinking can happen but where the sink point isn't a successor. For
572 // the instruction could be sunk over the whole diamond for the
573 // if/then/else (or loop, etc), allowing it to be sunk into other blocks
576 // Virtual register defs can only be sunk if all their uses are in blocks
577 // dominated by one of the successors.
579 // If a previous operand picked a block to sink to, then this operand
580 // must be sinkable to the same block.
581 bool LocalUse = false;
582 if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo, MBB,
583 BreakPHIEdge, LocalUse))
589 // Otherwise, we should look at all the successors and decide which one
590 // we should sink to. If we have reliable block frequency information
591 // (frequency != 0) available, give successors with smaller frequencies
592 // higher priority, otherwise prioritize smaller loop depths.
593 SmallVector<MachineBasicBlock*, 4> Succs(MBB->succ_begin(),
595 // Sort Successors according to their loop depth or block frequency info.
597 Succs.begin(), Succs.end(),
598 [this](const MachineBasicBlock *L, const MachineBasicBlock *R) {
599 uint64_t LHSFreq = MBFI ? MBFI->getBlockFreq(L).getFrequency() : 0;
600 uint64_t RHSFreq = MBFI ? MBFI->getBlockFreq(R).getFrequency() : 0;
601 bool HasBlockFreq = LHSFreq != 0 && RHSFreq != 0;
602 return HasBlockFreq ? LHSFreq < RHSFreq
603 : LI->getLoopDepth(L) < LI->getLoopDepth(R);
605 for (SmallVectorImpl<MachineBasicBlock *>::iterator SI = Succs.begin(),
606 E = Succs.end(); SI != E; ++SI) {
607 MachineBasicBlock *SuccBlock = *SI;
608 bool LocalUse = false;
609 if (AllUsesDominatedByBlock(Reg, SuccBlock, MBB,
610 BreakPHIEdge, LocalUse)) {
611 SuccToSinkTo = SuccBlock;
615 // Def is used locally, it's never safe to move this def.
619 // If we couldn't find a block to sink to, ignore this instruction.
622 if (!isProfitableToSinkTo(Reg, MI, MBB, SuccToSinkTo))
627 // It is not possible to sink an instruction into its own block. This can
628 // happen with loops.
629 if (MBB == SuccToSinkTo)
632 // It's not safe to sink instructions to EH landing pad. Control flow into
633 // landing pad is implicitly defined.
634 if (SuccToSinkTo && SuccToSinkTo->isLandingPad())
640 /// SinkInstruction - Determine whether it is safe to sink the specified machine
641 /// instruction out of its current block into a successor.
642 bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) {
643 // Don't sink insert_subreg, subreg_to_reg, reg_sequence. These are meant to
644 // be close to the source to make it easier to coalesce.
645 if (AvoidsSinking(MI, MRI))
648 // Check if it's safe to move the instruction.
649 if (!MI->isSafeToMove(TII, AA, SawStore))
652 // FIXME: This should include support for sinking instructions within the
653 // block they are currently in to shorten the live ranges. We often get
654 // instructions sunk into the top of a large block, but it would be better to
655 // also sink them down before their first use in the block. This xform has to
656 // be careful not to *increase* register pressure though, e.g. sinking
657 // "x = y + z" down if it kills y and z would increase the live ranges of y
658 // and z and only shrink the live range of x.
660 bool BreakPHIEdge = false;
661 MachineBasicBlock *ParentBlock = MI->getParent();
662 MachineBasicBlock *SuccToSinkTo = FindSuccToSinkTo(MI, ParentBlock, BreakPHIEdge);
664 // If there are no outputs, it must have side-effects.
669 // If the instruction to move defines a dead physical register which is live
670 // when leaving the basic block, don't move it because it could turn into a
671 // "zombie" define of that preg. E.g., EFLAGS. (<rdar://problem/8030636>)
672 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
673 const MachineOperand &MO = MI->getOperand(I);
674 if (!MO.isReg()) continue;
675 unsigned Reg = MO.getReg();
676 if (Reg == 0 || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
677 if (SuccToSinkTo->isLiveIn(Reg))
681 DEBUG(dbgs() << "Sink instr " << *MI << "\tinto block " << *SuccToSinkTo);
683 // If the block has multiple predecessors, this is a critical edge.
684 // Decide if we can sink along it or need to break the edge.
685 if (SuccToSinkTo->pred_size() > 1) {
686 // We cannot sink a load across a critical edge - there may be stores in
688 bool TryBreak = false;
690 if (!MI->isSafeToMove(TII, AA, store)) {
691 DEBUG(dbgs() << " *** NOTE: Won't sink load along critical edge.\n");
695 // We don't want to sink across a critical edge if we don't dominate the
696 // successor. We could be introducing calculations to new code paths.
697 if (!TryBreak && !DT->dominates(ParentBlock, SuccToSinkTo)) {
698 DEBUG(dbgs() << " *** NOTE: Critical edge found\n");
702 // Don't sink instructions into a loop.
703 if (!TryBreak && LI->isLoopHeader(SuccToSinkTo)) {
704 DEBUG(dbgs() << " *** NOTE: Loop header found\n");
708 // Otherwise we are OK with sinking along a critical edge.
710 DEBUG(dbgs() << "Sinking along critical edge.\n");
712 // Mark this edge as to be split.
713 // If the edge can actually be split, the next iteration of the main loop
714 // will sink MI in the newly created block.
716 PostponeSplitCriticalEdge(MI, ParentBlock, SuccToSinkTo, BreakPHIEdge);
718 DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to "
719 "break critical edge\n");
720 // The instruction will not be sunk this time.
726 // BreakPHIEdge is true if all the uses are in the successor MBB being
727 // sunken into and they are all PHI nodes. In this case, machine-sink must
728 // break the critical edge first.
729 bool Status = PostponeSplitCriticalEdge(MI, ParentBlock,
730 SuccToSinkTo, BreakPHIEdge);
732 DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to "
733 "break critical edge\n");
734 // The instruction will not be sunk this time.
738 // Determine where to insert into. Skip phi nodes.
739 MachineBasicBlock::iterator InsertPos = SuccToSinkTo->begin();
740 while (InsertPos != SuccToSinkTo->end() && InsertPos->isPHI())
743 // collect matching debug values.
744 SmallVector<MachineInstr *, 2> DbgValuesToSink;
745 collectDebugValues(MI, DbgValuesToSink);
747 // Move the instruction.
748 SuccToSinkTo->splice(InsertPos, ParentBlock, MI,
749 ++MachineBasicBlock::iterator(MI));
751 // Move debug values.
752 for (SmallVectorImpl<MachineInstr *>::iterator DBI = DbgValuesToSink.begin(),
753 DBE = DbgValuesToSink.end(); DBI != DBE; ++DBI) {
754 MachineInstr *DbgMI = *DBI;
755 SuccToSinkTo->splice(InsertPos, ParentBlock, DbgMI,
756 ++MachineBasicBlock::iterator(DbgMI));
759 // Conservatively, clear any kill flags, since it's possible that they are no