1 //===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/Function.h"
27 #include "llvm/CodeGen/LiveVariables.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/ADT/DenseSet.h"
36 #include "llvm/ADT/SetOperations.h"
37 #include "llvm/ADT/SmallVector.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/raw_ostream.h"
45 struct VISIBILITY_HIDDEN MachineVerifier : public MachineFunctionPass {
46 static char ID; // Pass ID, replacement for typeid
48 MachineVerifier(bool allowDoubleDefs = false) :
49 MachineFunctionPass(&ID),
50 allowVirtDoubleDefs(allowDoubleDefs),
51 allowPhysDoubleDefs(allowDoubleDefs),
52 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
55 void getAnalysisUsage(AnalysisUsage &AU) const {
57 MachineFunctionPass::getAnalysisUsage(AU);
60 bool runOnMachineFunction(MachineFunction &MF);
62 const bool allowVirtDoubleDefs;
63 const bool allowPhysDoubleDefs;
65 const char *const OutFileName;
67 const MachineFunction *MF;
68 const TargetMachine *TM;
69 const TargetRegisterInfo *TRI;
70 const MachineRegisterInfo *MRI;
74 typedef SmallVector<unsigned, 16> RegVector;
75 typedef DenseSet<unsigned> RegSet;
76 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
78 BitVector regsReserved;
80 RegVector regsDefined, regsDead, regsKilled;
81 RegSet regsLiveInButUnused;
83 // Add Reg and any sub-registers to RV
84 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
86 if (TargetRegisterInfo::isPhysicalRegister(Reg))
87 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
92 // Is this MBB reachable from the MF entry point?
95 // Vregs that must be live in because they are used without being
96 // defined. Map value is the user.
99 // Vregs that must be dead in because they are defined without being
100 // killed first. Map value is the defining instruction.
103 // Regs killed in MBB. They may be defined again, and will then be in both
104 // regsKilled and regsLiveOut.
107 // Regs defined in MBB and live out. Note that vregs passing through may
108 // be live out without being mentioned here.
111 // Vregs that pass through MBB untouched. This set is disjoint from
112 // regsKilled and regsLiveOut.
115 BBInfo() : reachable(false) {}
117 // Add register to vregsPassed if it belongs there. Return true if
119 bool addPassed(unsigned Reg) {
120 if (!TargetRegisterInfo::isVirtualRegister(Reg))
122 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
124 return vregsPassed.insert(Reg).second;
127 // Same for a full set.
128 bool addPassed(const RegSet &RS) {
129 bool changed = false;
130 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
136 // Live-out registers are either in regsLiveOut or vregsPassed.
137 bool isLiveOut(unsigned Reg) const {
138 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
142 // Extra register info per MBB.
143 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
145 bool isReserved(unsigned Reg) {
146 return Reg < regsReserved.size() && regsReserved.test(Reg);
149 void visitMachineFunctionBefore();
150 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
151 void visitMachineInstrBefore(const MachineInstr *MI);
152 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
153 void visitMachineInstrAfter(const MachineInstr *MI);
154 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
155 void visitMachineFunctionAfter();
157 void report(const char *msg, const MachineFunction *MF);
158 void report(const char *msg, const MachineBasicBlock *MBB);
159 void report(const char *msg, const MachineInstr *MI);
160 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
162 void markReachable(const MachineBasicBlock *MBB);
163 void calcMaxRegsPassed();
164 void calcMinRegsPassed();
165 void checkPHIOps(const MachineBasicBlock *MBB);
169 char MachineVerifier::ID = 0;
170 static RegisterPass<MachineVerifier>
171 MachineVer("machineverifier", "Verify generated machine code");
172 static const PassInfo *const MachineVerifyID = &MachineVer;
174 FunctionPass *llvm::createMachineVerifierPass(bool allowPhysDoubleDefs) {
175 return new MachineVerifier(allowPhysDoubleDefs);
178 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
179 raw_ostream *OutFile = 0;
181 std::string ErrorInfo;
182 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
183 raw_fd_ostream::F_Append);
184 if (!ErrorInfo.empty()) {
185 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
197 TM = &MF.getTarget();
198 TRI = TM->getRegisterInfo();
199 MRI = &MF.getRegInfo();
201 visitMachineFunctionBefore();
202 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
204 visitMachineBasicBlockBefore(MFI);
205 for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
206 MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
207 visitMachineInstrBefore(MBBI);
208 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
209 visitMachineOperand(&MBBI->getOperand(I), I);
210 visitMachineInstrAfter(MBBI);
212 visitMachineBasicBlockAfter(MFI);
214 visitMachineFunctionAfter();
218 else if (foundErrors)
219 llvm_report_error("Found "+Twine(foundErrors)+" machine code errors.");
226 regsLiveInButUnused.clear();
229 return false; // no changes
232 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
237 *OS << "*** Bad machine code: " << msg << " ***\n"
238 << "- function: " << MF->getFunction()->getNameStr() << "\n";
242 MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB)
245 report(msg, MBB->getParent());
246 *OS << "- basic block: " << MBB->getBasicBlock()->getNameStr()
248 << " (#" << MBB->getNumber() << ")\n";
252 MachineVerifier::report(const char *msg, const MachineInstr *MI)
255 report(msg, MI->getParent());
256 *OS << "- instruction: ";
261 MachineVerifier::report(const char *msg,
262 const MachineOperand *MO, unsigned MONum)
265 report(msg, MO->getParent());
266 *OS << "- operand " << MONum << ": ";
272 MachineVerifier::markReachable(const MachineBasicBlock *MBB)
274 BBInfo &MInfo = MBBInfoMap[MBB];
275 if (!MInfo.reachable) {
276 MInfo.reachable = true;
277 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
278 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
284 MachineVerifier::visitMachineFunctionBefore()
286 regsReserved = TRI->getReservedRegs(*MF);
288 // A sub-register of a reserved register is also reserved
289 for (int Reg = regsReserved.find_first(); Reg>=0;
290 Reg = regsReserved.find_next(Reg)) {
291 for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
292 // FIXME: This should probably be:
293 // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
294 regsReserved.set(*Sub);
297 markReachable(&MF->front());
301 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB)
303 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
305 // Start with minimal CFG sanity checks.
306 MachineFunction::const_iterator MBBI = MBB;
308 if (MBBI != MF->end()) {
309 // Block is not last in function.
310 if (!MBB->isSuccessor(MBBI)) {
311 // Block does not fall through.
313 report("MBB doesn't fall through but is empty!", MBB);
316 if (TII->BlockHasNoFallThrough(*MBB)) {
318 report("TargetInstrInfo says the block has no fall through, but the "
319 "block is empty!", MBB);
320 } else if (!MBB->back().getDesc().isBarrier()) {
321 report("TargetInstrInfo says the block has no fall through, but the "
322 "block does not end in a barrier!", MBB);
326 // Block is last in function.
328 report("MBB is last in function but is empty!", MBB);
332 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
333 MachineBasicBlock *TBB = 0, *FBB = 0;
334 SmallVector<MachineOperand, 4> Cond;
335 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
337 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
338 // check whether its answers match up with reality.
340 // Block falls through to its successor.
341 MachineFunction::const_iterator MBBI = MBB;
343 if (MBBI == MF->end()) {
344 // It's possible that the block legitimately ends with a noreturn
345 // call or an unreachable, in which case it won't actually fall
346 // out the bottom of the function.
347 } else if (MBB->succ_empty()) {
348 // It's possible that the block legitimately ends with a noreturn
349 // call or an unreachable, in which case it won't actuall fall
351 } else if (MBB->succ_size() != 1) {
352 report("MBB exits via unconditional fall-through but doesn't have "
353 "exactly one CFG successor!", MBB);
354 } else if (MBB->succ_begin()[0] != MBBI) {
355 report("MBB exits via unconditional fall-through but its successor "
356 "differs from its CFG successor!", MBB);
358 if (!MBB->empty() && MBB->back().getDesc().isBarrier()) {
359 report("MBB exits via unconditional fall-through but ends with a "
360 "barrier instruction!", MBB);
363 report("MBB exits via unconditional fall-through but has a condition!",
366 } else if (TBB && !FBB && Cond.empty()) {
367 // Block unconditionally branches somewhere.
368 if (MBB->succ_size() != 1) {
369 report("MBB exits via unconditional branch but doesn't have "
370 "exactly one CFG successor!", MBB);
371 } else if (MBB->succ_begin()[0] != TBB) {
372 report("MBB exits via unconditional branch but the CFG "
373 "successor doesn't match the actual successor!", MBB);
376 report("MBB exits via unconditional branch but doesn't contain "
377 "any instructions!", MBB);
378 } else if (!MBB->back().getDesc().isBarrier()) {
379 report("MBB exits via unconditional branch but doesn't end with a "
380 "barrier instruction!", MBB);
381 } else if (!MBB->back().getDesc().isTerminator()) {
382 report("MBB exits via unconditional branch but the branch isn't a "
383 "terminator instruction!", MBB);
385 } else if (TBB && !FBB && !Cond.empty()) {
386 // Block conditionally branches somewhere, otherwise falls through.
387 MachineFunction::const_iterator MBBI = MBB;
389 if (MBBI == MF->end()) {
390 report("MBB conditionally falls through out of function!", MBB);
391 } if (MBB->succ_size() != 2) {
392 report("MBB exits via conditional branch/fall-through but doesn't have "
393 "exactly two CFG successors!", MBB);
394 } else if ((MBB->succ_begin()[0] == TBB && MBB->succ_end()[1] == MBBI) ||
395 (MBB->succ_begin()[1] == TBB && MBB->succ_end()[0] == MBBI)) {
396 report("MBB exits via conditional branch/fall-through but the CFG "
397 "successors don't match the actual successors!", MBB);
400 report("MBB exits via conditional branch/fall-through but doesn't "
401 "contain any instructions!", MBB);
402 } else if (MBB->back().getDesc().isBarrier()) {
403 report("MBB exits via conditional branch/fall-through but ends with a "
404 "barrier instruction!", MBB);
405 } else if (!MBB->back().getDesc().isTerminator()) {
406 report("MBB exits via conditional branch/fall-through but the branch "
407 "isn't a terminator instruction!", MBB);
409 } else if (TBB && FBB) {
410 // Block conditionally branches somewhere, otherwise branches
412 if (MBB->succ_size() != 2) {
413 report("MBB exits via conditional branch/branch but doesn't have "
414 "exactly two CFG successors!", MBB);
415 } else if ((MBB->succ_begin()[0] == TBB && MBB->succ_end()[1] == FBB) ||
416 (MBB->succ_begin()[1] == TBB && MBB->succ_end()[0] == FBB)) {
417 report("MBB exits via conditional branch/branch but the CFG "
418 "successors don't match the actual successors!", MBB);
421 report("MBB exits via conditional branch/branch but doesn't "
422 "contain any instructions!", MBB);
423 } else if (!MBB->back().getDesc().isBarrier()) {
424 report("MBB exits via conditional branch/branch but doesn't end with a "
425 "barrier instruction!", MBB);
426 } else if (!MBB->back().getDesc().isTerminator()) {
427 report("MBB exits via conditional branch/branch but the branch "
428 "isn't a terminator instruction!", MBB);
431 report("MBB exits via conditinal branch/branch but there's no "
435 report("AnalyzeBranch returned invalid data!", MBB);
440 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
441 E = MBB->livein_end(); I != E; ++I) {
442 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
443 report("MBB live-in list contains non-physical register", MBB);
447 for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
450 regsLiveInButUnused = regsLive;
452 const MachineFrameInfo *MFI = MF->getFrameInfo();
453 assert(MFI && "Function has no frame info");
454 BitVector PR = MFI->getPristineRegs(MBB);
455 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
457 for (const unsigned *R = TRI->getSubRegisters(I); *R; R++)
466 MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI)
468 const TargetInstrDesc &TI = MI->getDesc();
469 if (MI->getNumOperands() < TI.getNumOperands()) {
470 report("Too few operands", MI);
471 *OS << TI.getNumOperands() << " operands expected, but "
472 << MI->getNumExplicitOperands() << " given.\n";
477 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
479 const MachineInstr *MI = MO->getParent();
480 const TargetInstrDesc &TI = MI->getDesc();
482 // The first TI.NumDefs operands must be explicit register defines
483 if (MONum < TI.getNumDefs()) {
485 report("Explicit definition must be a register", MO, MONum);
486 else if (!MO->isDef())
487 report("Explicit definition marked as use", MO, MONum);
488 else if (MO->isImplicit())
489 report("Explicit definition marked as implicit", MO, MONum);
490 } else if (MONum < TI.getNumOperands()) {
493 report("Explicit operand marked as def", MO, MONum);
494 if (MO->isImplicit())
495 report("Explicit operand marked as implicit", MO, MONum);
498 if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic())
499 report("Extra explicit operand on non-variadic instruction", MO, MONum);
502 switch (MO->getType()) {
503 case MachineOperand::MO_Register: {
504 const unsigned Reg = MO->getReg();
508 // Check Live Variables.
510 // An <undef> doesn't refer to any register, so just skip it.
511 } else if (MO->isUse()) {
512 regsLiveInButUnused.erase(Reg);
515 addRegWithSubRegs(regsKilled, Reg);
516 // Tied operands on two-address instuctions MUST NOT have a <kill> flag.
517 if (MI->isRegTiedToDefOperand(MONum))
518 report("Illegal kill flag on two-address instruction operand",
521 // TwoAddress instr modifying a reg is treated as kill+def.
523 if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
524 MI->getOperand(defIdx).getReg() == Reg)
525 addRegWithSubRegs(regsKilled, Reg);
527 // Use of a dead register.
528 if (!regsLive.count(Reg)) {
529 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
530 // Reserved registers may be used even when 'dead'.
531 if (!isReserved(Reg))
532 report("Using an undefined physical register", MO, MONum);
534 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
535 // We don't know which virtual registers are live in, so only complain
536 // if vreg was killed in this MBB. Otherwise keep track of vregs that
537 // must be live in. PHI instructions are handled separately.
538 if (MInfo.regsKilled.count(Reg))
539 report("Using a killed virtual register", MO, MONum);
540 else if (MI->getOpcode() != TargetInstrInfo::PHI)
541 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
547 // TODO: verify that earlyclobber ops are not used.
549 addRegWithSubRegs(regsDead, Reg);
551 addRegWithSubRegs(regsDefined, Reg);
554 // Check register classes.
555 if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
556 const TargetOperandInfo &TOI = TI.OpInfo[MONum];
557 unsigned SubIdx = MO->getSubReg();
559 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
562 unsigned s = TRI->getSubReg(Reg, SubIdx);
564 report("Invalid subregister index for physical register",
570 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
571 if (!DRC->contains(sr)) {
572 report("Illegal physical register for instruction", MO, MONum);
573 *OS << TRI->getName(sr) << " is not a "
574 << DRC->getName() << " register.\n";
579 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
581 if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) {
582 report("Invalid subregister index for virtual register", MO, MONum);
585 RC = *(RC->subregclasses_begin()+SubIdx);
587 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
588 if (RC != DRC && !RC->hasSuperClass(DRC)) {
589 report("Illegal virtual register for instruction", MO, MONum);
590 *OS << "Expected a " << DRC->getName() << " register, but got a "
591 << RC->getName() << " register\n";
599 case MachineOperand::MO_MachineBasicBlock:
600 if (MI->getOpcode() == TargetInstrInfo::PHI) {
601 if (!MO->getMBB()->isSuccessor(MI->getParent()))
602 report("PHI operand is not in the CFG", MO, MONum);
612 MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI)
614 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
615 set_union(MInfo.regsKilled, regsKilled);
616 set_subtract(regsLive, regsKilled);
619 // Verify that both <def> and <def,dead> operands refer to dead registers.
620 RegVector defs(regsDefined);
621 defs.append(regsDead.begin(), regsDead.end());
623 for (RegVector::const_iterator I = defs.begin(), E = defs.end();
625 if (regsLive.count(*I)) {
626 if (TargetRegisterInfo::isPhysicalRegister(*I)) {
627 if (!allowPhysDoubleDefs && !isReserved(*I) &&
628 !regsLiveInButUnused.count(*I)) {
629 report("Redefining a live physical register", MI);
630 *OS << "Register " << TRI->getName(*I)
631 << " was defined but already live.\n";
634 if (!allowVirtDoubleDefs) {
635 report("Redefining a live virtual register", MI);
636 *OS << "Virtual register %reg" << *I
637 << " was defined but already live.\n";
640 } else if (TargetRegisterInfo::isVirtualRegister(*I) &&
641 !MInfo.regsKilled.count(*I)) {
642 // Virtual register defined without being killed first must be dead on
644 MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
648 set_subtract(regsLive, regsDead); regsDead.clear();
649 set_union(regsLive, regsDefined); regsDefined.clear();
653 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB)
655 MBBInfoMap[MBB].regsLiveOut = regsLive;
659 // Calculate the largest possible vregsPassed sets. These are the registers that
660 // can pass through an MBB live, but may not be live every time. It is assumed
661 // that all vregsPassed sets are empty before the call.
663 MachineVerifier::calcMaxRegsPassed()
665 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
666 // have any vregsPassed.
667 DenseSet<const MachineBasicBlock*> todo;
668 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
670 const MachineBasicBlock &MBB(*MFI);
671 BBInfo &MInfo = MBBInfoMap[&MBB];
672 if (!MInfo.reachable)
674 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
675 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
676 BBInfo &SInfo = MBBInfoMap[*SuI];
677 if (SInfo.addPassed(MInfo.regsLiveOut))
682 // Iteratively push vregsPassed to successors. This will converge to the same
683 // final state regardless of DenseSet iteration order.
684 while (!todo.empty()) {
685 const MachineBasicBlock *MBB = *todo.begin();
687 BBInfo &MInfo = MBBInfoMap[MBB];
688 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
689 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
692 BBInfo &SInfo = MBBInfoMap[*SuI];
693 if (SInfo.addPassed(MInfo.vregsPassed))
699 // Calculate the minimum vregsPassed set. These are the registers that always
700 // pass live through an MBB. The calculation assumes that calcMaxRegsPassed has
701 // been called earlier.
703 MachineVerifier::calcMinRegsPassed()
705 DenseSet<const MachineBasicBlock*> todo;
706 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
710 while (!todo.empty()) {
711 const MachineBasicBlock *MBB = *todo.begin();
713 BBInfo &MInfo = MBBInfoMap[MBB];
715 // Remove entries from vRegsPassed that are not live out from all
716 // reachable predecessors.
718 for (RegSet::iterator I = MInfo.vregsPassed.begin(),
719 E = MInfo.vregsPassed.end(); I != E; ++I) {
720 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
721 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
722 BBInfo &PrInfo = MBBInfoMap[*PrI];
723 if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) {
729 // If any regs removed, we need to recheck successors.
731 set_subtract(MInfo.vregsPassed, dead);
732 todo.insert(MBB->succ_begin(), MBB->succ_end());
737 // Check PHI instructions at the beginning of MBB. It is assumed that
738 // calcMinRegsPassed has been run so BBInfo::isLiveOut is valid.
740 MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB)
742 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
743 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
744 DenseSet<const MachineBasicBlock*> seen;
746 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
747 unsigned Reg = BBI->getOperand(i).getReg();
748 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
749 if (!Pre->isSuccessor(MBB))
752 BBInfo &PrInfo = MBBInfoMap[Pre];
753 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
754 report("PHI operand is not live-out from predecessor",
755 &BBI->getOperand(i), i);
758 // Did we see all predecessors?
759 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
760 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
761 if (!seen.count(*PrI)) {
762 report("Missing PHI operand", BBI);
763 *OS << "MBB #" << (*PrI)->getNumber()
764 << " is a predecessor according to the CFG.\n";
771 MachineVerifier::visitMachineFunctionAfter()
775 // With the maximal set of vregsPassed we can verify dead-in registers.
776 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
778 BBInfo &MInfo = MBBInfoMap[MFI];
780 // Skip unreachable MBBs.
781 if (!MInfo.reachable)
784 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
785 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
786 BBInfo &PrInfo = MBBInfoMap[*PrI];
787 if (!PrInfo.reachable)
790 // Verify physical live-ins. EH landing pads have magic live-ins so we
792 if (!MFI->isLandingPad()) {
793 for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(),
794 E = MFI->livein_end(); I != E; ++I) {
795 if (TargetRegisterInfo::isPhysicalRegister(*I) &&
796 !isReserved (*I) && !PrInfo.isLiveOut(*I)) {
797 report("Live-in physical register is not live-out from predecessor",
799 *OS << "Register " << TRI->getName(*I)
800 << " is not live-out from MBB #" << (*PrI)->getNumber()
807 // Verify dead-in virtual registers.
808 if (!allowVirtDoubleDefs) {
809 for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
810 E = MInfo.vregsDeadIn.end(); I != E; ++I) {
811 // DeadIn register must be in neither regsLiveOut or vregsPassed of
813 if (PrInfo.isLiveOut(I->first)) {
814 report("Live-in virtual register redefined", I->second);
815 *OS << "Register %reg" << I->first
816 << " was live-out from predecessor MBB #"
817 << (*PrI)->getNumber() << ".\n";
826 // With the minimal set of vregsPassed we can verify live-in virtual
827 // registers, including PHI instructions.
828 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
830 BBInfo &MInfo = MBBInfoMap[MFI];
832 // Skip unreachable MBBs.
833 if (!MInfo.reachable)
838 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
839 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
840 BBInfo &PrInfo = MBBInfoMap[*PrI];
841 if (!PrInfo.reachable)
844 for (RegMap::iterator I = MInfo.vregsLiveIn.begin(),
845 E = MInfo.vregsLiveIn.end(); I != E; ++I) {
846 if (!PrInfo.isLiveOut(I->first)) {
847 report("Used virtual register is not live-in", I->second);
848 *OS << "Register %reg" << I->first
849 << " is not live-out from predecessor MBB #"
850 << (*PrI)->getNumber()