1 //===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/Function.h"
27 #include "llvm/CodeGen/LiveVariables.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/ADT/DenseSet.h"
37 #include "llvm/ADT/SetOperations.h"
38 #include "llvm/ADT/SmallVector.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/raw_ostream.h"
45 struct MachineVerifier {
47 MachineVerifier(Pass *pass, bool allowDoubleDefs) :
49 allowVirtDoubleDefs(allowDoubleDefs),
50 allowPhysDoubleDefs(true),
51 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
54 bool runOnMachineFunction(MachineFunction &MF);
57 const bool allowVirtDoubleDefs;
58 const bool allowPhysDoubleDefs;
60 const char *const OutFileName;
62 const MachineFunction *MF;
63 const TargetMachine *TM;
64 const TargetRegisterInfo *TRI;
65 const MachineRegisterInfo *MRI;
69 typedef SmallVector<unsigned, 16> RegVector;
70 typedef DenseSet<unsigned> RegSet;
71 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
73 BitVector regsReserved;
75 RegVector regsDefined, regsDead, regsKilled;
76 RegSet regsLiveInButUnused;
78 // Add Reg and any sub-registers to RV
79 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
81 if (TargetRegisterInfo::isPhysicalRegister(Reg))
82 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
87 // Is this MBB reachable from the MF entry point?
90 // Vregs that must be live in because they are used without being
91 // defined. Map value is the user.
94 // Vregs that must be dead in because they are defined without being
95 // killed first. Map value is the defining instruction.
98 // Regs killed in MBB. They may be defined again, and will then be in both
99 // regsKilled and regsLiveOut.
102 // Regs defined in MBB and live out. Note that vregs passing through may
103 // be live out without being mentioned here.
106 // Vregs that pass through MBB untouched. This set is disjoint from
107 // regsKilled and regsLiveOut.
110 // Vregs that must pass through MBB because they are needed by a successor
111 // block. This set is disjoint from regsLiveOut.
112 RegSet vregsRequired;
114 BBInfo() : reachable(false) {}
116 // Add register to vregsPassed if it belongs there. Return true if
118 bool addPassed(unsigned Reg) {
119 if (!TargetRegisterInfo::isVirtualRegister(Reg))
121 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
123 return vregsPassed.insert(Reg).second;
126 // Same for a full set.
127 bool addPassed(const RegSet &RS) {
128 bool changed = false;
129 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
135 // Add register to vregsRequired if it belongs there. Return true if
137 bool addRequired(unsigned Reg) {
138 if (!TargetRegisterInfo::isVirtualRegister(Reg))
140 if (regsLiveOut.count(Reg))
142 return vregsRequired.insert(Reg).second;
145 // Same for a full set.
146 bool addRequired(const RegSet &RS) {
147 bool changed = false;
148 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
154 // Same for a full map.
155 bool addRequired(const RegMap &RM) {
156 bool changed = false;
157 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
158 if (addRequired(I->first))
163 // Live-out registers are either in regsLiveOut or vregsPassed.
164 bool isLiveOut(unsigned Reg) const {
165 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
169 // Extra register info per MBB.
170 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
172 bool isReserved(unsigned Reg) {
173 return Reg < regsReserved.size() && regsReserved.test(Reg);
176 // Analysis information if available
177 LiveVariables *LiveVars;
179 void visitMachineFunctionBefore();
180 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
181 void visitMachineInstrBefore(const MachineInstr *MI);
182 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
183 void visitMachineInstrAfter(const MachineInstr *MI);
184 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
185 void visitMachineFunctionAfter();
187 void report(const char *msg, const MachineFunction *MF);
188 void report(const char *msg, const MachineBasicBlock *MBB);
189 void report(const char *msg, const MachineInstr *MI);
190 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
192 void markReachable(const MachineBasicBlock *MBB);
193 void calcRegsPassed();
194 void checkPHIOps(const MachineBasicBlock *MBB);
196 void calcRegsRequired();
197 void verifyLiveVariables();
200 struct MachineVerifierPass : public MachineFunctionPass {
201 static char ID; // Pass ID, replacement for typeid
202 bool AllowDoubleDefs;
204 explicit MachineVerifierPass(bool allowDoubleDefs = false)
205 : MachineFunctionPass(&ID),
206 AllowDoubleDefs(allowDoubleDefs) {}
208 void getAnalysisUsage(AnalysisUsage &AU) const {
209 AU.setPreservesAll();
210 MachineFunctionPass::getAnalysisUsage(AU);
213 bool runOnMachineFunction(MachineFunction &MF) {
214 MF.verify(this, AllowDoubleDefs);
221 char MachineVerifierPass::ID = 0;
222 static RegisterPass<MachineVerifierPass>
223 MachineVer("machineverifier", "Verify generated machine code");
224 static const PassInfo *const MachineVerifyID = &MachineVer;
226 FunctionPass *llvm::createMachineVerifierPass(bool allowPhysDoubleDefs) {
227 return new MachineVerifierPass(allowPhysDoubleDefs);
230 void MachineFunction::verify(Pass *p, bool allowDoubleDefs) const {
231 MachineVerifier(p, allowDoubleDefs)
232 .runOnMachineFunction(const_cast<MachineFunction&>(*this));
235 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
236 raw_ostream *OutFile = 0;
238 std::string ErrorInfo;
239 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
240 raw_fd_ostream::F_Append);
241 if (!ErrorInfo.empty()) {
242 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
254 TM = &MF.getTarget();
255 TRI = TM->getRegisterInfo();
256 MRI = &MF.getRegInfo();
259 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
264 visitMachineFunctionBefore();
265 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
267 visitMachineBasicBlockBefore(MFI);
268 for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
269 MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
270 visitMachineInstrBefore(MBBI);
271 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
272 visitMachineOperand(&MBBI->getOperand(I), I);
273 visitMachineInstrAfter(MBBI);
275 visitMachineBasicBlockAfter(MFI);
277 visitMachineFunctionAfter();
281 else if (foundErrors)
282 report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
289 regsLiveInButUnused.clear();
292 return false; // no changes
295 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
300 *OS << "*** Bad machine code: " << msg << " ***\n"
301 << "- function: " << MF->getFunction()->getNameStr() << "\n";
304 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
306 report(msg, MBB->getParent());
307 *OS << "- basic block: " << MBB->getName()
309 << " (BB#" << MBB->getNumber() << ")\n";
312 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
314 report(msg, MI->getParent());
315 *OS << "- instruction: ";
319 void MachineVerifier::report(const char *msg,
320 const MachineOperand *MO, unsigned MONum) {
322 report(msg, MO->getParent());
323 *OS << "- operand " << MONum << ": ";
328 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
329 BBInfo &MInfo = MBBInfoMap[MBB];
330 if (!MInfo.reachable) {
331 MInfo.reachable = true;
332 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
333 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
338 void MachineVerifier::visitMachineFunctionBefore() {
339 regsReserved = TRI->getReservedRegs(*MF);
341 // A sub-register of a reserved register is also reserved
342 for (int Reg = regsReserved.find_first(); Reg>=0;
343 Reg = regsReserved.find_next(Reg)) {
344 for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
345 // FIXME: This should probably be:
346 // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
347 regsReserved.set(*Sub);
350 markReachable(&MF->front());
353 // Does iterator point to a and b as the first two elements?
354 static bool matchPair(MachineBasicBlock::const_succ_iterator i,
355 const MachineBasicBlock *a, const MachineBasicBlock *b) {
364 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
365 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
367 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
368 MachineBasicBlock *TBB = 0, *FBB = 0;
369 SmallVector<MachineOperand, 4> Cond;
370 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
372 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
373 // check whether its answers match up with reality.
375 // Block falls through to its successor.
376 MachineFunction::const_iterator MBBI = MBB;
378 if (MBBI == MF->end()) {
379 // It's possible that the block legitimately ends with a noreturn
380 // call or an unreachable, in which case it won't actually fall
381 // out the bottom of the function.
382 } else if (MBB->succ_empty()) {
383 // It's possible that the block legitimately ends with a noreturn
384 // call or an unreachable, in which case it won't actuall fall
386 } else if (MBB->succ_size() != 1) {
387 report("MBB exits via unconditional fall-through but doesn't have "
388 "exactly one CFG successor!", MBB);
389 } else if (MBB->succ_begin()[0] != MBBI) {
390 report("MBB exits via unconditional fall-through but its successor "
391 "differs from its CFG successor!", MBB);
393 if (!MBB->empty() && MBB->back().getDesc().isBarrier() &&
394 !TII->isPredicated(&MBB->back())) {
395 report("MBB exits via unconditional fall-through but ends with a "
396 "barrier instruction!", MBB);
399 report("MBB exits via unconditional fall-through but has a condition!",
402 } else if (TBB && !FBB && Cond.empty()) {
403 // Block unconditionally branches somewhere.
404 if (MBB->succ_size() != 1) {
405 report("MBB exits via unconditional branch but doesn't have "
406 "exactly one CFG successor!", MBB);
407 } else if (MBB->succ_begin()[0] != TBB) {
408 report("MBB exits via unconditional branch but the CFG "
409 "successor doesn't match the actual successor!", MBB);
412 report("MBB exits via unconditional branch but doesn't contain "
413 "any instructions!", MBB);
414 } else if (!MBB->back().getDesc().isBarrier()) {
415 report("MBB exits via unconditional branch but doesn't end with a "
416 "barrier instruction!", MBB);
417 } else if (!MBB->back().getDesc().isTerminator()) {
418 report("MBB exits via unconditional branch but the branch isn't a "
419 "terminator instruction!", MBB);
421 } else if (TBB && !FBB && !Cond.empty()) {
422 // Block conditionally branches somewhere, otherwise falls through.
423 MachineFunction::const_iterator MBBI = MBB;
425 if (MBBI == MF->end()) {
426 report("MBB conditionally falls through out of function!", MBB);
427 } if (MBB->succ_size() != 2) {
428 report("MBB exits via conditional branch/fall-through but doesn't have "
429 "exactly two CFG successors!", MBB);
430 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
431 report("MBB exits via conditional branch/fall-through but the CFG "
432 "successors don't match the actual successors!", MBB);
435 report("MBB exits via conditional branch/fall-through but doesn't "
436 "contain any instructions!", MBB);
437 } else if (MBB->back().getDesc().isBarrier()) {
438 report("MBB exits via conditional branch/fall-through but ends with a "
439 "barrier instruction!", MBB);
440 } else if (!MBB->back().getDesc().isTerminator()) {
441 report("MBB exits via conditional branch/fall-through but the branch "
442 "isn't a terminator instruction!", MBB);
444 } else if (TBB && FBB) {
445 // Block conditionally branches somewhere, otherwise branches
447 if (MBB->succ_size() != 2) {
448 report("MBB exits via conditional branch/branch but doesn't have "
449 "exactly two CFG successors!", MBB);
450 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
451 report("MBB exits via conditional branch/branch but the CFG "
452 "successors don't match the actual successors!", MBB);
455 report("MBB exits via conditional branch/branch but doesn't "
456 "contain any instructions!", MBB);
457 } else if (!MBB->back().getDesc().isBarrier()) {
458 report("MBB exits via conditional branch/branch but doesn't end with a "
459 "barrier instruction!", MBB);
460 } else if (!MBB->back().getDesc().isTerminator()) {
461 report("MBB exits via conditional branch/branch but the branch "
462 "isn't a terminator instruction!", MBB);
465 report("MBB exits via conditinal branch/branch but there's no "
469 report("AnalyzeBranch returned invalid data!", MBB);
474 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
475 E = MBB->livein_end(); I != E; ++I) {
476 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
477 report("MBB live-in list contains non-physical register", MBB);
481 for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
484 regsLiveInButUnused = regsLive;
486 const MachineFrameInfo *MFI = MF->getFrameInfo();
487 assert(MFI && "Function has no frame info");
488 BitVector PR = MFI->getPristineRegs(MBB);
489 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
491 for (const unsigned *R = TRI->getSubRegisters(I); *R; R++)
499 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
500 const TargetInstrDesc &TI = MI->getDesc();
501 if (MI->getNumOperands() < TI.getNumOperands()) {
502 report("Too few operands", MI);
503 *OS << TI.getNumOperands() << " operands expected, but "
504 << MI->getNumExplicitOperands() << " given.\n";
507 // Check the MachineMemOperands for basic consistency.
508 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
509 E = MI->memoperands_end(); I != E; ++I) {
510 if ((*I)->isLoad() && !TI.mayLoad())
511 report("Missing mayLoad flag", MI);
512 if ((*I)->isStore() && !TI.mayStore())
513 report("Missing mayStore flag", MI);
518 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
519 const MachineInstr *MI = MO->getParent();
520 const TargetInstrDesc &TI = MI->getDesc();
522 // The first TI.NumDefs operands must be explicit register defines
523 if (MONum < TI.getNumDefs()) {
525 report("Explicit definition must be a register", MO, MONum);
526 else if (!MO->isDef())
527 report("Explicit definition marked as use", MO, MONum);
528 else if (MO->isImplicit())
529 report("Explicit definition marked as implicit", MO, MONum);
530 } else if (MONum < TI.getNumOperands()) {
533 report("Explicit operand marked as def", MO, MONum);
534 if (MO->isImplicit())
535 report("Explicit operand marked as implicit", MO, MONum);
538 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
539 if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg())
540 report("Extra explicit operand on non-variadic instruction", MO, MONum);
543 switch (MO->getType()) {
544 case MachineOperand::MO_Register: {
545 const unsigned Reg = MO->getReg();
549 // Check Live Variables.
551 // An <undef> doesn't refer to any register, so just skip it.
552 } else if (MO->isUse()) {
553 regsLiveInButUnused.erase(Reg);
557 if (MI->isRegTiedToDefOperand(MONum, &defIdx)) {
558 // A two-addr use counts as a kill if use and def are the same.
559 unsigned DefReg = MI->getOperand(defIdx).getReg();
562 // ANd in that case an explicit kill flag is not allowed.
564 report("Illegal kill flag on two-address instruction operand",
566 } else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
567 report("Two-address instruction operands must be identical",
571 isKill = MO->isKill();
574 addRegWithSubRegs(regsKilled, Reg);
576 // Check that LiveVars knows this kill
577 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg)) {
578 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
579 if (std::find(VI.Kills.begin(),
580 VI.Kills.end(), MI) == VI.Kills.end())
581 report("Kill missing from LiveVariables", MO, MONum);
585 // Use of a dead register.
586 if (!regsLive.count(Reg)) {
587 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
588 // Reserved registers may be used even when 'dead'.
589 if (!isReserved(Reg))
590 report("Using an undefined physical register", MO, MONum);
592 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
593 // We don't know which virtual registers are live in, so only complain
594 // if vreg was killed in this MBB. Otherwise keep track of vregs that
595 // must be live in. PHI instructions are handled separately.
596 if (MInfo.regsKilled.count(Reg))
597 report("Using a killed virtual register", MO, MONum);
598 else if (!MI->isPHI())
599 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
605 // TODO: verify that earlyclobber ops are not used.
607 addRegWithSubRegs(regsDead, Reg);
609 addRegWithSubRegs(regsDefined, Reg);
612 // Check register classes.
613 if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
614 const TargetOperandInfo &TOI = TI.OpInfo[MONum];
615 unsigned SubIdx = MO->getSubReg();
617 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
620 unsigned s = TRI->getSubReg(Reg, SubIdx);
622 report("Invalid subregister index for physical register",
628 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
629 if (!DRC->contains(sr)) {
630 report("Illegal physical register for instruction", MO, MONum);
631 *OS << TRI->getName(sr) << " is not a "
632 << DRC->getName() << " register.\n";
637 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
639 const TargetRegisterClass *SRC = RC->getSubRegisterRegClass(SubIdx);
641 report("Invalid subregister index for virtual register", MO, MONum);
642 *OS << "Register class " << RC->getName()
643 << " does not support subreg index " << SubIdx << "\n";
648 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
649 if (RC != DRC && !RC->hasSuperClass(DRC)) {
650 report("Illegal virtual register for instruction", MO, MONum);
651 *OS << "Expected a " << DRC->getName() << " register, but got a "
652 << RC->getName() << " register\n";
660 case MachineOperand::MO_MachineBasicBlock:
661 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
662 report("PHI operand is not in the CFG", MO, MONum);
670 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
671 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
672 set_union(MInfo.regsKilled, regsKilled);
673 set_subtract(regsLive, regsKilled);
676 // Verify that both <def> and <def,dead> operands refer to dead registers.
677 RegVector defs(regsDefined);
678 defs.append(regsDead.begin(), regsDead.end());
680 for (RegVector::const_iterator I = defs.begin(), E = defs.end();
682 if (regsLive.count(*I)) {
683 if (TargetRegisterInfo::isPhysicalRegister(*I)) {
684 if (!allowPhysDoubleDefs && !isReserved(*I) &&
685 !regsLiveInButUnused.count(*I)) {
686 report("Redefining a live physical register", MI);
687 *OS << "Register " << TRI->getName(*I)
688 << " was defined but already live.\n";
691 if (!allowVirtDoubleDefs) {
692 report("Redefining a live virtual register", MI);
693 *OS << "Virtual register %reg" << *I
694 << " was defined but already live.\n";
697 } else if (TargetRegisterInfo::isVirtualRegister(*I) &&
698 !MInfo.regsKilled.count(*I)) {
699 // Virtual register defined without being killed first must be dead on
701 MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
705 set_subtract(regsLive, regsDead); regsDead.clear();
706 set_union(regsLive, regsDefined); regsDefined.clear();
710 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
711 MBBInfoMap[MBB].regsLiveOut = regsLive;
715 // Calculate the largest possible vregsPassed sets. These are the registers that
716 // can pass through an MBB live, but may not be live every time. It is assumed
717 // that all vregsPassed sets are empty before the call.
718 void MachineVerifier::calcRegsPassed() {
719 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
720 // have any vregsPassed.
721 DenseSet<const MachineBasicBlock*> todo;
722 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
724 const MachineBasicBlock &MBB(*MFI);
725 BBInfo &MInfo = MBBInfoMap[&MBB];
726 if (!MInfo.reachable)
728 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
729 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
730 BBInfo &SInfo = MBBInfoMap[*SuI];
731 if (SInfo.addPassed(MInfo.regsLiveOut))
736 // Iteratively push vregsPassed to successors. This will converge to the same
737 // final state regardless of DenseSet iteration order.
738 while (!todo.empty()) {
739 const MachineBasicBlock *MBB = *todo.begin();
741 BBInfo &MInfo = MBBInfoMap[MBB];
742 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
743 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
746 BBInfo &SInfo = MBBInfoMap[*SuI];
747 if (SInfo.addPassed(MInfo.vregsPassed))
753 // Calculate the set of virtual registers that must be passed through each basic
754 // block in order to satisfy the requirements of successor blocks. This is very
755 // similar to calcRegsPassed, only backwards.
756 void MachineVerifier::calcRegsRequired() {
757 // First push live-in regs to predecessors' vregsRequired.
758 DenseSet<const MachineBasicBlock*> todo;
759 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
761 const MachineBasicBlock &MBB(*MFI);
762 BBInfo &MInfo = MBBInfoMap[&MBB];
763 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
764 PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
765 BBInfo &PInfo = MBBInfoMap[*PrI];
766 if (PInfo.addRequired(MInfo.vregsLiveIn))
771 // Iteratively push vregsRequired to predecessors. This will converge to the
772 // same final state regardless of DenseSet iteration order.
773 while (!todo.empty()) {
774 const MachineBasicBlock *MBB = *todo.begin();
776 BBInfo &MInfo = MBBInfoMap[MBB];
777 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
778 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
781 BBInfo &SInfo = MBBInfoMap[*PrI];
782 if (SInfo.addRequired(MInfo.vregsRequired))
788 // Check PHI instructions at the beginning of MBB. It is assumed that
789 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
790 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
791 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
792 BBI != BBE && BBI->isPHI(); ++BBI) {
793 DenseSet<const MachineBasicBlock*> seen;
795 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
796 unsigned Reg = BBI->getOperand(i).getReg();
797 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
798 if (!Pre->isSuccessor(MBB))
801 BBInfo &PrInfo = MBBInfoMap[Pre];
802 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
803 report("PHI operand is not live-out from predecessor",
804 &BBI->getOperand(i), i);
807 // Did we see all predecessors?
808 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
809 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
810 if (!seen.count(*PrI)) {
811 report("Missing PHI operand", BBI);
812 *OS << "BB#" << (*PrI)->getNumber()
813 << " is a predecessor according to the CFG.\n";
819 void MachineVerifier::visitMachineFunctionAfter() {
822 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
824 BBInfo &MInfo = MBBInfoMap[MFI];
826 // Skip unreachable MBBs.
827 if (!MInfo.reachable)
832 // Verify dead-in virtual registers.
833 if (!allowVirtDoubleDefs) {
834 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
835 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
836 BBInfo &PrInfo = MBBInfoMap[*PrI];
837 if (!PrInfo.reachable)
840 for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
841 E = MInfo.vregsDeadIn.end(); I != E; ++I) {
842 // DeadIn register must be in neither regsLiveOut or vregsPassed of
844 if (PrInfo.isLiveOut(I->first)) {
845 report("Live-in virtual register redefined", I->second);
846 *OS << "Register %reg" << I->first
847 << " was live-out from predecessor MBB #"
848 << (*PrI)->getNumber() << ".\n";
855 // Now check LiveVariables info if available
858 verifyLiveVariables();
862 void MachineVerifier::verifyLiveVariables() {
863 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
864 for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister,
865 RegE = MRI->getLastVirtReg()-1; Reg != RegE; ++Reg) {
866 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
867 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
869 BBInfo &MInfo = MBBInfoMap[MFI];
871 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
872 if (MInfo.vregsRequired.count(Reg)) {
873 if (!VI.AliveBlocks.test(MFI->getNumber())) {
874 report("LiveVariables: Block missing from AliveBlocks", MFI);
875 *OS << "Virtual register %reg" << Reg
876 << " must be live through the block.\n";
879 if (VI.AliveBlocks.test(MFI->getNumber())) {
880 report("LiveVariables: Block should not be in AliveBlocks", MFI);
881 *OS << "Virtual register %reg" << Reg
882 << " is not needed live through the block.\n";