1 //===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/Function.h"
27 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
28 #include "llvm/CodeGen/LiveVariables.h"
29 #include "llvm/CodeGen/LiveStackAnalysis.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetRegisterInfo.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/ADT/DenseSet.h"
39 #include "llvm/ADT/SetOperations.h"
40 #include "llvm/ADT/SmallVector.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/raw_ostream.h"
47 struct MachineVerifier {
49 MachineVerifier(Pass *pass, const char *b) :
52 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
55 bool runOnMachineFunction(MachineFunction &MF);
59 const char *const OutFileName;
61 const MachineFunction *MF;
62 const TargetMachine *TM;
63 const TargetRegisterInfo *TRI;
64 const MachineRegisterInfo *MRI;
68 typedef SmallVector<unsigned, 16> RegVector;
69 typedef DenseSet<unsigned> RegSet;
70 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
72 BitVector regsReserved;
74 RegVector regsDefined, regsDead, regsKilled;
75 RegSet regsLiveInButUnused;
77 // Add Reg and any sub-registers to RV
78 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
80 if (TargetRegisterInfo::isPhysicalRegister(Reg))
81 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
86 // Is this MBB reachable from the MF entry point?
89 // Vregs that must be live in because they are used without being
90 // defined. Map value is the user.
93 // Regs killed in MBB. They may be defined again, and will then be in both
94 // regsKilled and regsLiveOut.
97 // Regs defined in MBB and live out. Note that vregs passing through may
98 // be live out without being mentioned here.
101 // Vregs that pass through MBB untouched. This set is disjoint from
102 // regsKilled and regsLiveOut.
105 // Vregs that must pass through MBB because they are needed by a successor
106 // block. This set is disjoint from regsLiveOut.
107 RegSet vregsRequired;
109 BBInfo() : reachable(false) {}
111 // Add register to vregsPassed if it belongs there. Return true if
113 bool addPassed(unsigned Reg) {
114 if (!TargetRegisterInfo::isVirtualRegister(Reg))
116 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
118 return vregsPassed.insert(Reg).second;
121 // Same for a full set.
122 bool addPassed(const RegSet &RS) {
123 bool changed = false;
124 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
130 // Add register to vregsRequired if it belongs there. Return true if
132 bool addRequired(unsigned Reg) {
133 if (!TargetRegisterInfo::isVirtualRegister(Reg))
135 if (regsLiveOut.count(Reg))
137 return vregsRequired.insert(Reg).second;
140 // Same for a full set.
141 bool addRequired(const RegSet &RS) {
142 bool changed = false;
143 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
149 // Same for a full map.
150 bool addRequired(const RegMap &RM) {
151 bool changed = false;
152 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
153 if (addRequired(I->first))
158 // Live-out registers are either in regsLiveOut or vregsPassed.
159 bool isLiveOut(unsigned Reg) const {
160 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
164 // Extra register info per MBB.
165 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
167 bool isReserved(unsigned Reg) {
168 return Reg < regsReserved.size() && regsReserved.test(Reg);
171 // Analysis information if available
172 LiveVariables *LiveVars;
173 LiveIntervals *LiveInts;
174 LiveStacks *LiveStks;
175 SlotIndexes *Indexes;
177 void visitMachineFunctionBefore();
178 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
179 void visitMachineInstrBefore(const MachineInstr *MI);
180 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
181 void visitMachineInstrAfter(const MachineInstr *MI);
182 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
183 void visitMachineFunctionAfter();
185 void report(const char *msg, const MachineFunction *MF);
186 void report(const char *msg, const MachineBasicBlock *MBB);
187 void report(const char *msg, const MachineInstr *MI);
188 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
190 void markReachable(const MachineBasicBlock *MBB);
191 void calcRegsPassed();
192 void checkPHIOps(const MachineBasicBlock *MBB);
194 void calcRegsRequired();
195 void verifyLiveVariables();
196 void verifyLiveIntervals();
199 struct MachineVerifierPass : public MachineFunctionPass {
200 static char ID; // Pass ID, replacement for typeid
201 const char *const Banner;
203 MachineVerifierPass(const char *b = 0)
204 : MachineFunctionPass(ID), Banner(b) {
205 initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
208 void getAnalysisUsage(AnalysisUsage &AU) const {
209 AU.setPreservesAll();
210 MachineFunctionPass::getAnalysisUsage(AU);
213 bool runOnMachineFunction(MachineFunction &MF) {
214 MF.verify(this, Banner);
221 char MachineVerifierPass::ID = 0;
222 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
223 "Verify generated machine code", false, false)
225 FunctionPass *llvm::createMachineVerifierPass(const char *Banner) {
226 return new MachineVerifierPass(Banner);
229 void MachineFunction::verify(Pass *p, const char *Banner) const {
230 MachineVerifier(p, Banner)
231 .runOnMachineFunction(const_cast<MachineFunction&>(*this));
234 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
235 raw_ostream *OutFile = 0;
237 std::string ErrorInfo;
238 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
239 raw_fd_ostream::F_Append);
240 if (!ErrorInfo.empty()) {
241 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
253 TM = &MF.getTarget();
254 TRI = TM->getRegisterInfo();
255 MRI = &MF.getRegInfo();
262 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
263 // We don't want to verify LiveVariables if LiveIntervals is available.
265 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
266 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
267 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
270 visitMachineFunctionBefore();
271 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
273 visitMachineBasicBlockBefore(MFI);
274 for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
275 MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
276 visitMachineInstrBefore(MBBI);
277 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
278 visitMachineOperand(&MBBI->getOperand(I), I);
279 visitMachineInstrAfter(MBBI);
281 visitMachineBasicBlockAfter(MFI);
283 visitMachineFunctionAfter();
287 else if (foundErrors)
288 report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
295 regsLiveInButUnused.clear();
298 return false; // no changes
301 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
304 if (!foundErrors++) {
306 *OS << "# " << Banner << '\n';
307 MF->print(*OS, Indexes);
309 *OS << "*** Bad machine code: " << msg << " ***\n"
310 << "- function: " << MF->getFunction()->getNameStr() << "\n";
313 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
315 report(msg, MBB->getParent());
316 *OS << "- basic block: " << MBB->getName()
318 << " (BB#" << MBB->getNumber() << ")";
320 *OS << " [" << Indexes->getMBBStartIdx(MBB)
321 << ';' << Indexes->getMBBEndIdx(MBB) << ')';
325 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
327 report(msg, MI->getParent());
328 *OS << "- instruction: ";
329 if (Indexes && Indexes->hasIndex(MI))
330 *OS << Indexes->getInstructionIndex(MI) << '\t';
334 void MachineVerifier::report(const char *msg,
335 const MachineOperand *MO, unsigned MONum) {
337 report(msg, MO->getParent());
338 *OS << "- operand " << MONum << ": ";
343 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
344 BBInfo &MInfo = MBBInfoMap[MBB];
345 if (!MInfo.reachable) {
346 MInfo.reachable = true;
347 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
348 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
353 void MachineVerifier::visitMachineFunctionBefore() {
354 regsReserved = TRI->getReservedRegs(*MF);
356 // A sub-register of a reserved register is also reserved
357 for (int Reg = regsReserved.find_first(); Reg>=0;
358 Reg = regsReserved.find_next(Reg)) {
359 for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
360 // FIXME: This should probably be:
361 // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
362 regsReserved.set(*Sub);
365 markReachable(&MF->front());
368 // Does iterator point to a and b as the first two elements?
369 static bool matchPair(MachineBasicBlock::const_succ_iterator i,
370 const MachineBasicBlock *a, const MachineBasicBlock *b) {
379 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
380 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
382 // Count the number of landing pad successors.
383 unsigned LandingPadSuccs = 0;
384 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
385 E = MBB->succ_end(); I != E; ++I)
386 LandingPadSuccs += (*I)->isLandingPad();
387 if (LandingPadSuccs > 1)
388 report("MBB has more than one landing pad successor", MBB);
390 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
391 MachineBasicBlock *TBB = 0, *FBB = 0;
392 SmallVector<MachineOperand, 4> Cond;
393 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
395 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
396 // check whether its answers match up with reality.
398 // Block falls through to its successor.
399 MachineFunction::const_iterator MBBI = MBB;
401 if (MBBI == MF->end()) {
402 // It's possible that the block legitimately ends with a noreturn
403 // call or an unreachable, in which case it won't actually fall
404 // out the bottom of the function.
405 } else if (MBB->succ_size() == LandingPadSuccs) {
406 // It's possible that the block legitimately ends with a noreturn
407 // call or an unreachable, in which case it won't actuall fall
409 } else if (MBB->succ_size() != 1+LandingPadSuccs) {
410 report("MBB exits via unconditional fall-through but doesn't have "
411 "exactly one CFG successor!", MBB);
412 } else if (!MBB->isSuccessor(MBBI)) {
413 report("MBB exits via unconditional fall-through but its successor "
414 "differs from its CFG successor!", MBB);
416 if (!MBB->empty() && MBB->back().getDesc().isBarrier() &&
417 !TII->isPredicated(&MBB->back())) {
418 report("MBB exits via unconditional fall-through but ends with a "
419 "barrier instruction!", MBB);
422 report("MBB exits via unconditional fall-through but has a condition!",
425 } else if (TBB && !FBB && Cond.empty()) {
426 // Block unconditionally branches somewhere.
427 if (MBB->succ_size() != 1+LandingPadSuccs) {
428 report("MBB exits via unconditional branch but doesn't have "
429 "exactly one CFG successor!", MBB);
430 } else if (!MBB->isSuccessor(TBB)) {
431 report("MBB exits via unconditional branch but the CFG "
432 "successor doesn't match the actual successor!", MBB);
435 report("MBB exits via unconditional branch but doesn't contain "
436 "any instructions!", MBB);
437 } else if (!MBB->back().getDesc().isBarrier()) {
438 report("MBB exits via unconditional branch but doesn't end with a "
439 "barrier instruction!", MBB);
440 } else if (!MBB->back().getDesc().isTerminator()) {
441 report("MBB exits via unconditional branch but the branch isn't a "
442 "terminator instruction!", MBB);
444 } else if (TBB && !FBB && !Cond.empty()) {
445 // Block conditionally branches somewhere, otherwise falls through.
446 MachineFunction::const_iterator MBBI = MBB;
448 if (MBBI == MF->end()) {
449 report("MBB conditionally falls through out of function!", MBB);
450 } if (MBB->succ_size() != 2) {
451 report("MBB exits via conditional branch/fall-through but doesn't have "
452 "exactly two CFG successors!", MBB);
453 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
454 report("MBB exits via conditional branch/fall-through but the CFG "
455 "successors don't match the actual successors!", MBB);
458 report("MBB exits via conditional branch/fall-through but doesn't "
459 "contain any instructions!", MBB);
460 } else if (MBB->back().getDesc().isBarrier()) {
461 report("MBB exits via conditional branch/fall-through but ends with a "
462 "barrier instruction!", MBB);
463 } else if (!MBB->back().getDesc().isTerminator()) {
464 report("MBB exits via conditional branch/fall-through but the branch "
465 "isn't a terminator instruction!", MBB);
467 } else if (TBB && FBB) {
468 // Block conditionally branches somewhere, otherwise branches
470 if (MBB->succ_size() != 2) {
471 report("MBB exits via conditional branch/branch but doesn't have "
472 "exactly two CFG successors!", MBB);
473 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
474 report("MBB exits via conditional branch/branch but the CFG "
475 "successors don't match the actual successors!", MBB);
478 report("MBB exits via conditional branch/branch but doesn't "
479 "contain any instructions!", MBB);
480 } else if (!MBB->back().getDesc().isBarrier()) {
481 report("MBB exits via conditional branch/branch but doesn't end with a "
482 "barrier instruction!", MBB);
483 } else if (!MBB->back().getDesc().isTerminator()) {
484 report("MBB exits via conditional branch/branch but the branch "
485 "isn't a terminator instruction!", MBB);
488 report("MBB exits via conditinal branch/branch but there's no "
492 report("AnalyzeBranch returned invalid data!", MBB);
497 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
498 E = MBB->livein_end(); I != E; ++I) {
499 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
500 report("MBB live-in list contains non-physical register", MBB);
504 for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
507 regsLiveInButUnused = regsLive;
509 const MachineFrameInfo *MFI = MF->getFrameInfo();
510 assert(MFI && "Function has no frame info");
511 BitVector PR = MFI->getPristineRegs(MBB);
512 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
514 for (const unsigned *R = TRI->getSubRegisters(I); *R; R++)
522 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
523 const TargetInstrDesc &TI = MI->getDesc();
524 if (MI->getNumOperands() < TI.getNumOperands()) {
525 report("Too few operands", MI);
526 *OS << TI.getNumOperands() << " operands expected, but "
527 << MI->getNumExplicitOperands() << " given.\n";
530 // Check the MachineMemOperands for basic consistency.
531 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
532 E = MI->memoperands_end(); I != E; ++I) {
533 if ((*I)->isLoad() && !TI.mayLoad())
534 report("Missing mayLoad flag", MI);
535 if ((*I)->isStore() && !TI.mayStore())
536 report("Missing mayStore flag", MI);
539 // Debug values must not have a slot index.
540 // Other instructions must have one.
542 bool mapped = !LiveInts->isNotInMIMap(MI);
543 if (MI->isDebugValue()) {
545 report("Debug instruction has a slot index", MI);
548 report("Missing slot index", MI);
555 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
556 const MachineInstr *MI = MO->getParent();
557 const TargetInstrDesc &TI = MI->getDesc();
558 const TargetOperandInfo &TOI = TI.OpInfo[MONum];
560 // The first TI.NumDefs operands must be explicit register defines
561 if (MONum < TI.getNumDefs()) {
563 report("Explicit definition must be a register", MO, MONum);
564 else if (!MO->isDef())
565 report("Explicit definition marked as use", MO, MONum);
566 else if (MO->isImplicit())
567 report("Explicit definition marked as implicit", MO, MONum);
568 } else if (MONum < TI.getNumOperands()) {
569 // Don't check if it's the last operand in a variadic instruction. See,
570 // e.g., LDM_RET in the arm back end.
571 if (MO->isReg() && !(TI.isVariadic() && MONum == TI.getNumOperands()-1)) {
572 if (MO->isDef() && !TOI.isOptionalDef())
573 report("Explicit operand marked as def", MO, MONum);
574 if (MO->isImplicit())
575 report("Explicit operand marked as implicit", MO, MONum);
578 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
579 if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg())
580 report("Extra explicit operand on non-variadic instruction", MO, MONum);
583 switch (MO->getType()) {
584 case MachineOperand::MO_Register: {
585 const unsigned Reg = MO->getReg();
589 // Check Live Variables.
590 if (MI->isDebugValue()) {
591 // Liveness checks are not valid for debug values.
592 } else if (MO->isUndef()) {
593 // An <undef> doesn't refer to any register, so just skip it.
594 } else if (MO->isUse()) {
595 regsLiveInButUnused.erase(Reg);
599 if (MI->isRegTiedToDefOperand(MONum, &defIdx)) {
600 // A two-addr use counts as a kill if use and def are the same.
601 unsigned DefReg = MI->getOperand(defIdx).getReg();
604 // And in that case an explicit kill flag is not allowed.
606 report("Illegal kill flag on two-address instruction operand",
608 } else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
609 report("Two-address instruction operands must be identical",
613 isKill = MO->isKill();
616 addRegWithSubRegs(regsKilled, Reg);
618 // Check that LiveVars knows this kill.
619 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
621 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
622 if (std::find(VI.Kills.begin(),
623 VI.Kills.end(), MI) == VI.Kills.end())
624 report("Kill missing from LiveVariables", MO, MONum);
627 // Check LiveInts liveness and kill.
628 if (TargetRegisterInfo::isVirtualRegister(Reg) &&
629 LiveInts && !LiveInts->isNotInMIMap(MI)) {
630 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI).getUseIndex();
631 if (LiveInts->hasInterval(Reg)) {
632 const LiveInterval &LI = LiveInts->getInterval(Reg);
633 if (!LI.liveAt(UseIdx)) {
634 report("No live range at use", MO, MONum);
635 *OS << UseIdx << " is not live in " << LI << '\n';
637 // Verify isKill == LI.killedAt.
638 // Two-address instrs don't have kill flags on the tied operands, and
640 // %r1 = add %r1, %r1
641 // without a kill flag on the untied operand.
642 // MI->findRegisterUseOperandIdx finds the first operand using reg.
643 if (!MI->isRegTiedToDefOperand(MI->findRegisterUseOperandIdx(Reg))) {
644 // MI could kill register without a kill flag on MO.
645 bool miKill = MI->killsRegister(Reg);
646 bool liKill = LI.killedAt(UseIdx.getDefIndex());
647 if (miKill && !liKill) {
648 report("Live range continues after kill flag", MO, MONum);
649 *OS << "Live range: " << LI << '\n';
651 if (!miKill && liKill) {
652 report("Live range ends without kill flag", MO, MONum);
653 *OS << "Live range: " << LI << '\n';
657 report("Virtual register has no Live interval", MO, MONum);
661 // Use of a dead register.
662 if (!regsLive.count(Reg)) {
663 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
664 // Reserved registers may be used even when 'dead'.
665 if (!isReserved(Reg))
666 report("Using an undefined physical register", MO, MONum);
668 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
669 // We don't know which virtual registers are live in, so only complain
670 // if vreg was killed in this MBB. Otherwise keep track of vregs that
671 // must be live in. PHI instructions are handled separately.
672 if (MInfo.regsKilled.count(Reg))
673 report("Using a killed virtual register", MO, MONum);
674 else if (!MI->isPHI())
675 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
681 // TODO: verify that earlyclobber ops are not used.
683 addRegWithSubRegs(regsDead, Reg);
685 addRegWithSubRegs(regsDefined, Reg);
687 // Check LiveInts for a live range, but only for virtual registers.
688 if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
689 !LiveInts->isNotInMIMap(MI)) {
690 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI).getDefIndex();
691 if (LiveInts->hasInterval(Reg)) {
692 const LiveInterval &LI = LiveInts->getInterval(Reg);
693 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
694 assert(VNI && "NULL valno is not allowed");
695 if (VNI->def != DefIdx && !MO->isEarlyClobber()) {
696 report("Inconsistent valno->def", MO, MONum);
697 *OS << "Valno " << VNI->id << " is not defined at "
698 << DefIdx << " in " << LI << '\n';
701 report("No live range at def", MO, MONum);
702 *OS << DefIdx << " is not live in " << LI << '\n';
705 report("Virtual register has no Live interval", MO, MONum);
710 // Check register classes.
711 if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
712 unsigned SubIdx = MO->getSubReg();
714 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
717 unsigned s = TRI->getSubReg(Reg, SubIdx);
719 report("Invalid subregister index for physical register",
725 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
726 if (!DRC->contains(sr)) {
727 report("Illegal physical register for instruction", MO, MONum);
728 *OS << TRI->getName(sr) << " is not a "
729 << DRC->getName() << " register.\n";
734 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
736 const TargetRegisterClass *SRC = RC->getSubRegisterRegClass(SubIdx);
738 report("Invalid subregister index for virtual register", MO, MONum);
739 *OS << "Register class " << RC->getName()
740 << " does not support subreg index " << SubIdx << "\n";
745 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
746 if (RC != DRC && !RC->hasSuperClass(DRC)) {
747 report("Illegal virtual register for instruction", MO, MONum);
748 *OS << "Expected a " << DRC->getName() << " register, but got a "
749 << RC->getName() << " register\n";
757 case MachineOperand::MO_MachineBasicBlock:
758 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
759 report("PHI operand is not in the CFG", MO, MONum);
762 case MachineOperand::MO_FrameIndex:
763 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
764 LiveInts && !LiveInts->isNotInMIMap(MI)) {
765 LiveInterval &LI = LiveStks->getInterval(MO->getIndex());
766 SlotIndex Idx = LiveInts->getInstructionIndex(MI);
767 if (TI.mayLoad() && !LI.liveAt(Idx.getUseIndex())) {
768 report("Instruction loads from dead spill slot", MO, MONum);
769 *OS << "Live stack: " << LI << '\n';
771 if (TI.mayStore() && !LI.liveAt(Idx.getDefIndex())) {
772 report("Instruction stores to dead spill slot", MO, MONum);
773 *OS << "Live stack: " << LI << '\n';
783 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
784 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
785 set_union(MInfo.regsKilled, regsKilled);
786 set_subtract(regsLive, regsKilled); regsKilled.clear();
787 set_subtract(regsLive, regsDead); regsDead.clear();
788 set_union(regsLive, regsDefined); regsDefined.clear();
792 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
793 MBBInfoMap[MBB].regsLiveOut = regsLive;
797 // Calculate the largest possible vregsPassed sets. These are the registers that
798 // can pass through an MBB live, but may not be live every time. It is assumed
799 // that all vregsPassed sets are empty before the call.
800 void MachineVerifier::calcRegsPassed() {
801 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
802 // have any vregsPassed.
803 DenseSet<const MachineBasicBlock*> todo;
804 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
806 const MachineBasicBlock &MBB(*MFI);
807 BBInfo &MInfo = MBBInfoMap[&MBB];
808 if (!MInfo.reachable)
810 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
811 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
812 BBInfo &SInfo = MBBInfoMap[*SuI];
813 if (SInfo.addPassed(MInfo.regsLiveOut))
818 // Iteratively push vregsPassed to successors. This will converge to the same
819 // final state regardless of DenseSet iteration order.
820 while (!todo.empty()) {
821 const MachineBasicBlock *MBB = *todo.begin();
823 BBInfo &MInfo = MBBInfoMap[MBB];
824 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
825 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
828 BBInfo &SInfo = MBBInfoMap[*SuI];
829 if (SInfo.addPassed(MInfo.vregsPassed))
835 // Calculate the set of virtual registers that must be passed through each basic
836 // block in order to satisfy the requirements of successor blocks. This is very
837 // similar to calcRegsPassed, only backwards.
838 void MachineVerifier::calcRegsRequired() {
839 // First push live-in regs to predecessors' vregsRequired.
840 DenseSet<const MachineBasicBlock*> todo;
841 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
843 const MachineBasicBlock &MBB(*MFI);
844 BBInfo &MInfo = MBBInfoMap[&MBB];
845 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
846 PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
847 BBInfo &PInfo = MBBInfoMap[*PrI];
848 if (PInfo.addRequired(MInfo.vregsLiveIn))
853 // Iteratively push vregsRequired to predecessors. This will converge to the
854 // same final state regardless of DenseSet iteration order.
855 while (!todo.empty()) {
856 const MachineBasicBlock *MBB = *todo.begin();
858 BBInfo &MInfo = MBBInfoMap[MBB];
859 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
860 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
863 BBInfo &SInfo = MBBInfoMap[*PrI];
864 if (SInfo.addRequired(MInfo.vregsRequired))
870 // Check PHI instructions at the beginning of MBB. It is assumed that
871 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
872 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
873 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
874 BBI != BBE && BBI->isPHI(); ++BBI) {
875 DenseSet<const MachineBasicBlock*> seen;
877 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
878 unsigned Reg = BBI->getOperand(i).getReg();
879 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
880 if (!Pre->isSuccessor(MBB))
883 BBInfo &PrInfo = MBBInfoMap[Pre];
884 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
885 report("PHI operand is not live-out from predecessor",
886 &BBI->getOperand(i), i);
889 // Did we see all predecessors?
890 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
891 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
892 if (!seen.count(*PrI)) {
893 report("Missing PHI operand", BBI);
894 *OS << "BB#" << (*PrI)->getNumber()
895 << " is a predecessor according to the CFG.\n";
901 void MachineVerifier::visitMachineFunctionAfter() {
904 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
906 BBInfo &MInfo = MBBInfoMap[MFI];
908 // Skip unreachable MBBs.
909 if (!MInfo.reachable)
915 // Now check liveness info if available
916 if (LiveVars || LiveInts)
919 verifyLiveVariables();
921 verifyLiveIntervals();
924 void MachineVerifier::verifyLiveVariables() {
925 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
926 for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister,
927 RegE = MRI->getLastVirtReg()-1; Reg != RegE; ++Reg) {
928 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
929 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
931 BBInfo &MInfo = MBBInfoMap[MFI];
933 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
934 if (MInfo.vregsRequired.count(Reg)) {
935 if (!VI.AliveBlocks.test(MFI->getNumber())) {
936 report("LiveVariables: Block missing from AliveBlocks", MFI);
937 *OS << "Virtual register %reg" << Reg
938 << " must be live through the block.\n";
941 if (VI.AliveBlocks.test(MFI->getNumber())) {
942 report("LiveVariables: Block should not be in AliveBlocks", MFI);
943 *OS << "Virtual register %reg" << Reg
944 << " is not needed live through the block.\n";
951 void MachineVerifier::verifyLiveIntervals() {
952 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
953 for (LiveIntervals::const_iterator LVI = LiveInts->begin(),
954 LVE = LiveInts->end(); LVI != LVE; ++LVI) {
955 const LiveInterval &LI = *LVI->second;
957 // Spilling and splitting may leave unused registers around. Skip them.
958 if (MRI->use_empty(LI.reg))
961 // Physical registers have much weirdness going on, mostly from coalescing.
962 // We should probably fix it, but for now just ignore them.
963 if (TargetRegisterInfo::isPhysicalRegister(LI.reg))
966 assert(LVI->first == LI.reg && "Invalid reg to interval mapping");
968 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
971 const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def);
974 if (!VNI->isUnused()) {
975 report("Valno not live at def and not marked unused", MF);
976 *OS << "Valno #" << VNI->id << " in " << LI << '\n';
985 report("Live range at def has different valno", MF);
986 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
987 << " where valno #" << DefVNI->id << " is live in " << LI << '\n';
991 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
993 report("Invalid definition index", MF);
994 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
995 << " in " << LI << '\n';
999 if (VNI->isPHIDef()) {
1000 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
1001 report("PHIDef value is not defined at MBB start", MF);
1002 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1003 << ", not at the beginning of BB#" << MBB->getNumber()
1004 << " in " << LI << '\n';
1008 if (!VNI->def.isDef()) {
1009 report("Non-PHI def must be at a DEF slot", MF);
1010 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1011 << " in " << LI << '\n';
1013 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
1015 report("No instruction at def index", MF);
1016 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1017 << " in " << LI << '\n';
1018 } else if (!MI->modifiesRegister(LI.reg, TRI)) {
1019 report("Defining instruction does not modify register", MI);
1020 *OS << "Valno #" << VNI->id << " in " << LI << '\n';
1025 for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I) {
1026 const VNInfo *VNI = I->valno;
1027 assert(VNI && "Live range has no valno");
1029 if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) {
1030 report("Foreign valno in live range", MF);
1032 *OS << " has a valno not in " << LI << '\n';
1035 if (VNI->isUnused()) {
1036 report("Live range valno is marked unused", MF);
1038 *OS << " in " << LI << '\n';
1041 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(I->start);
1043 report("Bad start of live segment, no basic block", MF);
1045 *OS << " in " << LI << '\n';
1048 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
1049 if (I->start != MBBStartIdx && I->start != VNI->def) {
1050 report("Live segment must begin at MBB entry or valno def", MBB);
1052 *OS << " in " << LI << '\n' << "Basic block starts at "
1053 << MBBStartIdx << '\n';
1056 const MachineBasicBlock *EndMBB =
1057 LiveInts->getMBBFromIndex(I->end.getPrevSlot());
1059 report("Bad end of live segment, no basic block", MF);
1061 *OS << " in " << LI << '\n';
1064 if (I->end != LiveInts->getMBBEndIdx(EndMBB)) {
1065 // The live segment is ending inside EndMBB
1066 const MachineInstr *MI =
1067 LiveInts->getInstructionFromIndex(I->end.getPrevSlot());
1069 report("Live segment doesn't end at a valid instruction", EndMBB);
1071 *OS << " in " << LI << '\n' << "Basic block starts at "
1072 << MBBStartIdx << '\n';
1073 } else if (TargetRegisterInfo::isVirtualRegister(LI.reg) &&
1074 !MI->readsVirtualRegister(LI.reg)) {
1075 // A live range can end with either a redefinition, a kill flag on a
1076 // use, or a dead flag on a def.
1077 // FIXME: Should we check for each of these?
1078 bool hasDeadDef = false;
1079 for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
1080 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
1081 if (MOI->isReg() && MOI->getReg() == LI.reg && MOI->isDef() && MOI->isDead()) {
1088 report("Instruction killing live segment neither defines nor reads "
1091 *OS << " in " << LI << '\n';
1096 // Now check all the basic blocks in this live segment.
1097 MachineFunction::const_iterator MFI = MBB;
1098 // Is LI live-in to MBB and not a PHIDef?
1099 if (I->start == VNI->def) {
1100 // Not live-in to any blocks.
1107 assert(LiveInts->isLiveInToMBB(LI, MFI));
1108 // We don't know how to track physregs into a landing pad.
1109 if (TargetRegisterInfo::isPhysicalRegister(LI.reg) &&
1110 MFI->isLandingPad()) {
1111 if (&*MFI == EndMBB)
1116 // Check that VNI is live-out of all predecessors.
1117 for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
1118 PE = MFI->pred_end(); PI != PE; ++PI) {
1119 SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI).getPrevSlot();
1120 const VNInfo *PVNI = LI.getVNInfoAt(PEnd);
1122 report("Register not marked live out of predecessor", *PI);
1123 *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
1124 << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live at "
1125 << PEnd << " in " << LI << '\n';
1126 } else if (PVNI != VNI) {
1127 report("Different value live out of predecessor", *PI);
1128 *OS << "Valno #" << PVNI->id << " live out of BB#"
1129 << (*PI)->getNumber() << '@' << PEnd
1130 << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
1131 << '@' << LiveInts->getMBBStartIdx(MFI) << " in " << LI << '\n';
1134 if (&*MFI == EndMBB)
1140 // Check the LI only has one connected component.
1141 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1142 ConnectedVNInfoEqClasses ConEQ(*LiveInts);
1143 unsigned NumComp = ConEQ.Classify(&LI);
1145 report("Multiple connected components in live interval", MF);
1146 *OS << NumComp << " components in " << LI << '\n';
1147 for (unsigned comp = 0; comp != NumComp; ++comp) {
1148 *OS << comp << ": valnos";
1149 for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
1150 E = LI.vni_end(); I!=E; ++I)
1151 if (comp == ConEQ.getEqClass(*I))
1152 *OS << ' ' << (*I)->id;