1 //===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/ADT/DenseSet.h"
28 #include "llvm/ADT/SetOperations.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
31 #include "llvm/CodeGen/LiveStackAnalysis.h"
32 #include "llvm/CodeGen/LiveVariables.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstrBundle.h"
36 #include "llvm/CodeGen/MachineMemOperand.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/IR/BasicBlock.h"
39 #include "llvm/IR/InlineAsm.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/MC/MCAsmInfo.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/raw_ostream.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetRegisterInfo.h"
51 struct MachineVerifier {
53 MachineVerifier(Pass *pass, const char *b) :
56 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
59 bool runOnMachineFunction(MachineFunction &MF);
63 const char *const OutFileName;
65 const MachineFunction *MF;
66 const TargetMachine *TM;
67 const TargetInstrInfo *TII;
68 const TargetRegisterInfo *TRI;
69 const MachineRegisterInfo *MRI;
73 typedef SmallVector<unsigned, 16> RegVector;
74 typedef SmallVector<const uint32_t*, 4> RegMaskVector;
75 typedef DenseSet<unsigned> RegSet;
76 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
77 typedef SmallPtrSet<const MachineBasicBlock*, 8> BlockSet;
79 const MachineInstr *FirstTerminator;
80 BlockSet FunctionBlocks;
82 BitVector regsReserved;
84 RegVector regsDefined, regsDead, regsKilled;
85 RegMaskVector regMasks;
86 RegSet regsLiveInButUnused;
90 // Add Reg and any sub-registers to RV
91 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
93 if (TargetRegisterInfo::isPhysicalRegister(Reg))
94 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
95 RV.push_back(*SubRegs);
99 // Is this MBB reachable from the MF entry point?
102 // Vregs that must be live in because they are used without being
103 // defined. Map value is the user.
106 // Regs killed in MBB. They may be defined again, and will then be in both
107 // regsKilled and regsLiveOut.
110 // Regs defined in MBB and live out. Note that vregs passing through may
111 // be live out without being mentioned here.
114 // Vregs that pass through MBB untouched. This set is disjoint from
115 // regsKilled and regsLiveOut.
118 // Vregs that must pass through MBB because they are needed by a successor
119 // block. This set is disjoint from regsLiveOut.
120 RegSet vregsRequired;
122 // Set versions of block's predecessor and successor lists.
123 BlockSet Preds, Succs;
125 BBInfo() : reachable(false) {}
127 // Add register to vregsPassed if it belongs there. Return true if
129 bool addPassed(unsigned Reg) {
130 if (!TargetRegisterInfo::isVirtualRegister(Reg))
132 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
134 return vregsPassed.insert(Reg).second;
137 // Same for a full set.
138 bool addPassed(const RegSet &RS) {
139 bool changed = false;
140 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
146 // Add register to vregsRequired if it belongs there. Return true if
148 bool addRequired(unsigned Reg) {
149 if (!TargetRegisterInfo::isVirtualRegister(Reg))
151 if (regsLiveOut.count(Reg))
153 return vregsRequired.insert(Reg).second;
156 // Same for a full set.
157 bool addRequired(const RegSet &RS) {
158 bool changed = false;
159 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
165 // Same for a full map.
166 bool addRequired(const RegMap &RM) {
167 bool changed = false;
168 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
169 if (addRequired(I->first))
174 // Live-out registers are either in regsLiveOut or vregsPassed.
175 bool isLiveOut(unsigned Reg) const {
176 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
180 // Extra register info per MBB.
181 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
183 bool isReserved(unsigned Reg) {
184 return Reg < regsReserved.size() && regsReserved.test(Reg);
187 bool isAllocatable(unsigned Reg) {
188 return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg);
191 // Analysis information if available
192 LiveVariables *LiveVars;
193 LiveIntervals *LiveInts;
194 LiveStacks *LiveStks;
195 SlotIndexes *Indexes;
197 void visitMachineFunctionBefore();
198 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
199 void visitMachineBundleBefore(const MachineInstr *MI);
200 void visitMachineInstrBefore(const MachineInstr *MI);
201 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
202 void visitMachineInstrAfter(const MachineInstr *MI);
203 void visitMachineBundleAfter(const MachineInstr *MI);
204 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
205 void visitMachineFunctionAfter();
207 void report(const char *msg, const MachineFunction *MF);
208 void report(const char *msg, const MachineBasicBlock *MBB);
209 void report(const char *msg, const MachineInstr *MI);
210 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
211 void report(const char *msg, const MachineFunction *MF,
212 const LiveInterval &LI);
213 void report(const char *msg, const MachineBasicBlock *MBB,
214 const LiveInterval &LI);
216 void verifyInlineAsm(const MachineInstr *MI);
218 void checkLiveness(const MachineOperand *MO, unsigned MONum);
219 void markReachable(const MachineBasicBlock *MBB);
220 void calcRegsPassed();
221 void checkPHIOps(const MachineBasicBlock *MBB);
223 void calcRegsRequired();
224 void verifyLiveVariables();
225 void verifyLiveIntervals();
226 void verifyLiveInterval(const LiveInterval&);
227 void verifyLiveIntervalValue(const LiveInterval&, VNInfo*);
228 void verifyLiveIntervalSegment(const LiveInterval&,
229 LiveInterval::const_iterator);
232 struct MachineVerifierPass : public MachineFunctionPass {
233 static char ID; // Pass ID, replacement for typeid
234 const char *const Banner;
236 MachineVerifierPass(const char *b = 0)
237 : MachineFunctionPass(ID), Banner(b) {
238 initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
241 void getAnalysisUsage(AnalysisUsage &AU) const {
242 AU.setPreservesAll();
243 MachineFunctionPass::getAnalysisUsage(AU);
246 bool runOnMachineFunction(MachineFunction &MF) {
247 MF.verify(this, Banner);
254 char MachineVerifierPass::ID = 0;
255 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
256 "Verify generated machine code", false, false)
258 FunctionPass *llvm::createMachineVerifierPass(const char *Banner) {
259 return new MachineVerifierPass(Banner);
262 void MachineFunction::verify(Pass *p, const char *Banner) const {
263 MachineVerifier(p, Banner)
264 .runOnMachineFunction(const_cast<MachineFunction&>(*this));
267 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
268 raw_ostream *OutFile = 0;
270 std::string ErrorInfo;
271 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
272 raw_fd_ostream::F_Append);
273 if (!ErrorInfo.empty()) {
274 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
286 TM = &MF.getTarget();
287 TII = TM->getInstrInfo();
288 TRI = TM->getRegisterInfo();
289 MRI = &MF.getRegInfo();
296 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
297 // We don't want to verify LiveVariables if LiveIntervals is available.
299 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
300 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
301 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
304 visitMachineFunctionBefore();
305 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
307 visitMachineBasicBlockBefore(MFI);
308 // Keep track of the current bundle header.
309 const MachineInstr *CurBundle = 0;
310 // Do we expect the next instruction to be part of the same bundle?
311 bool InBundle = false;
313 for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
314 MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
315 if (MBBI->getParent() != MFI) {
316 report("Bad instruction parent pointer", MFI);
317 *OS << "Instruction: " << *MBBI;
321 // Check for consistent bundle flags.
322 if (InBundle && !MBBI->isBundledWithPred())
323 report("Missing BundledPred flag, "
324 "BundledSucc was set on predecessor", MBBI);
325 if (!InBundle && MBBI->isBundledWithPred())
326 report("BundledPred flag is set, "
327 "but BundledSucc not set on predecessor", MBBI);
329 // Is this a bundle header?
330 if (!MBBI->isInsideBundle()) {
332 visitMachineBundleAfter(CurBundle);
334 visitMachineBundleBefore(CurBundle);
335 } else if (!CurBundle)
336 report("No bundle header", MBBI);
337 visitMachineInstrBefore(MBBI);
338 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
339 visitMachineOperand(&MBBI->getOperand(I), I);
340 visitMachineInstrAfter(MBBI);
342 // Was this the last bundled instruction?
343 InBundle = MBBI->isBundledWithSucc();
346 visitMachineBundleAfter(CurBundle);
348 report("BundledSucc flag set on last instruction in block", &MFI->back());
349 visitMachineBasicBlockAfter(MFI);
351 visitMachineFunctionAfter();
355 else if (foundErrors)
356 report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
364 regsLiveInButUnused.clear();
367 return false; // no changes
370 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
373 if (!foundErrors++) {
375 *OS << "# " << Banner << '\n';
376 MF->print(*OS, Indexes);
378 *OS << "*** Bad machine code: " << msg << " ***\n"
379 << "- function: " << MF->getName() << "\n";
382 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
384 report(msg, MBB->getParent());
385 *OS << "- basic block: BB#" << MBB->getNumber()
386 << ' ' << MBB->getName()
387 << " (" << (const void*)MBB << ')';
389 *OS << " [" << Indexes->getMBBStartIdx(MBB)
390 << ';' << Indexes->getMBBEndIdx(MBB) << ')';
394 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
396 report(msg, MI->getParent());
397 *OS << "- instruction: ";
398 if (Indexes && Indexes->hasIndex(MI))
399 *OS << Indexes->getInstructionIndex(MI) << '\t';
403 void MachineVerifier::report(const char *msg,
404 const MachineOperand *MO, unsigned MONum) {
406 report(msg, MO->getParent());
407 *OS << "- operand " << MONum << ": ";
412 void MachineVerifier::report(const char *msg, const MachineFunction *MF,
413 const LiveInterval &LI) {
415 *OS << "- interval: ";
416 if (TargetRegisterInfo::isVirtualRegister(LI.reg))
417 *OS << PrintReg(LI.reg, TRI);
419 *OS << PrintRegUnit(LI.reg, TRI);
420 *OS << ' ' << LI << '\n';
423 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
424 const LiveInterval &LI) {
426 *OS << "- interval: ";
427 if (TargetRegisterInfo::isVirtualRegister(LI.reg))
428 *OS << PrintReg(LI.reg, TRI);
430 *OS << PrintRegUnit(LI.reg, TRI);
431 *OS << ' ' << LI << '\n';
434 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
435 BBInfo &MInfo = MBBInfoMap[MBB];
436 if (!MInfo.reachable) {
437 MInfo.reachable = true;
438 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
439 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
444 void MachineVerifier::visitMachineFunctionBefore() {
445 lastIndex = SlotIndex();
446 regsReserved = MRI->getReservedRegs();
448 // A sub-register of a reserved register is also reserved
449 for (int Reg = regsReserved.find_first(); Reg>=0;
450 Reg = regsReserved.find_next(Reg)) {
451 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
452 // FIXME: This should probably be:
453 // assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register");
454 regsReserved.set(*SubRegs);
458 markReachable(&MF->front());
460 // Build a set of the basic blocks in the function.
461 FunctionBlocks.clear();
462 for (MachineFunction::const_iterator
463 I = MF->begin(), E = MF->end(); I != E; ++I) {
464 FunctionBlocks.insert(I);
465 BBInfo &MInfo = MBBInfoMap[I];
467 MInfo.Preds.insert(I->pred_begin(), I->pred_end());
468 if (MInfo.Preds.size() != I->pred_size())
469 report("MBB has duplicate entries in its predecessor list.", I);
471 MInfo.Succs.insert(I->succ_begin(), I->succ_end());
472 if (MInfo.Succs.size() != I->succ_size())
473 report("MBB has duplicate entries in its successor list.", I);
477 // Does iterator point to a and b as the first two elements?
478 static bool matchPair(MachineBasicBlock::const_succ_iterator i,
479 const MachineBasicBlock *a, const MachineBasicBlock *b) {
488 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
492 // If this block has allocatable physical registers live-in, check that
493 // it is an entry block or landing pad.
494 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
495 LE = MBB->livein_end();
498 if (isAllocatable(reg) && !MBB->isLandingPad() &&
499 MBB != MBB->getParent()->begin()) {
500 report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
505 // Count the number of landing pad successors.
506 SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
507 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
508 E = MBB->succ_end(); I != E; ++I) {
509 if ((*I)->isLandingPad())
510 LandingPadSuccs.insert(*I);
511 if (!FunctionBlocks.count(*I))
512 report("MBB has successor that isn't part of the function.", MBB);
513 if (!MBBInfoMap[*I].Preds.count(MBB)) {
514 report("Inconsistent CFG", MBB);
515 *OS << "MBB is not in the predecessor list of the successor BB#"
516 << (*I)->getNumber() << ".\n";
520 // Check the predecessor list.
521 for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
522 E = MBB->pred_end(); I != E; ++I) {
523 if (!FunctionBlocks.count(*I))
524 report("MBB has predecessor that isn't part of the function.", MBB);
525 if (!MBBInfoMap[*I].Succs.count(MBB)) {
526 report("Inconsistent CFG", MBB);
527 *OS << "MBB is not in the successor list of the predecessor BB#"
528 << (*I)->getNumber() << ".\n";
532 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
533 const BasicBlock *BB = MBB->getBasicBlock();
534 if (LandingPadSuccs.size() > 1 &&
536 AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
537 BB && isa<SwitchInst>(BB->getTerminator())))
538 report("MBB has more than one landing pad successor", MBB);
540 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
541 MachineBasicBlock *TBB = 0, *FBB = 0;
542 SmallVector<MachineOperand, 4> Cond;
543 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
545 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
546 // check whether its answers match up with reality.
548 // Block falls through to its successor.
549 MachineFunction::const_iterator MBBI = MBB;
551 if (MBBI == MF->end()) {
552 // It's possible that the block legitimately ends with a noreturn
553 // call or an unreachable, in which case it won't actually fall
554 // out the bottom of the function.
555 } else if (MBB->succ_size() == LandingPadSuccs.size()) {
556 // It's possible that the block legitimately ends with a noreturn
557 // call or an unreachable, in which case it won't actuall fall
559 } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
560 report("MBB exits via unconditional fall-through but doesn't have "
561 "exactly one CFG successor!", MBB);
562 } else if (!MBB->isSuccessor(MBBI)) {
563 report("MBB exits via unconditional fall-through but its successor "
564 "differs from its CFG successor!", MBB);
566 if (!MBB->empty() && getBundleStart(&MBB->back())->isBarrier() &&
567 !TII->isPredicated(getBundleStart(&MBB->back()))) {
568 report("MBB exits via unconditional fall-through but ends with a "
569 "barrier instruction!", MBB);
572 report("MBB exits via unconditional fall-through but has a condition!",
575 } else if (TBB && !FBB && Cond.empty()) {
576 // Block unconditionally branches somewhere.
577 if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
578 report("MBB exits via unconditional branch but doesn't have "
579 "exactly one CFG successor!", MBB);
580 } else if (!MBB->isSuccessor(TBB)) {
581 report("MBB exits via unconditional branch but the CFG "
582 "successor doesn't match the actual successor!", MBB);
585 report("MBB exits via unconditional branch but doesn't contain "
586 "any instructions!", MBB);
587 } else if (!getBundleStart(&MBB->back())->isBarrier()) {
588 report("MBB exits via unconditional branch but doesn't end with a "
589 "barrier instruction!", MBB);
590 } else if (!getBundleStart(&MBB->back())->isTerminator()) {
591 report("MBB exits via unconditional branch but the branch isn't a "
592 "terminator instruction!", MBB);
594 } else if (TBB && !FBB && !Cond.empty()) {
595 // Block conditionally branches somewhere, otherwise falls through.
596 MachineFunction::const_iterator MBBI = MBB;
598 if (MBBI == MF->end()) {
599 report("MBB conditionally falls through out of function!", MBB);
600 } else if (MBB->succ_size() == 1) {
601 // A conditional branch with only one successor is weird, but allowed.
603 report("MBB exits via conditional branch/fall-through but only has "
604 "one CFG successor!", MBB);
605 else if (TBB != *MBB->succ_begin())
606 report("MBB exits via conditional branch/fall-through but the CFG "
607 "successor don't match the actual successor!", MBB);
608 } else if (MBB->succ_size() != 2) {
609 report("MBB exits via conditional branch/fall-through but doesn't have "
610 "exactly two CFG successors!", MBB);
611 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
612 report("MBB exits via conditional branch/fall-through but the CFG "
613 "successors don't match the actual successors!", MBB);
616 report("MBB exits via conditional branch/fall-through but doesn't "
617 "contain any instructions!", MBB);
618 } else if (getBundleStart(&MBB->back())->isBarrier()) {
619 report("MBB exits via conditional branch/fall-through but ends with a "
620 "barrier instruction!", MBB);
621 } else if (!getBundleStart(&MBB->back())->isTerminator()) {
622 report("MBB exits via conditional branch/fall-through but the branch "
623 "isn't a terminator instruction!", MBB);
625 } else if (TBB && FBB) {
626 // Block conditionally branches somewhere, otherwise branches
628 if (MBB->succ_size() == 1) {
629 // A conditional branch with only one successor is weird, but allowed.
631 report("MBB exits via conditional branch/branch through but only has "
632 "one CFG successor!", MBB);
633 else if (TBB != *MBB->succ_begin())
634 report("MBB exits via conditional branch/branch through but the CFG "
635 "successor don't match the actual successor!", MBB);
636 } else if (MBB->succ_size() != 2) {
637 report("MBB exits via conditional branch/branch but doesn't have "
638 "exactly two CFG successors!", MBB);
639 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
640 report("MBB exits via conditional branch/branch but the CFG "
641 "successors don't match the actual successors!", MBB);
644 report("MBB exits via conditional branch/branch but doesn't "
645 "contain any instructions!", MBB);
646 } else if (!getBundleStart(&MBB->back())->isBarrier()) {
647 report("MBB exits via conditional branch/branch but doesn't end with a "
648 "barrier instruction!", MBB);
649 } else if (!getBundleStart(&MBB->back())->isTerminator()) {
650 report("MBB exits via conditional branch/branch but the branch "
651 "isn't a terminator instruction!", MBB);
654 report("MBB exits via conditinal branch/branch but there's no "
658 report("AnalyzeBranch returned invalid data!", MBB);
663 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
664 E = MBB->livein_end(); I != E; ++I) {
665 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
666 report("MBB live-in list contains non-physical register", MBB);
670 for (MCSubRegIterator SubRegs(*I, TRI); SubRegs.isValid(); ++SubRegs)
671 regsLive.insert(*SubRegs);
673 regsLiveInButUnused = regsLive;
675 const MachineFrameInfo *MFI = MF->getFrameInfo();
676 assert(MFI && "Function has no frame info");
677 BitVector PR = MFI->getPristineRegs(MBB);
678 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
680 for (MCSubRegIterator SubRegs(I, TRI); SubRegs.isValid(); ++SubRegs)
681 regsLive.insert(*SubRegs);
688 lastIndex = Indexes->getMBBStartIdx(MBB);
691 // This function gets called for all bundle headers, including normal
692 // stand-alone unbundled instructions.
693 void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
694 if (Indexes && Indexes->hasIndex(MI)) {
695 SlotIndex idx = Indexes->getInstructionIndex(MI);
696 if (!(idx > lastIndex)) {
697 report("Instruction index out of order", MI);
698 *OS << "Last instruction was at " << lastIndex << '\n';
703 // Ensure non-terminators don't follow terminators.
704 // Ignore predicated terminators formed by if conversion.
705 // FIXME: If conversion shouldn't need to violate this rule.
706 if (MI->isTerminator() && !TII->isPredicated(MI)) {
707 if (!FirstTerminator)
708 FirstTerminator = MI;
709 } else if (FirstTerminator) {
710 report("Non-terminator instruction after the first terminator", MI);
711 *OS << "First terminator was:\t" << *FirstTerminator;
715 // The operands on an INLINEASM instruction must follow a template.
716 // Verify that the flag operands make sense.
717 void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
718 // The first two operands on INLINEASM are the asm string and global flags.
719 if (MI->getNumOperands() < 2) {
720 report("Too few operands on inline asm", MI);
723 if (!MI->getOperand(0).isSymbol())
724 report("Asm string must be an external symbol", MI);
725 if (!MI->getOperand(1).isImm())
726 report("Asm flags must be an immediate", MI);
727 // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
728 // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16.
729 if (!isUInt<5>(MI->getOperand(1).getImm()))
730 report("Unknown asm flags", &MI->getOperand(1), 1);
732 assert(InlineAsm::MIOp_FirstOperand == 2 && "Asm format changed");
734 unsigned OpNo = InlineAsm::MIOp_FirstOperand;
736 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
737 const MachineOperand &MO = MI->getOperand(OpNo);
738 // There may be implicit ops after the fixed operands.
741 NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
744 if (OpNo > MI->getNumOperands())
745 report("Missing operands in last group", MI);
747 // An optional MDNode follows the groups.
748 if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
751 // All trailing operands must be implicit registers.
752 for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
753 const MachineOperand &MO = MI->getOperand(OpNo);
754 if (!MO.isReg() || !MO.isImplicit())
755 report("Expected implicit register after groups", &MO, OpNo);
759 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
760 const MCInstrDesc &MCID = MI->getDesc();
761 if (MI->getNumOperands() < MCID.getNumOperands()) {
762 report("Too few operands", MI);
763 *OS << MCID.getNumOperands() << " operands expected, but "
764 << MI->getNumExplicitOperands() << " given.\n";
767 // Check the tied operands.
768 if (MI->isInlineAsm())
771 // Check the MachineMemOperands for basic consistency.
772 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
773 E = MI->memoperands_end(); I != E; ++I) {
774 if ((*I)->isLoad() && !MI->mayLoad())
775 report("Missing mayLoad flag", MI);
776 if ((*I)->isStore() && !MI->mayStore())
777 report("Missing mayStore flag", MI);
780 // Debug values must not have a slot index.
781 // Other instructions must have one, unless they are inside a bundle.
783 bool mapped = !LiveInts->isNotInMIMap(MI);
784 if (MI->isDebugValue()) {
786 report("Debug instruction has a slot index", MI);
787 } else if (MI->isInsideBundle()) {
789 report("Instruction inside bundle has a slot index", MI);
792 report("Missing slot index", MI);
797 if (!TII->verifyInstruction(MI, ErrorInfo))
798 report(ErrorInfo.data(), MI);
802 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
803 const MachineInstr *MI = MO->getParent();
804 const MCInstrDesc &MCID = MI->getDesc();
806 // The first MCID.NumDefs operands must be explicit register defines
807 if (MONum < MCID.getNumDefs()) {
808 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
810 report("Explicit definition must be a register", MO, MONum);
811 else if (!MO->isDef() && !MCOI.isOptionalDef())
812 report("Explicit definition marked as use", MO, MONum);
813 else if (MO->isImplicit())
814 report("Explicit definition marked as implicit", MO, MONum);
815 } else if (MONum < MCID.getNumOperands()) {
816 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
817 // Don't check if it's the last operand in a variadic instruction. See,
818 // e.g., LDM_RET in the arm back end.
820 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
821 if (MO->isDef() && !MCOI.isOptionalDef())
822 report("Explicit operand marked as def", MO, MONum);
823 if (MO->isImplicit())
824 report("Explicit operand marked as implicit", MO, MONum);
827 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
830 report("Tied use must be a register", MO, MONum);
831 else if (!MO->isTied())
832 report("Operand should be tied", MO, MONum);
833 else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
834 report("Tied def doesn't match MCInstrDesc", MO, MONum);
835 } else if (MO->isReg() && MO->isTied())
836 report("Explicit operand should not be tied", MO, MONum);
838 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
839 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
840 report("Extra explicit operand on non-variadic instruction", MO, MONum);
843 switch (MO->getType()) {
844 case MachineOperand::MO_Register: {
845 const unsigned Reg = MO->getReg();
848 if (MRI->tracksLiveness() && !MI->isDebugValue())
849 checkLiveness(MO, MONum);
851 // Verify the consistency of tied operands.
853 unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
854 const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
855 if (!OtherMO.isReg())
856 report("Must be tied to a register", MO, MONum);
857 if (!OtherMO.isTied())
858 report("Missing tie flags on tied operand", MO, MONum);
859 if (MI->findTiedOperandIdx(OtherIdx) != MONum)
860 report("Inconsistent tie links", MO, MONum);
861 if (MONum < MCID.getNumDefs()) {
862 if (OtherIdx < MCID.getNumOperands()) {
863 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
864 report("Explicit def tied to explicit use without tie constraint",
867 if (!OtherMO.isImplicit())
868 report("Explicit def should be tied to implicit use", MO, MONum);
873 // Verify two-address constraints after leaving SSA form.
875 if (!MRI->isSSA() && MO->isUse() &&
876 MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
877 Reg != MI->getOperand(DefIdx).getReg())
878 report("Two-address instruction operands must be identical", MO, MONum);
880 // Check register classes.
881 if (MONum < MCID.getNumOperands() && !MO->isImplicit()) {
882 unsigned SubIdx = MO->getSubReg();
884 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
886 report("Illegal subregister index for physical register", MO, MONum);
889 if (const TargetRegisterClass *DRC =
890 TII->getRegClass(MCID, MONum, TRI, *MF)) {
891 if (!DRC->contains(Reg)) {
892 report("Illegal physical register for instruction", MO, MONum);
893 *OS << TRI->getName(Reg) << " is not a "
894 << DRC->getName() << " register.\n";
899 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
901 const TargetRegisterClass *SRC =
902 TRI->getSubClassWithSubReg(RC, SubIdx);
904 report("Invalid subregister index for virtual register", MO, MONum);
905 *OS << "Register class " << RC->getName()
906 << " does not support subreg index " << SubIdx << "\n";
910 report("Invalid register class for subregister index", MO, MONum);
911 *OS << "Register class " << RC->getName()
912 << " does not fully support subreg index " << SubIdx << "\n";
916 if (const TargetRegisterClass *DRC =
917 TII->getRegClass(MCID, MONum, TRI, *MF)) {
919 const TargetRegisterClass *SuperRC =
920 TRI->getLargestLegalSuperClass(RC);
922 report("No largest legal super class exists.", MO, MONum);
925 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
927 report("No matching super-reg register class.", MO, MONum);
931 if (!RC->hasSuperClassEq(DRC)) {
932 report("Illegal virtual register for instruction", MO, MONum);
933 *OS << "Expected a " << DRC->getName() << " register, but got a "
934 << RC->getName() << " register\n";
942 case MachineOperand::MO_RegisterMask:
943 regMasks.push_back(MO->getRegMask());
946 case MachineOperand::MO_MachineBasicBlock:
947 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
948 report("PHI operand is not in the CFG", MO, MONum);
951 case MachineOperand::MO_FrameIndex:
952 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
953 LiveInts && !LiveInts->isNotInMIMap(MI)) {
954 LiveInterval &LI = LiveStks->getInterval(MO->getIndex());
955 SlotIndex Idx = LiveInts->getInstructionIndex(MI);
956 if (MI->mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) {
957 report("Instruction loads from dead spill slot", MO, MONum);
958 *OS << "Live stack: " << LI << '\n';
960 if (MI->mayStore() && !LI.liveAt(Idx.getRegSlot())) {
961 report("Instruction stores to dead spill slot", MO, MONum);
962 *OS << "Live stack: " << LI << '\n';
972 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
973 const MachineInstr *MI = MO->getParent();
974 const unsigned Reg = MO->getReg();
976 // Both use and def operands can read a register.
977 if (MO->readsReg()) {
978 regsLiveInButUnused.erase(Reg);
981 addRegWithSubRegs(regsKilled, Reg);
983 // Check that LiveVars knows this kill.
984 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
986 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
987 if (std::find(VI.Kills.begin(), VI.Kills.end(), MI) == VI.Kills.end())
988 report("Kill missing from LiveVariables", MO, MONum);
991 // Check LiveInts liveness and kill.
992 if (LiveInts && !LiveInts->isNotInMIMap(MI)) {
993 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI);
994 // Check the cached regunit intervals.
995 if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) {
996 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
997 if (const LiveInterval *LI = LiveInts->getCachedRegUnit(*Units)) {
998 LiveRangeQuery LRQ(*LI, UseIdx);
999 if (!LRQ.valueIn()) {
1000 report("No live range at use", MO, MONum);
1001 *OS << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
1002 << ' ' << *LI << '\n';
1004 if (MO->isKill() && !LRQ.isKill()) {
1005 report("Live range continues after kill flag", MO, MONum);
1006 *OS << PrintRegUnit(*Units, TRI) << ' ' << *LI << '\n';
1012 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1013 if (LiveInts->hasInterval(Reg)) {
1014 // This is a virtual register interval.
1015 const LiveInterval &LI = LiveInts->getInterval(Reg);
1016 LiveRangeQuery LRQ(LI, UseIdx);
1017 if (!LRQ.valueIn()) {
1018 report("No live range at use", MO, MONum);
1019 *OS << UseIdx << " is not live in " << LI << '\n';
1021 // Check for extra kill flags.
1022 // Note that we allow missing kill flags for now.
1023 if (MO->isKill() && !LRQ.isKill()) {
1024 report("Live range continues after kill flag", MO, MONum);
1025 *OS << "Live range: " << LI << '\n';
1028 report("Virtual register has no live interval", MO, MONum);
1033 // Use of a dead register.
1034 if (!regsLive.count(Reg)) {
1035 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1036 // Reserved registers may be used even when 'dead'.
1037 if (!isReserved(Reg))
1038 report("Using an undefined physical register", MO, MONum);
1039 } else if (MRI->def_empty(Reg)) {
1040 report("Reading virtual register without a def", MO, MONum);
1042 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1043 // We don't know which virtual registers are live in, so only complain
1044 // if vreg was killed in this MBB. Otherwise keep track of vregs that
1045 // must be live in. PHI instructions are handled separately.
1046 if (MInfo.regsKilled.count(Reg))
1047 report("Using a killed virtual register", MO, MONum);
1048 else if (!MI->isPHI())
1049 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
1055 // Register defined.
1056 // TODO: verify that earlyclobber ops are not used.
1058 addRegWithSubRegs(regsDead, Reg);
1060 addRegWithSubRegs(regsDefined, Reg);
1063 if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
1064 llvm::next(MRI->def_begin(Reg)) != MRI->def_end())
1065 report("Multiple virtual register defs in SSA form", MO, MONum);
1067 // Check LiveInts for a live range, but only for virtual registers.
1068 if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
1069 !LiveInts->isNotInMIMap(MI)) {
1070 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI);
1071 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
1072 if (LiveInts->hasInterval(Reg)) {
1073 const LiveInterval &LI = LiveInts->getInterval(Reg);
1074 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
1075 assert(VNI && "NULL valno is not allowed");
1076 if (VNI->def != DefIdx) {
1077 report("Inconsistent valno->def", MO, MONum);
1078 *OS << "Valno " << VNI->id << " is not defined at "
1079 << DefIdx << " in " << LI << '\n';
1082 report("No live range at def", MO, MONum);
1083 *OS << DefIdx << " is not live in " << LI << '\n';
1086 report("Virtual register has no Live interval", MO, MONum);
1092 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
1095 // This function gets called after visiting all instructions in a bundle. The
1096 // argument points to the bundle header.
1097 // Normal stand-alone instructions are also considered 'bundles', and this
1098 // function is called for all of them.
1099 void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
1100 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1101 set_union(MInfo.regsKilled, regsKilled);
1102 set_subtract(regsLive, regsKilled); regsKilled.clear();
1103 // Kill any masked registers.
1104 while (!regMasks.empty()) {
1105 const uint32_t *Mask = regMasks.pop_back_val();
1106 for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
1107 if (TargetRegisterInfo::isPhysicalRegister(*I) &&
1108 MachineOperand::clobbersPhysReg(Mask, *I))
1109 regsDead.push_back(*I);
1111 set_subtract(regsLive, regsDead); regsDead.clear();
1112 set_union(regsLive, regsDefined); regsDefined.clear();
1116 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
1117 MBBInfoMap[MBB].regsLiveOut = regsLive;
1121 SlotIndex stop = Indexes->getMBBEndIdx(MBB);
1122 if (!(stop > lastIndex)) {
1123 report("Block ends before last instruction index", MBB);
1124 *OS << "Block ends at " << stop
1125 << " last instruction was at " << lastIndex << '\n';
1131 // Calculate the largest possible vregsPassed sets. These are the registers that
1132 // can pass through an MBB live, but may not be live every time. It is assumed
1133 // that all vregsPassed sets are empty before the call.
1134 void MachineVerifier::calcRegsPassed() {
1135 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
1136 // have any vregsPassed.
1137 SmallPtrSet<const MachineBasicBlock*, 8> todo;
1138 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1139 MFI != MFE; ++MFI) {
1140 const MachineBasicBlock &MBB(*MFI);
1141 BBInfo &MInfo = MBBInfoMap[&MBB];
1142 if (!MInfo.reachable)
1144 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
1145 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
1146 BBInfo &SInfo = MBBInfoMap[*SuI];
1147 if (SInfo.addPassed(MInfo.regsLiveOut))
1152 // Iteratively push vregsPassed to successors. This will converge to the same
1153 // final state regardless of DenseSet iteration order.
1154 while (!todo.empty()) {
1155 const MachineBasicBlock *MBB = *todo.begin();
1157 BBInfo &MInfo = MBBInfoMap[MBB];
1158 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
1159 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
1162 BBInfo &SInfo = MBBInfoMap[*SuI];
1163 if (SInfo.addPassed(MInfo.vregsPassed))
1169 // Calculate the set of virtual registers that must be passed through each basic
1170 // block in order to satisfy the requirements of successor blocks. This is very
1171 // similar to calcRegsPassed, only backwards.
1172 void MachineVerifier::calcRegsRequired() {
1173 // First push live-in regs to predecessors' vregsRequired.
1174 SmallPtrSet<const MachineBasicBlock*, 8> todo;
1175 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1176 MFI != MFE; ++MFI) {
1177 const MachineBasicBlock &MBB(*MFI);
1178 BBInfo &MInfo = MBBInfoMap[&MBB];
1179 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
1180 PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
1181 BBInfo &PInfo = MBBInfoMap[*PrI];
1182 if (PInfo.addRequired(MInfo.vregsLiveIn))
1187 // Iteratively push vregsRequired to predecessors. This will converge to the
1188 // same final state regardless of DenseSet iteration order.
1189 while (!todo.empty()) {
1190 const MachineBasicBlock *MBB = *todo.begin();
1192 BBInfo &MInfo = MBBInfoMap[MBB];
1193 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1194 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1197 BBInfo &SInfo = MBBInfoMap[*PrI];
1198 if (SInfo.addRequired(MInfo.vregsRequired))
1204 // Check PHI instructions at the beginning of MBB. It is assumed that
1205 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
1206 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
1207 SmallPtrSet<const MachineBasicBlock*, 8> seen;
1208 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
1209 BBI != BBE && BBI->isPHI(); ++BBI) {
1212 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
1213 unsigned Reg = BBI->getOperand(i).getReg();
1214 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
1215 if (!Pre->isSuccessor(MBB))
1218 BBInfo &PrInfo = MBBInfoMap[Pre];
1219 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
1220 report("PHI operand is not live-out from predecessor",
1221 &BBI->getOperand(i), i);
1224 // Did we see all predecessors?
1225 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1226 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1227 if (!seen.count(*PrI)) {
1228 report("Missing PHI operand", BBI);
1229 *OS << "BB#" << (*PrI)->getNumber()
1230 << " is a predecessor according to the CFG.\n";
1236 void MachineVerifier::visitMachineFunctionAfter() {
1239 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1240 MFI != MFE; ++MFI) {
1241 BBInfo &MInfo = MBBInfoMap[MFI];
1243 // Skip unreachable MBBs.
1244 if (!MInfo.reachable)
1250 // Now check liveness info if available
1253 // Check for killed virtual registers that should be live out.
1254 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1255 MFI != MFE; ++MFI) {
1256 BBInfo &MInfo = MBBInfoMap[MFI];
1257 for (RegSet::iterator
1258 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1260 if (MInfo.regsKilled.count(*I)) {
1261 report("Virtual register killed in block, but needed live out.", MFI);
1262 *OS << "Virtual register " << PrintReg(*I)
1263 << " is used after the block.\n";
1268 BBInfo &MInfo = MBBInfoMap[&MF->front()];
1269 for (RegSet::iterator
1270 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1272 report("Virtual register def doesn't dominate all uses.",
1273 MRI->getVRegDef(*I));
1277 verifyLiveVariables();
1279 verifyLiveIntervals();
1282 void MachineVerifier::verifyLiveVariables() {
1283 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
1284 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1285 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1286 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1287 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1288 MFI != MFE; ++MFI) {
1289 BBInfo &MInfo = MBBInfoMap[MFI];
1291 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
1292 if (MInfo.vregsRequired.count(Reg)) {
1293 if (!VI.AliveBlocks.test(MFI->getNumber())) {
1294 report("LiveVariables: Block missing from AliveBlocks", MFI);
1295 *OS << "Virtual register " << PrintReg(Reg)
1296 << " must be live through the block.\n";
1299 if (VI.AliveBlocks.test(MFI->getNumber())) {
1300 report("LiveVariables: Block should not be in AliveBlocks", MFI);
1301 *OS << "Virtual register " << PrintReg(Reg)
1302 << " is not needed live through the block.\n";
1309 void MachineVerifier::verifyLiveIntervals() {
1310 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
1311 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1312 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1314 // Spilling and splitting may leave unused registers around. Skip them.
1315 if (MRI->reg_nodbg_empty(Reg))
1318 if (!LiveInts->hasInterval(Reg)) {
1319 report("Missing live interval for virtual register", MF);
1320 *OS << PrintReg(Reg, TRI) << " still has defs or uses\n";
1324 const LiveInterval &LI = LiveInts->getInterval(Reg);
1325 assert(Reg == LI.reg && "Invalid reg to interval mapping");
1326 verifyLiveInterval(LI);
1329 // Verify all the cached regunit intervals.
1330 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
1331 if (const LiveInterval *LI = LiveInts->getCachedRegUnit(i))
1332 verifyLiveInterval(*LI);
1335 void MachineVerifier::verifyLiveIntervalValue(const LiveInterval &LI,
1337 if (VNI->isUnused())
1340 const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def);
1343 report("Valno not live at def and not marked unused", MF, LI);
1344 *OS << "Valno #" << VNI->id << '\n';
1348 if (DefVNI != VNI) {
1349 report("Live range at def has different valno", MF, LI);
1350 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1351 << " where valno #" << DefVNI->id << " is live\n";
1355 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
1357 report("Invalid definition index", MF, LI);
1358 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1359 << " in " << LI << '\n';
1363 if (VNI->isPHIDef()) {
1364 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
1365 report("PHIDef value is not defined at MBB start", MBB, LI);
1366 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1367 << ", not at the beginning of BB#" << MBB->getNumber() << '\n';
1373 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
1375 report("No instruction at def index", MBB, LI);
1376 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1380 bool hasDef = false;
1381 bool isEarlyClobber = false;
1382 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1383 if (!MOI->isReg() || !MOI->isDef())
1385 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1386 if (MOI->getReg() != LI.reg)
1389 if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
1390 !TRI->hasRegUnit(MOI->getReg(), LI.reg))
1394 if (MOI->isEarlyClobber())
1395 isEarlyClobber = true;
1399 report("Defining instruction does not modify register", MI);
1400 *OS << "Valno #" << VNI->id << " in " << LI << '\n';
1403 // Early clobber defs begin at USE slots, but other defs must begin at
1405 if (isEarlyClobber) {
1406 if (!VNI->def.isEarlyClobber()) {
1407 report("Early clobber def must be at an early-clobber slot", MBB, LI);
1408 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1410 } else if (!VNI->def.isRegister()) {
1411 report("Non-PHI, non-early clobber def must be at a register slot",
1413 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1418 MachineVerifier::verifyLiveIntervalSegment(const LiveInterval &LI,
1419 LiveInterval::const_iterator I) {
1420 const VNInfo *VNI = I->valno;
1421 assert(VNI && "Live range has no valno");
1423 if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) {
1424 report("Foreign valno in live range", MF, LI);
1425 *OS << *I << " has a bad valno\n";
1428 if (VNI->isUnused()) {
1429 report("Live range valno is marked unused", MF, LI);
1433 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(I->start);
1435 report("Bad start of live segment, no basic block", MF, LI);
1439 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
1440 if (I->start != MBBStartIdx && I->start != VNI->def) {
1441 report("Live segment must begin at MBB entry or valno def", MBB, LI);
1445 const MachineBasicBlock *EndMBB =
1446 LiveInts->getMBBFromIndex(I->end.getPrevSlot());
1448 report("Bad end of live segment, no basic block", MF, LI);
1453 // No more checks for live-out segments.
1454 if (I->end == LiveInts->getMBBEndIdx(EndMBB))
1457 // RegUnit intervals are allowed dead phis.
1458 if (!TargetRegisterInfo::isVirtualRegister(LI.reg) && VNI->isPHIDef() &&
1459 I->start == VNI->def && I->end == VNI->def.getDeadSlot())
1462 // The live segment is ending inside EndMBB
1463 const MachineInstr *MI =
1464 LiveInts->getInstructionFromIndex(I->end.getPrevSlot());
1466 report("Live segment doesn't end at a valid instruction", EndMBB, LI);
1471 // The block slot must refer to a basic block boundary.
1472 if (I->end.isBlock()) {
1473 report("Live segment ends at B slot of an instruction", EndMBB, LI);
1477 if (I->end.isDead()) {
1478 // Segment ends on the dead slot.
1479 // That means there must be a dead def.
1480 if (!SlotIndex::isSameInstr(I->start, I->end)) {
1481 report("Live segment ending at dead slot spans instructions", EndMBB, LI);
1486 // A live segment can only end at an early-clobber slot if it is being
1487 // redefined by an early-clobber def.
1488 if (I->end.isEarlyClobber()) {
1489 if (I+1 == LI.end() || (I+1)->start != I->end) {
1490 report("Live segment ending at early clobber slot must be "
1491 "redefined by an EC def in the same instruction", EndMBB, LI);
1496 // The following checks only apply to virtual registers. Physreg liveness
1497 // is too weird to check.
1498 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1499 // A live range can end with either a redefinition, a kill flag on a
1500 // use, or a dead flag on a def.
1501 bool hasRead = false;
1502 bool hasDeadDef = false;
1503 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1504 if (!MOI->isReg() || MOI->getReg() != LI.reg)
1506 if (MOI->readsReg())
1508 if (MOI->isDef() && MOI->isDead())
1512 if (I->end.isDead()) {
1514 report("Instruction doesn't have a dead def operand", MI);
1516 *OS << " in " << LI << '\n';
1520 report("Instruction ending live range doesn't read the register", MI);
1521 *OS << *I << " in " << LI << '\n';
1526 // Now check all the basic blocks in this live segment.
1527 MachineFunction::const_iterator MFI = MBB;
1528 // Is this live range the beginning of a non-PHIDef VN?
1529 if (I->start == VNI->def && !VNI->isPHIDef()) {
1530 // Not live-in to any blocks.
1537 assert(LiveInts->isLiveInToMBB(LI, MFI));
1538 // We don't know how to track physregs into a landing pad.
1539 if (!TargetRegisterInfo::isVirtualRegister(LI.reg) &&
1540 MFI->isLandingPad()) {
1541 if (&*MFI == EndMBB)
1547 // Is VNI a PHI-def in the current block?
1548 bool IsPHI = VNI->isPHIDef() &&
1549 VNI->def == LiveInts->getMBBStartIdx(MFI);
1551 // Check that VNI is live-out of all predecessors.
1552 for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
1553 PE = MFI->pred_end(); PI != PE; ++PI) {
1554 SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
1555 const VNInfo *PVNI = LI.getVNInfoBefore(PEnd);
1557 // All predecessors must have a live-out value.
1559 report("Register not marked live out of predecessor", *PI, LI);
1560 *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
1561 << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before "
1566 // Only PHI-defs can take different predecessor values.
1567 if (!IsPHI && PVNI != VNI) {
1568 report("Different value live out of predecessor", *PI, LI);
1569 *OS << "Valno #" << PVNI->id << " live out of BB#"
1570 << (*PI)->getNumber() << '@' << PEnd
1571 << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
1572 << '@' << LiveInts->getMBBStartIdx(MFI) << '\n';
1575 if (&*MFI == EndMBB)
1581 void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
1582 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
1584 verifyLiveIntervalValue(LI, *I);
1586 for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I)
1587 verifyLiveIntervalSegment(LI, I);
1589 // Check the LI only has one connected component.
1590 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1591 ConnectedVNInfoEqClasses ConEQ(*LiveInts);
1592 unsigned NumComp = ConEQ.Classify(&LI);
1594 report("Multiple connected components in live interval", MF, LI);
1595 for (unsigned comp = 0; comp != NumComp; ++comp) {
1596 *OS << comp << ": valnos";
1597 for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
1598 E = LI.vni_end(); I!=E; ++I)
1599 if (comp == ConEQ.getEqClass(*I))
1600 *OS << ' ' << (*I)->id;