1 //===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/Function.h"
27 #include "llvm/CodeGen/LiveVariables.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/ADT/DenseSet.h"
37 #include "llvm/ADT/SetOperations.h"
38 #include "llvm/ADT/SmallVector.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/raw_ostream.h"
45 struct MachineVerifier {
47 MachineVerifier(Pass *pass, bool allowDoubleDefs) :
49 allowVirtDoubleDefs(allowDoubleDefs),
50 allowPhysDoubleDefs(allowDoubleDefs),
51 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
54 bool runOnMachineFunction(MachineFunction &MF);
57 const bool allowVirtDoubleDefs;
58 const bool allowPhysDoubleDefs;
60 const char *const OutFileName;
62 const MachineFunction *MF;
63 const TargetMachine *TM;
64 const TargetRegisterInfo *TRI;
65 const MachineRegisterInfo *MRI;
69 typedef SmallVector<unsigned, 16> RegVector;
70 typedef DenseSet<unsigned> RegSet;
71 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
73 BitVector regsReserved;
75 RegVector regsDefined, regsDead, regsKilled;
76 RegSet regsLiveInButUnused;
78 // Add Reg and any sub-registers to RV
79 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
81 if (TargetRegisterInfo::isPhysicalRegister(Reg))
82 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
87 // Is this MBB reachable from the MF entry point?
90 // Vregs that must be live in because they are used without being
91 // defined. Map value is the user.
94 // Vregs that must be dead in because they are defined without being
95 // killed first. Map value is the defining instruction.
98 // Regs killed in MBB. They may be defined again, and will then be in both
99 // regsKilled and regsLiveOut.
102 // Regs defined in MBB and live out. Note that vregs passing through may
103 // be live out without being mentioned here.
106 // Vregs that pass through MBB untouched. This set is disjoint from
107 // regsKilled and regsLiveOut.
110 // Vregs that must pass through MBB because they are needed by a successor
111 // block. This set is disjoint from regsLiveOut.
112 RegSet vregsRequired;
114 BBInfo() : reachable(false) {}
116 // Add register to vregsPassed if it belongs there. Return true if
118 bool addPassed(unsigned Reg) {
119 if (!TargetRegisterInfo::isVirtualRegister(Reg))
121 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
123 return vregsPassed.insert(Reg).second;
126 // Same for a full set.
127 bool addPassed(const RegSet &RS) {
128 bool changed = false;
129 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
135 // Add register to vregsRequired if it belongs there. Return true if
137 bool addRequired(unsigned Reg) {
138 if (!TargetRegisterInfo::isVirtualRegister(Reg))
140 if (regsLiveOut.count(Reg))
142 return vregsRequired.insert(Reg).second;
145 // Same for a full set.
146 bool addRequired(const RegSet &RS) {
147 bool changed = false;
148 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
154 // Same for a full map.
155 bool addRequired(const RegMap &RM) {
156 bool changed = false;
157 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
158 if (addRequired(I->first))
163 // Live-out registers are either in regsLiveOut or vregsPassed.
164 bool isLiveOut(unsigned Reg) const {
165 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
169 // Extra register info per MBB.
170 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
172 bool isReserved(unsigned Reg) {
173 return Reg < regsReserved.size() && regsReserved.test(Reg);
176 // Analysis information if available
177 LiveVariables *LiveVars;
179 void visitMachineFunctionBefore();
180 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
181 void visitMachineInstrBefore(const MachineInstr *MI);
182 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
183 void visitMachineInstrAfter(const MachineInstr *MI);
184 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
185 void visitMachineFunctionAfter();
187 void report(const char *msg, const MachineFunction *MF);
188 void report(const char *msg, const MachineBasicBlock *MBB);
189 void report(const char *msg, const MachineInstr *MI);
190 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
192 void markReachable(const MachineBasicBlock *MBB);
193 void calcRegsPassed();
194 void checkPHIOps(const MachineBasicBlock *MBB);
196 void calcRegsRequired();
197 void verifyLiveVariables();
200 struct MachineVerifierPass : public MachineFunctionPass {
201 static char ID; // Pass ID, replacement for typeid
202 bool AllowDoubleDefs;
204 explicit MachineVerifierPass(bool allowDoubleDefs = false)
205 : MachineFunctionPass(&ID),
206 AllowDoubleDefs(allowDoubleDefs) {}
208 void getAnalysisUsage(AnalysisUsage &AU) const {
209 AU.setPreservesAll();
210 MachineFunctionPass::getAnalysisUsage(AU);
213 bool runOnMachineFunction(MachineFunction &MF) {
214 MF.verify(this, AllowDoubleDefs);
221 char MachineVerifierPass::ID = 0;
222 static RegisterPass<MachineVerifierPass>
223 MachineVer("machineverifier", "Verify generated machine code");
224 static const PassInfo *const MachineVerifyID = &MachineVer;
226 FunctionPass *llvm::createMachineVerifierPass(bool allowPhysDoubleDefs) {
227 return new MachineVerifierPass(allowPhysDoubleDefs);
230 void MachineFunction::verify(Pass *p, bool allowDoubleDefs) const {
231 MachineVerifier(p, allowDoubleDefs)
232 .runOnMachineFunction(const_cast<MachineFunction&>(*this));
235 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
236 raw_ostream *OutFile = 0;
238 std::string ErrorInfo;
239 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
240 raw_fd_ostream::F_Append);
241 if (!ErrorInfo.empty()) {
242 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
254 TM = &MF.getTarget();
255 TRI = TM->getRegisterInfo();
256 MRI = &MF.getRegInfo();
259 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
264 visitMachineFunctionBefore();
265 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
267 visitMachineBasicBlockBefore(MFI);
268 for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
269 MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
270 visitMachineInstrBefore(MBBI);
271 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
272 visitMachineOperand(&MBBI->getOperand(I), I);
273 visitMachineInstrAfter(MBBI);
275 visitMachineBasicBlockAfter(MFI);
277 visitMachineFunctionAfter();
281 else if (foundErrors)
282 llvm_report_error("Found "+Twine(foundErrors)+" machine code errors.");
289 regsLiveInButUnused.clear();
292 return false; // no changes
295 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
300 *OS << "*** Bad machine code: " << msg << " ***\n"
301 << "- function: " << MF->getFunction()->getNameStr() << "\n";
304 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
306 report(msg, MBB->getParent());
307 *OS << "- basic block: " << MBB->getName()
309 << " (BB#" << MBB->getNumber() << ")\n";
312 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
314 report(msg, MI->getParent());
315 *OS << "- instruction: ";
319 void MachineVerifier::report(const char *msg,
320 const MachineOperand *MO, unsigned MONum) {
322 report(msg, MO->getParent());
323 *OS << "- operand " << MONum << ": ";
328 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
329 BBInfo &MInfo = MBBInfoMap[MBB];
330 if (!MInfo.reachable) {
331 MInfo.reachable = true;
332 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
333 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
338 void MachineVerifier::visitMachineFunctionBefore() {
339 regsReserved = TRI->getReservedRegs(*MF);
341 // A sub-register of a reserved register is also reserved
342 for (int Reg = regsReserved.find_first(); Reg>=0;
343 Reg = regsReserved.find_next(Reg)) {
344 for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
345 // FIXME: This should probably be:
346 // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
347 regsReserved.set(*Sub);
350 markReachable(&MF->front());
353 // Does iterator point to a and b as the first two elements?
354 bool matchPair(MachineBasicBlock::const_succ_iterator i,
355 const MachineBasicBlock *a, const MachineBasicBlock *b) {
364 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
365 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
367 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
368 MachineBasicBlock *TBB = 0, *FBB = 0;
369 SmallVector<MachineOperand, 4> Cond;
370 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
372 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
373 // check whether its answers match up with reality.
375 // Block falls through to its successor.
376 MachineFunction::const_iterator MBBI = MBB;
378 if (MBBI == MF->end()) {
379 // It's possible that the block legitimately ends with a noreturn
380 // call or an unreachable, in which case it won't actually fall
381 // out the bottom of the function.
382 } else if (MBB->succ_empty()) {
383 // It's possible that the block legitimately ends with a noreturn
384 // call or an unreachable, in which case it won't actuall fall
386 } else if (MBB->succ_size() != 1) {
387 report("MBB exits via unconditional fall-through but doesn't have "
388 "exactly one CFG successor!", MBB);
389 } else if (MBB->succ_begin()[0] != MBBI) {
390 report("MBB exits via unconditional fall-through but its successor "
391 "differs from its CFG successor!", MBB);
393 if (!MBB->empty() && MBB->back().getDesc().isBarrier()) {
394 report("MBB exits via unconditional fall-through but ends with a "
395 "barrier instruction!", MBB);
398 report("MBB exits via unconditional fall-through but has a condition!",
401 } else if (TBB && !FBB && Cond.empty()) {
402 // Block unconditionally branches somewhere.
403 if (MBB->succ_size() != 1) {
404 report("MBB exits via unconditional branch but doesn't have "
405 "exactly one CFG successor!", MBB);
406 } else if (MBB->succ_begin()[0] != TBB) {
407 report("MBB exits via unconditional branch but the CFG "
408 "successor doesn't match the actual successor!", MBB);
411 report("MBB exits via unconditional branch but doesn't contain "
412 "any instructions!", MBB);
413 } else if (!MBB->back().getDesc().isBarrier()) {
414 report("MBB exits via unconditional branch but doesn't end with a "
415 "barrier instruction!", MBB);
416 } else if (!MBB->back().getDesc().isTerminator()) {
417 report("MBB exits via unconditional branch but the branch isn't a "
418 "terminator instruction!", MBB);
420 } else if (TBB && !FBB && !Cond.empty()) {
421 // Block conditionally branches somewhere, otherwise falls through.
422 MachineFunction::const_iterator MBBI = MBB;
424 if (MBBI == MF->end()) {
425 report("MBB conditionally falls through out of function!", MBB);
426 } if (MBB->succ_size() != 2) {
427 report("MBB exits via conditional branch/fall-through but doesn't have "
428 "exactly two CFG successors!", MBB);
429 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
430 report("MBB exits via conditional branch/fall-through but the CFG "
431 "successors don't match the actual successors!", MBB);
434 report("MBB exits via conditional branch/fall-through but doesn't "
435 "contain any instructions!", MBB);
436 } else if (MBB->back().getDesc().isBarrier()) {
437 report("MBB exits via conditional branch/fall-through but ends with a "
438 "barrier instruction!", MBB);
439 } else if (!MBB->back().getDesc().isTerminator()) {
440 report("MBB exits via conditional branch/fall-through but the branch "
441 "isn't a terminator instruction!", MBB);
443 } else if (TBB && FBB) {
444 // Block conditionally branches somewhere, otherwise branches
446 if (MBB->succ_size() != 2) {
447 report("MBB exits via conditional branch/branch but doesn't have "
448 "exactly two CFG successors!", MBB);
449 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
450 report("MBB exits via conditional branch/branch but the CFG "
451 "successors don't match the actual successors!", MBB);
454 report("MBB exits via conditional branch/branch but doesn't "
455 "contain any instructions!", MBB);
456 } else if (!MBB->back().getDesc().isBarrier()) {
457 report("MBB exits via conditional branch/branch but doesn't end with a "
458 "barrier instruction!", MBB);
459 } else if (!MBB->back().getDesc().isTerminator()) {
460 report("MBB exits via conditional branch/branch but the branch "
461 "isn't a terminator instruction!", MBB);
464 report("MBB exits via conditinal branch/branch but there's no "
468 report("AnalyzeBranch returned invalid data!", MBB);
473 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
474 E = MBB->livein_end(); I != E; ++I) {
475 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
476 report("MBB live-in list contains non-physical register", MBB);
480 for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
483 regsLiveInButUnused = regsLive;
485 const MachineFrameInfo *MFI = MF->getFrameInfo();
486 assert(MFI && "Function has no frame info");
487 BitVector PR = MFI->getPristineRegs(MBB);
488 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
490 for (const unsigned *R = TRI->getSubRegisters(I); *R; R++)
498 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
499 const TargetInstrDesc &TI = MI->getDesc();
500 if (MI->getNumOperands() < TI.getNumOperands()) {
501 report("Too few operands", MI);
502 *OS << TI.getNumOperands() << " operands expected, but "
503 << MI->getNumExplicitOperands() << " given.\n";
506 // Check the MachineMemOperands for basic consistency.
507 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
508 E = MI->memoperands_end(); I != E; ++I) {
509 if ((*I)->isLoad() && !TI.mayLoad())
510 report("Missing mayLoad flag", MI);
511 if ((*I)->isStore() && !TI.mayStore())
512 report("Missing mayStore flag", MI);
517 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
518 const MachineInstr *MI = MO->getParent();
519 const TargetInstrDesc &TI = MI->getDesc();
521 // The first TI.NumDefs operands must be explicit register defines
522 if (MONum < TI.getNumDefs()) {
524 report("Explicit definition must be a register", MO, MONum);
525 else if (!MO->isDef())
526 report("Explicit definition marked as use", MO, MONum);
527 else if (MO->isImplicit())
528 report("Explicit definition marked as implicit", MO, MONum);
529 } else if (MONum < TI.getNumOperands()) {
532 report("Explicit operand marked as def", MO, MONum);
533 if (MO->isImplicit())
534 report("Explicit operand marked as implicit", MO, MONum);
537 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
538 if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg())
539 report("Extra explicit operand on non-variadic instruction", MO, MONum);
542 switch (MO->getType()) {
543 case MachineOperand::MO_Register: {
544 const unsigned Reg = MO->getReg();
548 // Check Live Variables.
550 // An <undef> doesn't refer to any register, so just skip it.
551 } else if (MO->isUse()) {
552 regsLiveInButUnused.erase(Reg);
557 // Tied operands on two-address instuctions MUST NOT have a <kill> flag.
558 if (MI->isRegTiedToDefOperand(MONum))
559 report("Illegal kill flag on two-address instruction operand",
562 // TwoAddress instr modifying a reg is treated as kill+def.
564 if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
565 MI->getOperand(defIdx).getReg() == Reg)
569 addRegWithSubRegs(regsKilled, Reg);
571 // Check that LiveVars knows this kill
572 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg)) {
573 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
574 if (std::find(VI.Kills.begin(),
575 VI.Kills.end(), MI) == VI.Kills.end())
576 report("Kill missing from LiveVariables", MO, MONum);
580 // Use of a dead register.
581 if (!regsLive.count(Reg)) {
582 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
583 // Reserved registers may be used even when 'dead'.
584 if (!isReserved(Reg))
585 report("Using an undefined physical register", MO, MONum);
587 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
588 // We don't know which virtual registers are live in, so only complain
589 // if vreg was killed in this MBB. Otherwise keep track of vregs that
590 // must be live in. PHI instructions are handled separately.
591 if (MInfo.regsKilled.count(Reg))
592 report("Using a killed virtual register", MO, MONum);
593 else if (MI->getOpcode() != TargetInstrInfo::PHI)
594 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
600 // TODO: verify that earlyclobber ops are not used.
602 addRegWithSubRegs(regsDead, Reg);
604 addRegWithSubRegs(regsDefined, Reg);
607 // Check register classes.
608 if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
609 const TargetOperandInfo &TOI = TI.OpInfo[MONum];
610 unsigned SubIdx = MO->getSubReg();
612 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
615 unsigned s = TRI->getSubReg(Reg, SubIdx);
617 report("Invalid subregister index for physical register",
623 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
624 if (!DRC->contains(sr)) {
625 report("Illegal physical register for instruction", MO, MONum);
626 *OS << TRI->getName(sr) << " is not a "
627 << DRC->getName() << " register.\n";
632 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
634 if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) {
635 report("Invalid subregister index for virtual register", MO, MONum);
638 RC = *(RC->subregclasses_begin()+SubIdx);
640 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
641 if (RC != DRC && !RC->hasSuperClass(DRC)) {
642 report("Illegal virtual register for instruction", MO, MONum);
643 *OS << "Expected a " << DRC->getName() << " register, but got a "
644 << RC->getName() << " register\n";
652 case MachineOperand::MO_MachineBasicBlock:
653 if (MI->getOpcode() == TargetInstrInfo::PHI) {
654 if (!MO->getMBB()->isSuccessor(MI->getParent()))
655 report("PHI operand is not in the CFG", MO, MONum);
664 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
665 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
666 set_union(MInfo.regsKilled, regsKilled);
667 set_subtract(regsLive, regsKilled);
670 // Verify that both <def> and <def,dead> operands refer to dead registers.
671 RegVector defs(regsDefined);
672 defs.append(regsDead.begin(), regsDead.end());
674 for (RegVector::const_iterator I = defs.begin(), E = defs.end();
676 if (regsLive.count(*I)) {
677 if (TargetRegisterInfo::isPhysicalRegister(*I)) {
678 if (!allowPhysDoubleDefs && !isReserved(*I) &&
679 !regsLiveInButUnused.count(*I)) {
680 report("Redefining a live physical register", MI);
681 *OS << "Register " << TRI->getName(*I)
682 << " was defined but already live.\n";
685 if (!allowVirtDoubleDefs) {
686 report("Redefining a live virtual register", MI);
687 *OS << "Virtual register %reg" << *I
688 << " was defined but already live.\n";
691 } else if (TargetRegisterInfo::isVirtualRegister(*I) &&
692 !MInfo.regsKilled.count(*I)) {
693 // Virtual register defined without being killed first must be dead on
695 MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
699 set_subtract(regsLive, regsDead); regsDead.clear();
700 set_union(regsLive, regsDefined); regsDefined.clear();
704 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
705 MBBInfoMap[MBB].regsLiveOut = regsLive;
709 // Calculate the largest possible vregsPassed sets. These are the registers that
710 // can pass through an MBB live, but may not be live every time. It is assumed
711 // that all vregsPassed sets are empty before the call.
712 void MachineVerifier::calcRegsPassed() {
713 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
714 // have any vregsPassed.
715 DenseSet<const MachineBasicBlock*> todo;
716 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
718 const MachineBasicBlock &MBB(*MFI);
719 BBInfo &MInfo = MBBInfoMap[&MBB];
720 if (!MInfo.reachable)
722 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
723 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
724 BBInfo &SInfo = MBBInfoMap[*SuI];
725 if (SInfo.addPassed(MInfo.regsLiveOut))
730 // Iteratively push vregsPassed to successors. This will converge to the same
731 // final state regardless of DenseSet iteration order.
732 while (!todo.empty()) {
733 const MachineBasicBlock *MBB = *todo.begin();
735 BBInfo &MInfo = MBBInfoMap[MBB];
736 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
737 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
740 BBInfo &SInfo = MBBInfoMap[*SuI];
741 if (SInfo.addPassed(MInfo.vregsPassed))
747 // Calculate the set of virtual registers that must be passed through each basic
748 // block in order to satisfy the requirements of successor blocks. This is very
749 // similar to calcRegsPassed, only backwards.
750 void MachineVerifier::calcRegsRequired() {
751 // First push live-in regs to predecessors' vregsRequired.
752 DenseSet<const MachineBasicBlock*> todo;
753 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
755 const MachineBasicBlock &MBB(*MFI);
756 BBInfo &MInfo = MBBInfoMap[&MBB];
757 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
758 PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
759 BBInfo &PInfo = MBBInfoMap[*PrI];
760 if (PInfo.addRequired(MInfo.vregsLiveIn))
765 // Iteratively push vregsRequired to predecessors. This will converge to the
766 // same final state regardless of DenseSet iteration order.
767 while (!todo.empty()) {
768 const MachineBasicBlock *MBB = *todo.begin();
770 BBInfo &MInfo = MBBInfoMap[MBB];
771 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
772 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
775 BBInfo &SInfo = MBBInfoMap[*PrI];
776 if (SInfo.addRequired(MInfo.vregsRequired))
782 // Check PHI instructions at the beginning of MBB. It is assumed that
783 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
784 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
785 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
786 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
787 DenseSet<const MachineBasicBlock*> seen;
789 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
790 unsigned Reg = BBI->getOperand(i).getReg();
791 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
792 if (!Pre->isSuccessor(MBB))
795 BBInfo &PrInfo = MBBInfoMap[Pre];
796 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
797 report("PHI operand is not live-out from predecessor",
798 &BBI->getOperand(i), i);
801 // Did we see all predecessors?
802 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
803 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
804 if (!seen.count(*PrI)) {
805 report("Missing PHI operand", BBI);
806 *OS << "BB#" << (*PrI)->getNumber()
807 << " is a predecessor according to the CFG.\n";
813 void MachineVerifier::visitMachineFunctionAfter() {
816 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
818 BBInfo &MInfo = MBBInfoMap[MFI];
820 // Skip unreachable MBBs.
821 if (!MInfo.reachable)
826 // Verify dead-in virtual registers.
827 if (!allowVirtDoubleDefs) {
828 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
829 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
830 BBInfo &PrInfo = MBBInfoMap[*PrI];
831 if (!PrInfo.reachable)
834 for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
835 E = MInfo.vregsDeadIn.end(); I != E; ++I) {
836 // DeadIn register must be in neither regsLiveOut or vregsPassed of
838 if (PrInfo.isLiveOut(I->first)) {
839 report("Live-in virtual register redefined", I->second);
840 *OS << "Register %reg" << I->first
841 << " was live-out from predecessor MBB #"
842 << (*PrI)->getNumber() << ".\n";
849 // Now check LiveVariables info if available
852 verifyLiveVariables();
856 void MachineVerifier::verifyLiveVariables() {
857 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
858 for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister,
859 RegE = MRI->getLastVirtReg()-1; Reg != RegE; ++Reg) {
860 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
861 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
863 BBInfo &MInfo = MBBInfoMap[MFI];
865 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
866 if (MInfo.vregsRequired.count(Reg)) {
867 if (!VI.AliveBlocks.test(MFI->getNumber())) {
868 report("LiveVariables: Block missing from AliveBlocks", MFI);
869 *OS << "Virtual register %reg" << Reg
870 << " must be live through the block.\n";
873 if (VI.AliveBlocks.test(MFI->getNumber())) {
874 report("LiveVariables: Block should not be in AliveBlocks", MFI);
875 *OS << "Virtual register %reg" << Reg
876 << " is not needed live through the block.\n";