1 //===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/Function.h"
27 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
28 #include "llvm/CodeGen/LiveVariables.h"
29 #include "llvm/CodeGen/LiveStackAnalysis.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetRegisterInfo.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/ADT/DenseSet.h"
39 #include "llvm/ADT/SetOperations.h"
40 #include "llvm/ADT/SmallVector.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/raw_ostream.h"
47 struct MachineVerifier {
49 MachineVerifier(Pass *pass) :
51 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
54 bool runOnMachineFunction(MachineFunction &MF);
57 const char *const OutFileName;
59 const MachineFunction *MF;
60 const TargetMachine *TM;
61 const TargetRegisterInfo *TRI;
62 const MachineRegisterInfo *MRI;
66 typedef SmallVector<unsigned, 16> RegVector;
67 typedef DenseSet<unsigned> RegSet;
68 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
70 BitVector regsReserved;
72 RegVector regsDefined, regsDead, regsKilled;
73 RegSet regsLiveInButUnused;
75 // Add Reg and any sub-registers to RV
76 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
78 if (TargetRegisterInfo::isPhysicalRegister(Reg))
79 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
84 // Is this MBB reachable from the MF entry point?
87 // Vregs that must be live in because they are used without being
88 // defined. Map value is the user.
91 // Regs killed in MBB. They may be defined again, and will then be in both
92 // regsKilled and regsLiveOut.
95 // Regs defined in MBB and live out. Note that vregs passing through may
96 // be live out without being mentioned here.
99 // Vregs that pass through MBB untouched. This set is disjoint from
100 // regsKilled and regsLiveOut.
103 // Vregs that must pass through MBB because they are needed by a successor
104 // block. This set is disjoint from regsLiveOut.
105 RegSet vregsRequired;
107 BBInfo() : reachable(false) {}
109 // Add register to vregsPassed if it belongs there. Return true if
111 bool addPassed(unsigned Reg) {
112 if (!TargetRegisterInfo::isVirtualRegister(Reg))
114 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
116 return vregsPassed.insert(Reg).second;
119 // Same for a full set.
120 bool addPassed(const RegSet &RS) {
121 bool changed = false;
122 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
128 // Add register to vregsRequired if it belongs there. Return true if
130 bool addRequired(unsigned Reg) {
131 if (!TargetRegisterInfo::isVirtualRegister(Reg))
133 if (regsLiveOut.count(Reg))
135 return vregsRequired.insert(Reg).second;
138 // Same for a full set.
139 bool addRequired(const RegSet &RS) {
140 bool changed = false;
141 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
147 // Same for a full map.
148 bool addRequired(const RegMap &RM) {
149 bool changed = false;
150 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
151 if (addRequired(I->first))
156 // Live-out registers are either in regsLiveOut or vregsPassed.
157 bool isLiveOut(unsigned Reg) const {
158 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
162 // Extra register info per MBB.
163 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
165 bool isReserved(unsigned Reg) {
166 return Reg < regsReserved.size() && regsReserved.test(Reg);
169 // Analysis information if available
170 LiveVariables *LiveVars;
171 LiveIntervals *LiveInts;
172 LiveStacks *LiveStks;
173 SlotIndexes *Indexes;
175 void visitMachineFunctionBefore();
176 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
177 void visitMachineInstrBefore(const MachineInstr *MI);
178 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
179 void visitMachineInstrAfter(const MachineInstr *MI);
180 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
181 void visitMachineFunctionAfter();
183 void report(const char *msg, const MachineFunction *MF);
184 void report(const char *msg, const MachineBasicBlock *MBB);
185 void report(const char *msg, const MachineInstr *MI);
186 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
188 void markReachable(const MachineBasicBlock *MBB);
189 void calcRegsPassed();
190 void checkPHIOps(const MachineBasicBlock *MBB);
192 void calcRegsRequired();
193 void verifyLiveVariables();
194 void verifyLiveIntervals();
197 struct MachineVerifierPass : public MachineFunctionPass {
198 static char ID; // Pass ID, replacement for typeid
200 MachineVerifierPass()
201 : MachineFunctionPass(ID) {
202 initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
205 void getAnalysisUsage(AnalysisUsage &AU) const {
206 AU.setPreservesAll();
207 MachineFunctionPass::getAnalysisUsage(AU);
210 bool runOnMachineFunction(MachineFunction &MF) {
218 char MachineVerifierPass::ID = 0;
219 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
220 "Verify generated machine code", false, false)
222 FunctionPass *llvm::createMachineVerifierPass() {
223 return new MachineVerifierPass();
226 void MachineFunction::verify(Pass *p) const {
227 MachineVerifier(p).runOnMachineFunction(const_cast<MachineFunction&>(*this));
230 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
231 raw_ostream *OutFile = 0;
233 std::string ErrorInfo;
234 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
235 raw_fd_ostream::F_Append);
236 if (!ErrorInfo.empty()) {
237 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
249 TM = &MF.getTarget();
250 TRI = TM->getRegisterInfo();
251 MRI = &MF.getRegInfo();
258 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
259 // We don't want to verify LiveVariables if LiveIntervals is available.
261 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
262 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
263 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
266 visitMachineFunctionBefore();
267 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
269 visitMachineBasicBlockBefore(MFI);
270 for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
271 MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
272 visitMachineInstrBefore(MBBI);
273 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
274 visitMachineOperand(&MBBI->getOperand(I), I);
275 visitMachineInstrAfter(MBBI);
277 visitMachineBasicBlockAfter(MFI);
279 visitMachineFunctionAfter();
283 else if (foundErrors)
284 report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
291 regsLiveInButUnused.clear();
294 return false; // no changes
297 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
301 MF->print(*OS, Indexes);
302 *OS << "*** Bad machine code: " << msg << " ***\n"
303 << "- function: " << MF->getFunction()->getNameStr() << "\n";
306 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
308 report(msg, MBB->getParent());
309 *OS << "- basic block: " << MBB->getName()
311 << " (BB#" << MBB->getNumber() << ")";
313 *OS << " [" << Indexes->getMBBStartIdx(MBB)
314 << ';' << Indexes->getMBBEndIdx(MBB) << ')';
318 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
320 report(msg, MI->getParent());
321 *OS << "- instruction: ";
322 if (Indexes && Indexes->hasIndex(MI))
323 *OS << Indexes->getInstructionIndex(MI) << '\t';
327 void MachineVerifier::report(const char *msg,
328 const MachineOperand *MO, unsigned MONum) {
330 report(msg, MO->getParent());
331 *OS << "- operand " << MONum << ": ";
336 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
337 BBInfo &MInfo = MBBInfoMap[MBB];
338 if (!MInfo.reachable) {
339 MInfo.reachable = true;
340 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
341 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
346 void MachineVerifier::visitMachineFunctionBefore() {
347 regsReserved = TRI->getReservedRegs(*MF);
349 // A sub-register of a reserved register is also reserved
350 for (int Reg = regsReserved.find_first(); Reg>=0;
351 Reg = regsReserved.find_next(Reg)) {
352 for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
353 // FIXME: This should probably be:
354 // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
355 regsReserved.set(*Sub);
358 markReachable(&MF->front());
361 // Does iterator point to a and b as the first two elements?
362 static bool matchPair(MachineBasicBlock::const_succ_iterator i,
363 const MachineBasicBlock *a, const MachineBasicBlock *b) {
372 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
373 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
375 // Count the number of landing pad successors.
376 unsigned LandingPadSuccs = 0;
377 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
378 E = MBB->succ_end(); I != E; ++I)
379 LandingPadSuccs += (*I)->isLandingPad();
380 if (LandingPadSuccs > 1)
381 report("MBB has more than one landing pad successor", MBB);
383 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
384 MachineBasicBlock *TBB = 0, *FBB = 0;
385 SmallVector<MachineOperand, 4> Cond;
386 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
388 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
389 // check whether its answers match up with reality.
391 // Block falls through to its successor.
392 MachineFunction::const_iterator MBBI = MBB;
394 if (MBBI == MF->end()) {
395 // It's possible that the block legitimately ends with a noreturn
396 // call or an unreachable, in which case it won't actually fall
397 // out the bottom of the function.
398 } else if (MBB->succ_size() == LandingPadSuccs) {
399 // It's possible that the block legitimately ends with a noreturn
400 // call or an unreachable, in which case it won't actuall fall
402 } else if (MBB->succ_size() != 1+LandingPadSuccs) {
403 report("MBB exits via unconditional fall-through but doesn't have "
404 "exactly one CFG successor!", MBB);
405 } else if (!MBB->isSuccessor(MBBI)) {
406 report("MBB exits via unconditional fall-through but its successor "
407 "differs from its CFG successor!", MBB);
409 if (!MBB->empty() && MBB->back().getDesc().isBarrier() &&
410 !TII->isPredicated(&MBB->back())) {
411 report("MBB exits via unconditional fall-through but ends with a "
412 "barrier instruction!", MBB);
415 report("MBB exits via unconditional fall-through but has a condition!",
418 } else if (TBB && !FBB && Cond.empty()) {
419 // Block unconditionally branches somewhere.
420 if (MBB->succ_size() != 1+LandingPadSuccs) {
421 report("MBB exits via unconditional branch but doesn't have "
422 "exactly one CFG successor!", MBB);
423 } else if (!MBB->isSuccessor(TBB)) {
424 report("MBB exits via unconditional branch but the CFG "
425 "successor doesn't match the actual successor!", MBB);
428 report("MBB exits via unconditional branch but doesn't contain "
429 "any instructions!", MBB);
430 } else if (!MBB->back().getDesc().isBarrier()) {
431 report("MBB exits via unconditional branch but doesn't end with a "
432 "barrier instruction!", MBB);
433 } else if (!MBB->back().getDesc().isTerminator()) {
434 report("MBB exits via unconditional branch but the branch isn't a "
435 "terminator instruction!", MBB);
437 } else if (TBB && !FBB && !Cond.empty()) {
438 // Block conditionally branches somewhere, otherwise falls through.
439 MachineFunction::const_iterator MBBI = MBB;
441 if (MBBI == MF->end()) {
442 report("MBB conditionally falls through out of function!", MBB);
443 } if (MBB->succ_size() != 2) {
444 report("MBB exits via conditional branch/fall-through but doesn't have "
445 "exactly two CFG successors!", MBB);
446 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
447 report("MBB exits via conditional branch/fall-through but the CFG "
448 "successors don't match the actual successors!", MBB);
451 report("MBB exits via conditional branch/fall-through but doesn't "
452 "contain any instructions!", MBB);
453 } else if (MBB->back().getDesc().isBarrier()) {
454 report("MBB exits via conditional branch/fall-through but ends with a "
455 "barrier instruction!", MBB);
456 } else if (!MBB->back().getDesc().isTerminator()) {
457 report("MBB exits via conditional branch/fall-through but the branch "
458 "isn't a terminator instruction!", MBB);
460 } else if (TBB && FBB) {
461 // Block conditionally branches somewhere, otherwise branches
463 if (MBB->succ_size() != 2) {
464 report("MBB exits via conditional branch/branch but doesn't have "
465 "exactly two CFG successors!", MBB);
466 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
467 report("MBB exits via conditional branch/branch but the CFG "
468 "successors don't match the actual successors!", MBB);
471 report("MBB exits via conditional branch/branch but doesn't "
472 "contain any instructions!", MBB);
473 } else if (!MBB->back().getDesc().isBarrier()) {
474 report("MBB exits via conditional branch/branch but doesn't end with a "
475 "barrier instruction!", MBB);
476 } else if (!MBB->back().getDesc().isTerminator()) {
477 report("MBB exits via conditional branch/branch but the branch "
478 "isn't a terminator instruction!", MBB);
481 report("MBB exits via conditinal branch/branch but there's no "
485 report("AnalyzeBranch returned invalid data!", MBB);
490 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
491 E = MBB->livein_end(); I != E; ++I) {
492 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
493 report("MBB live-in list contains non-physical register", MBB);
497 for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
500 regsLiveInButUnused = regsLive;
502 const MachineFrameInfo *MFI = MF->getFrameInfo();
503 assert(MFI && "Function has no frame info");
504 BitVector PR = MFI->getPristineRegs(MBB);
505 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
507 for (const unsigned *R = TRI->getSubRegisters(I); *R; R++)
515 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
516 const TargetInstrDesc &TI = MI->getDesc();
517 if (MI->getNumOperands() < TI.getNumOperands()) {
518 report("Too few operands", MI);
519 *OS << TI.getNumOperands() << " operands expected, but "
520 << MI->getNumExplicitOperands() << " given.\n";
523 // Check the MachineMemOperands for basic consistency.
524 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
525 E = MI->memoperands_end(); I != E; ++I) {
526 if ((*I)->isLoad() && !TI.mayLoad())
527 report("Missing mayLoad flag", MI);
528 if ((*I)->isStore() && !TI.mayStore())
529 report("Missing mayStore flag", MI);
532 // Debug values must not have a slot index.
533 // Other instructions must have one.
535 bool mapped = !LiveInts->isNotInMIMap(MI);
536 if (MI->isDebugValue()) {
538 report("Debug instruction has a slot index", MI);
541 report("Missing slot index", MI);
548 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
549 const MachineInstr *MI = MO->getParent();
550 const TargetInstrDesc &TI = MI->getDesc();
552 // The first TI.NumDefs operands must be explicit register defines
553 if (MONum < TI.getNumDefs()) {
555 report("Explicit definition must be a register", MO, MONum);
556 else if (!MO->isDef())
557 report("Explicit definition marked as use", MO, MONum);
558 else if (MO->isImplicit())
559 report("Explicit definition marked as implicit", MO, MONum);
560 } else if (MONum < TI.getNumOperands()) {
563 report("Explicit operand marked as def", MO, MONum);
564 if (MO->isImplicit())
565 report("Explicit operand marked as implicit", MO, MONum);
568 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
569 if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg())
570 report("Extra explicit operand on non-variadic instruction", MO, MONum);
573 switch (MO->getType()) {
574 case MachineOperand::MO_Register: {
575 const unsigned Reg = MO->getReg();
579 // Check Live Variables.
581 // An <undef> doesn't refer to any register, so just skip it.
582 } else if (MO->isUse()) {
583 regsLiveInButUnused.erase(Reg);
587 if (MI->isRegTiedToDefOperand(MONum, &defIdx)) {
588 // A two-addr use counts as a kill if use and def are the same.
589 unsigned DefReg = MI->getOperand(defIdx).getReg();
592 // And in that case an explicit kill flag is not allowed.
594 report("Illegal kill flag on two-address instruction operand",
596 } else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
597 report("Two-address instruction operands must be identical",
601 isKill = MO->isKill();
604 addRegWithSubRegs(regsKilled, Reg);
606 // Check that LiveVars knows this kill.
607 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
609 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
610 if (std::find(VI.Kills.begin(),
611 VI.Kills.end(), MI) == VI.Kills.end())
612 report("Kill missing from LiveVariables", MO, MONum);
615 // Check LiveInts liveness and kill.
616 if (TargetRegisterInfo::isVirtualRegister(Reg) &&
617 LiveInts && !LiveInts->isNotInMIMap(MI)) {
618 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI).getUseIndex();
619 if (LiveInts->hasInterval(Reg)) {
620 const LiveInterval &LI = LiveInts->getInterval(Reg);
621 if (!LI.liveAt(UseIdx)) {
622 report("No live range at use", MO, MONum);
623 *OS << UseIdx << " is not live in " << LI << '\n';
625 // Verify isKill == LI.killedAt.
626 if (!MI->isRegTiedToDefOperand(MONum)) {
627 bool liKill = LI.killedAt(UseIdx.getDefIndex());
628 if (isKill && !liKill) {
629 report("Live range continues after kill flag", MO, MONum);
630 *OS << "Live range: " << LI << '\n';
632 if (!isKill && liKill) {
633 report("Live range ends without kill flag", MO, MONum);
634 *OS << "Live range: " << LI << '\n';
638 report("Virtual register has no Live interval", MO, MONum);
642 // Use of a dead register.
643 if (!regsLive.count(Reg)) {
644 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
645 // Reserved registers may be used even when 'dead'.
646 if (!isReserved(Reg))
647 report("Using an undefined physical register", MO, MONum);
649 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
650 // We don't know which virtual registers are live in, so only complain
651 // if vreg was killed in this MBB. Otherwise keep track of vregs that
652 // must be live in. PHI instructions are handled separately.
653 if (MInfo.regsKilled.count(Reg))
654 report("Using a killed virtual register", MO, MONum);
655 else if (!MI->isPHI())
656 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
662 // TODO: verify that earlyclobber ops are not used.
664 addRegWithSubRegs(regsDead, Reg);
666 addRegWithSubRegs(regsDefined, Reg);
668 // Check LiveInts for a live range, but only for virtual registers.
669 if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
670 !LiveInts->isNotInMIMap(MI)) {
671 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI).getDefIndex();
672 if (LiveInts->hasInterval(Reg)) {
673 const LiveInterval &LI = LiveInts->getInterval(Reg);
674 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
675 assert(VNI && "NULL valno is not allowed");
676 if (VNI->def != DefIdx) {
677 report("Inconsistent valno->def", MO, MONum);
678 *OS << "Valno " << VNI->id << " is not defined at "
679 << DefIdx << " in " << LI << '\n';
682 report("No live range at def", MO, MONum);
683 *OS << DefIdx << " is not live in " << LI << '\n';
686 report("Virtual register has no Live interval", MO, MONum);
691 // Check register classes.
692 if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
693 const TargetOperandInfo &TOI = TI.OpInfo[MONum];
694 unsigned SubIdx = MO->getSubReg();
696 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
699 unsigned s = TRI->getSubReg(Reg, SubIdx);
701 report("Invalid subregister index for physical register",
707 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
708 if (!DRC->contains(sr)) {
709 report("Illegal physical register for instruction", MO, MONum);
710 *OS << TRI->getName(sr) << " is not a "
711 << DRC->getName() << " register.\n";
716 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
718 const TargetRegisterClass *SRC = RC->getSubRegisterRegClass(SubIdx);
720 report("Invalid subregister index for virtual register", MO, MONum);
721 *OS << "Register class " << RC->getName()
722 << " does not support subreg index " << SubIdx << "\n";
727 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
728 if (RC != DRC && !RC->hasSuperClass(DRC)) {
729 report("Illegal virtual register for instruction", MO, MONum);
730 *OS << "Expected a " << DRC->getName() << " register, but got a "
731 << RC->getName() << " register\n";
739 case MachineOperand::MO_MachineBasicBlock:
740 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
741 report("PHI operand is not in the CFG", MO, MONum);
744 case MachineOperand::MO_FrameIndex:
745 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
746 LiveInts && !LiveInts->isNotInMIMap(MI)) {
747 LiveInterval &LI = LiveStks->getInterval(MO->getIndex());
748 SlotIndex Idx = LiveInts->getInstructionIndex(MI);
749 if (TI.mayLoad() && !LI.liveAt(Idx.getUseIndex())) {
750 report("Instruction loads from dead spill slot", MO, MONum);
751 *OS << "Live stack: " << LI << '\n';
753 if (TI.mayStore() && !LI.liveAt(Idx.getDefIndex())) {
754 report("Instruction stores to dead spill slot", MO, MONum);
755 *OS << "Live stack: " << LI << '\n';
765 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
766 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
767 set_union(MInfo.regsKilled, regsKilled);
768 set_subtract(regsLive, regsKilled); regsKilled.clear();
769 set_subtract(regsLive, regsDead); regsDead.clear();
770 set_union(regsLive, regsDefined); regsDefined.clear();
774 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
775 MBBInfoMap[MBB].regsLiveOut = regsLive;
779 // Calculate the largest possible vregsPassed sets. These are the registers that
780 // can pass through an MBB live, but may not be live every time. It is assumed
781 // that all vregsPassed sets are empty before the call.
782 void MachineVerifier::calcRegsPassed() {
783 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
784 // have any vregsPassed.
785 DenseSet<const MachineBasicBlock*> todo;
786 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
788 const MachineBasicBlock &MBB(*MFI);
789 BBInfo &MInfo = MBBInfoMap[&MBB];
790 if (!MInfo.reachable)
792 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
793 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
794 BBInfo &SInfo = MBBInfoMap[*SuI];
795 if (SInfo.addPassed(MInfo.regsLiveOut))
800 // Iteratively push vregsPassed to successors. This will converge to the same
801 // final state regardless of DenseSet iteration order.
802 while (!todo.empty()) {
803 const MachineBasicBlock *MBB = *todo.begin();
805 BBInfo &MInfo = MBBInfoMap[MBB];
806 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
807 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
810 BBInfo &SInfo = MBBInfoMap[*SuI];
811 if (SInfo.addPassed(MInfo.vregsPassed))
817 // Calculate the set of virtual registers that must be passed through each basic
818 // block in order to satisfy the requirements of successor blocks. This is very
819 // similar to calcRegsPassed, only backwards.
820 void MachineVerifier::calcRegsRequired() {
821 // First push live-in regs to predecessors' vregsRequired.
822 DenseSet<const MachineBasicBlock*> todo;
823 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
825 const MachineBasicBlock &MBB(*MFI);
826 BBInfo &MInfo = MBBInfoMap[&MBB];
827 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
828 PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
829 BBInfo &PInfo = MBBInfoMap[*PrI];
830 if (PInfo.addRequired(MInfo.vregsLiveIn))
835 // Iteratively push vregsRequired to predecessors. This will converge to the
836 // same final state regardless of DenseSet iteration order.
837 while (!todo.empty()) {
838 const MachineBasicBlock *MBB = *todo.begin();
840 BBInfo &MInfo = MBBInfoMap[MBB];
841 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
842 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
845 BBInfo &SInfo = MBBInfoMap[*PrI];
846 if (SInfo.addRequired(MInfo.vregsRequired))
852 // Check PHI instructions at the beginning of MBB. It is assumed that
853 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
854 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
855 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
856 BBI != BBE && BBI->isPHI(); ++BBI) {
857 DenseSet<const MachineBasicBlock*> seen;
859 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
860 unsigned Reg = BBI->getOperand(i).getReg();
861 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
862 if (!Pre->isSuccessor(MBB))
865 BBInfo &PrInfo = MBBInfoMap[Pre];
866 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
867 report("PHI operand is not live-out from predecessor",
868 &BBI->getOperand(i), i);
871 // Did we see all predecessors?
872 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
873 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
874 if (!seen.count(*PrI)) {
875 report("Missing PHI operand", BBI);
876 *OS << "BB#" << (*PrI)->getNumber()
877 << " is a predecessor according to the CFG.\n";
883 void MachineVerifier::visitMachineFunctionAfter() {
886 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
888 BBInfo &MInfo = MBBInfoMap[MFI];
890 // Skip unreachable MBBs.
891 if (!MInfo.reachable)
897 // Now check liveness info if available
898 if (LiveVars || LiveInts)
901 verifyLiveVariables();
903 verifyLiveIntervals();
906 void MachineVerifier::verifyLiveVariables() {
907 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
908 for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister,
909 RegE = MRI->getLastVirtReg()-1; Reg != RegE; ++Reg) {
910 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
911 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
913 BBInfo &MInfo = MBBInfoMap[MFI];
915 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
916 if (MInfo.vregsRequired.count(Reg)) {
917 if (!VI.AliveBlocks.test(MFI->getNumber())) {
918 report("LiveVariables: Block missing from AliveBlocks", MFI);
919 *OS << "Virtual register %reg" << Reg
920 << " must be live through the block.\n";
923 if (VI.AliveBlocks.test(MFI->getNumber())) {
924 report("LiveVariables: Block should not be in AliveBlocks", MFI);
925 *OS << "Virtual register %reg" << Reg
926 << " is not needed live through the block.\n";
933 void MachineVerifier::verifyLiveIntervals() {
934 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
935 for (LiveIntervals::const_iterator LVI = LiveInts->begin(),
936 LVE = LiveInts->end(); LVI != LVE; ++LVI) {
937 const LiveInterval &LI = *LVI->second;
939 // Spilling and splitting may leave unused registers around. Skip them.
940 if (MRI->use_empty(LI.reg))
943 // Physical registers have much weirdness going on, mostly from coalescing.
944 // We should probably fix it, but for now just ignore them.
945 if (TargetRegisterInfo::isPhysicalRegister(LI.reg))
948 assert(LVI->first == LI.reg && "Invalid reg to interval mapping");
950 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
953 const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def);
956 if (!VNI->isUnused()) {
957 report("Valno not live at def and not marked unused", MF);
958 *OS << "Valno #" << VNI->id << " in " << LI << '\n';
967 report("Live range at def has different valno", MF);
968 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
969 << " where valno #" << DefVNI->id << " is live in " << LI << '\n';
973 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
975 report("Invalid definition index", MF);
976 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
977 << " in " << LI << '\n';
981 if (VNI->isPHIDef()) {
982 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
983 report("PHIDef value is not defined at MBB start", MF);
984 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
985 << ", not at the beginning of BB#" << MBB->getNumber()
986 << " in " << LI << '\n';
990 if (!VNI->def.isDef()) {
991 report("Non-PHI def must be at a DEF slot", MF);
992 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
993 << " in " << LI << '\n';
995 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
997 report("No instruction at def index", MF);
998 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
999 << " in " << LI << '\n';
1000 } else if (!MI->modifiesRegister(LI.reg, TRI)) {
1001 report("Defining instruction does not modify register", MI);
1002 *OS << "Valno #" << VNI->id << " in " << LI << '\n';
1007 for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I) {
1008 const VNInfo *VNI = I->valno;
1009 assert(VNI && "Live range has no valno");
1011 if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) {
1012 report("Foreign valno in live range", MF);
1014 *OS << " has a valno not in " << LI << '\n';
1017 if (VNI->isUnused()) {
1018 report("Live range valno is marked unused", MF);
1020 *OS << " in " << LI << '\n';
1023 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(I->start);
1025 report("Bad start of live segment, no basic block", MF);
1027 *OS << " in " << LI << '\n';
1030 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
1031 if (I->start != MBBStartIdx && I->start != VNI->def) {
1032 report("Live segment must begin at MBB entry or valno def", MBB);
1034 *OS << " in " << LI << '\n' << "Basic block starts at "
1035 << MBBStartIdx << '\n';
1038 const MachineBasicBlock *EndMBB =
1039 LiveInts->getMBBFromIndex(I->end.getPrevSlot());
1041 report("Bad end of live segment, no basic block", MF);
1043 *OS << " in " << LI << '\n';
1046 if (I->end != LiveInts->getMBBEndIdx(EndMBB)) {
1047 // The live segment is ending inside EndMBB
1048 const MachineInstr *MI =
1049 LiveInts->getInstructionFromIndex(I->end.getPrevSlot());
1051 report("Live segment doesn't end at a valid instruction", EndMBB);
1053 *OS << " in " << LI << '\n' << "Basic block starts at "
1054 << MBBStartIdx << '\n';
1055 } else if (TargetRegisterInfo::isVirtualRegister(LI.reg) &&
1056 !MI->readsVirtualRegister(LI.reg)) {
1057 // FIXME: Should we require a kill flag?
1058 report("Instruction killing live segment doesn't read register", MI);
1060 *OS << " in " << LI << '\n';
1064 // Now check all the basic blocks in this live segment.
1065 MachineFunction::const_iterator MFI = MBB;
1066 // Is LI live-in to MBB and not a PHIDef?
1067 if (I->start == VNI->def) {
1068 // Not live-in to any blocks.
1075 assert(LiveInts->isLiveInToMBB(LI, MFI));
1076 // We don't know how to track physregs into a landing pad.
1077 if (TargetRegisterInfo::isPhysicalRegister(LI.reg) &&
1078 MFI->isLandingPad()) {
1079 if (&*MFI == EndMBB)
1084 // Check that VNI is live-out of all predecessors.
1085 for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
1086 PE = MFI->pred_end(); PI != PE; ++PI) {
1087 SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI).getPrevSlot();
1088 const VNInfo *PVNI = LI.getVNInfoAt(PEnd);
1090 report("Register not marked live out of predecessor", *PI);
1091 *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
1092 << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live at "
1093 << PEnd << " in " << LI << '\n';
1094 } else if (PVNI != VNI) {
1095 report("Different value live out of predecessor", *PI);
1096 *OS << "Valno #" << PVNI->id << " live out of BB#"
1097 << (*PI)->getNumber() << '@' << PEnd
1098 << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
1099 << '@' << LiveInts->getMBBStartIdx(MFI) << " in " << LI << '\n';
1102 if (&*MFI == EndMBB)
1108 // Check the LI only has one connected component.
1109 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1110 ConnectedVNInfoEqClasses ConEQ(*LiveInts);
1111 unsigned NumComp = ConEQ.Classify(&LI);
1113 report("Multiple connected components in live interval", MF);
1114 *OS << NumComp << " components in " << LI << '\n';
1115 for (unsigned comp = 0; comp != NumComp; ++comp) {
1116 *OS << comp << ": valnos";
1117 for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
1118 E = LI.vni_end(); I!=E; ++I)
1119 if (comp == ConEQ.getEqClass(*I))
1120 *OS << ' ' << (*I)->id;