1 //===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/Function.h"
27 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
28 #include "llvm/CodeGen/LiveVariables.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetRegisterInfo.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/ADT/DenseSet.h"
38 #include "llvm/ADT/SetOperations.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/raw_ostream.h"
46 struct MachineVerifier {
48 MachineVerifier(Pass *pass) :
50 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
53 bool runOnMachineFunction(MachineFunction &MF);
56 const char *const OutFileName;
58 const MachineFunction *MF;
59 const TargetMachine *TM;
60 const TargetRegisterInfo *TRI;
61 const MachineRegisterInfo *MRI;
65 typedef SmallVector<unsigned, 16> RegVector;
66 typedef DenseSet<unsigned> RegSet;
67 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
69 BitVector regsReserved;
71 RegVector regsDefined, regsDead, regsKilled;
72 RegSet regsLiveInButUnused;
74 // Add Reg and any sub-registers to RV
75 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
77 if (TargetRegisterInfo::isPhysicalRegister(Reg))
78 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
83 // Is this MBB reachable from the MF entry point?
86 // Vregs that must be live in because they are used without being
87 // defined. Map value is the user.
90 // Regs killed in MBB. They may be defined again, and will then be in both
91 // regsKilled and regsLiveOut.
94 // Regs defined in MBB and live out. Note that vregs passing through may
95 // be live out without being mentioned here.
98 // Vregs that pass through MBB untouched. This set is disjoint from
99 // regsKilled and regsLiveOut.
102 // Vregs that must pass through MBB because they are needed by a successor
103 // block. This set is disjoint from regsLiveOut.
104 RegSet vregsRequired;
106 BBInfo() : reachable(false) {}
108 // Add register to vregsPassed if it belongs there. Return true if
110 bool addPassed(unsigned Reg) {
111 if (!TargetRegisterInfo::isVirtualRegister(Reg))
113 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
115 return vregsPassed.insert(Reg).second;
118 // Same for a full set.
119 bool addPassed(const RegSet &RS) {
120 bool changed = false;
121 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
127 // Add register to vregsRequired if it belongs there. Return true if
129 bool addRequired(unsigned Reg) {
130 if (!TargetRegisterInfo::isVirtualRegister(Reg))
132 if (regsLiveOut.count(Reg))
134 return vregsRequired.insert(Reg).second;
137 // Same for a full set.
138 bool addRequired(const RegSet &RS) {
139 bool changed = false;
140 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
146 // Same for a full map.
147 bool addRequired(const RegMap &RM) {
148 bool changed = false;
149 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
150 if (addRequired(I->first))
155 // Live-out registers are either in regsLiveOut or vregsPassed.
156 bool isLiveOut(unsigned Reg) const {
157 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
161 // Extra register info per MBB.
162 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
164 bool isReserved(unsigned Reg) {
165 return Reg < regsReserved.size() && regsReserved.test(Reg);
168 // Analysis information if available
169 LiveVariables *LiveVars;
170 const LiveIntervals *LiveInts;
172 void visitMachineFunctionBefore();
173 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
174 void visitMachineInstrBefore(const MachineInstr *MI);
175 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
176 void visitMachineInstrAfter(const MachineInstr *MI);
177 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
178 void visitMachineFunctionAfter();
180 void report(const char *msg, const MachineFunction *MF);
181 void report(const char *msg, const MachineBasicBlock *MBB);
182 void report(const char *msg, const MachineInstr *MI);
183 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
185 void markReachable(const MachineBasicBlock *MBB);
186 void calcRegsPassed();
187 void checkPHIOps(const MachineBasicBlock *MBB);
189 void calcRegsRequired();
190 void verifyLiveVariables();
191 void verifyLiveIntervals();
194 struct MachineVerifierPass : public MachineFunctionPass {
195 static char ID; // Pass ID, replacement for typeid
197 MachineVerifierPass()
198 : MachineFunctionPass(ID) {}
200 void getAnalysisUsage(AnalysisUsage &AU) const {
201 AU.setPreservesAll();
202 MachineFunctionPass::getAnalysisUsage(AU);
205 bool runOnMachineFunction(MachineFunction &MF) {
213 char MachineVerifierPass::ID = 0;
214 static RegisterPass<MachineVerifierPass>
215 MachineVer("machineverifier", "Verify generated machine code");
216 static const PassInfo *const MachineVerifyID = &MachineVer;
218 FunctionPass *llvm::createMachineVerifierPass() {
219 return new MachineVerifierPass();
222 void MachineFunction::verify(Pass *p) const {
223 MachineVerifier(p).runOnMachineFunction(const_cast<MachineFunction&>(*this));
226 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
227 raw_ostream *OutFile = 0;
229 std::string ErrorInfo;
230 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
231 raw_fd_ostream::F_Append);
232 if (!ErrorInfo.empty()) {
233 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
245 TM = &MF.getTarget();
246 TRI = TM->getRegisterInfo();
247 MRI = &MF.getRegInfo();
252 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
253 // We don't want to verify LiveVariables if LiveIntervals is available.
255 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
258 visitMachineFunctionBefore();
259 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
261 visitMachineBasicBlockBefore(MFI);
262 for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
263 MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
264 visitMachineInstrBefore(MBBI);
265 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
266 visitMachineOperand(&MBBI->getOperand(I), I);
267 visitMachineInstrAfter(MBBI);
269 visitMachineBasicBlockAfter(MFI);
271 visitMachineFunctionAfter();
275 else if (foundErrors)
276 report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
283 regsLiveInButUnused.clear();
286 return false; // no changes
289 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
294 *OS << "*** Bad machine code: " << msg << " ***\n"
295 << "- function: " << MF->getFunction()->getNameStr() << "\n";
298 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
300 report(msg, MBB->getParent());
301 *OS << "- basic block: " << MBB->getName()
303 << " (BB#" << MBB->getNumber() << ")\n";
306 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
308 report(msg, MI->getParent());
309 *OS << "- instruction: ";
313 void MachineVerifier::report(const char *msg,
314 const MachineOperand *MO, unsigned MONum) {
316 report(msg, MO->getParent());
317 *OS << "- operand " << MONum << ": ";
322 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
323 BBInfo &MInfo = MBBInfoMap[MBB];
324 if (!MInfo.reachable) {
325 MInfo.reachable = true;
326 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
327 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
332 void MachineVerifier::visitMachineFunctionBefore() {
333 regsReserved = TRI->getReservedRegs(*MF);
335 // A sub-register of a reserved register is also reserved
336 for (int Reg = regsReserved.find_first(); Reg>=0;
337 Reg = regsReserved.find_next(Reg)) {
338 for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
339 // FIXME: This should probably be:
340 // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
341 regsReserved.set(*Sub);
344 markReachable(&MF->front());
347 // Does iterator point to a and b as the first two elements?
348 static bool matchPair(MachineBasicBlock::const_succ_iterator i,
349 const MachineBasicBlock *a, const MachineBasicBlock *b) {
358 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
359 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
361 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
362 MachineBasicBlock *TBB = 0, *FBB = 0;
363 SmallVector<MachineOperand, 4> Cond;
364 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
366 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
367 // check whether its answers match up with reality.
369 // Block falls through to its successor.
370 MachineFunction::const_iterator MBBI = MBB;
372 if (MBBI == MF->end()) {
373 // It's possible that the block legitimately ends with a noreturn
374 // call or an unreachable, in which case it won't actually fall
375 // out the bottom of the function.
376 } else if (MBB->succ_empty()) {
377 // It's possible that the block legitimately ends with a noreturn
378 // call or an unreachable, in which case it won't actuall fall
380 } else if (MBB->succ_size() != 1) {
381 report("MBB exits via unconditional fall-through but doesn't have "
382 "exactly one CFG successor!", MBB);
383 } else if (MBB->succ_begin()[0] != MBBI) {
384 report("MBB exits via unconditional fall-through but its successor "
385 "differs from its CFG successor!", MBB);
387 if (!MBB->empty() && MBB->back().getDesc().isBarrier() &&
388 !TII->isPredicated(&MBB->back())) {
389 report("MBB exits via unconditional fall-through but ends with a "
390 "barrier instruction!", MBB);
393 report("MBB exits via unconditional fall-through but has a condition!",
396 } else if (TBB && !FBB && Cond.empty()) {
397 // Block unconditionally branches somewhere.
398 if (MBB->succ_size() != 1) {
399 report("MBB exits via unconditional branch but doesn't have "
400 "exactly one CFG successor!", MBB);
401 } else if (MBB->succ_begin()[0] != TBB) {
402 report("MBB exits via unconditional branch but the CFG "
403 "successor doesn't match the actual successor!", MBB);
406 report("MBB exits via unconditional branch but doesn't contain "
407 "any instructions!", MBB);
408 } else if (!MBB->back().getDesc().isBarrier()) {
409 report("MBB exits via unconditional branch but doesn't end with a "
410 "barrier instruction!", MBB);
411 } else if (!MBB->back().getDesc().isTerminator()) {
412 report("MBB exits via unconditional branch but the branch isn't a "
413 "terminator instruction!", MBB);
415 } else if (TBB && !FBB && !Cond.empty()) {
416 // Block conditionally branches somewhere, otherwise falls through.
417 MachineFunction::const_iterator MBBI = MBB;
419 if (MBBI == MF->end()) {
420 report("MBB conditionally falls through out of function!", MBB);
421 } if (MBB->succ_size() != 2) {
422 report("MBB exits via conditional branch/fall-through but doesn't have "
423 "exactly two CFG successors!", MBB);
424 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
425 report("MBB exits via conditional branch/fall-through but the CFG "
426 "successors don't match the actual successors!", MBB);
429 report("MBB exits via conditional branch/fall-through but doesn't "
430 "contain any instructions!", MBB);
431 } else if (MBB->back().getDesc().isBarrier()) {
432 report("MBB exits via conditional branch/fall-through but ends with a "
433 "barrier instruction!", MBB);
434 } else if (!MBB->back().getDesc().isTerminator()) {
435 report("MBB exits via conditional branch/fall-through but the branch "
436 "isn't a terminator instruction!", MBB);
438 } else if (TBB && FBB) {
439 // Block conditionally branches somewhere, otherwise branches
441 if (MBB->succ_size() != 2) {
442 report("MBB exits via conditional branch/branch but doesn't have "
443 "exactly two CFG successors!", MBB);
444 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
445 report("MBB exits via conditional branch/branch but the CFG "
446 "successors don't match the actual successors!", MBB);
449 report("MBB exits via conditional branch/branch but doesn't "
450 "contain any instructions!", MBB);
451 } else if (!MBB->back().getDesc().isBarrier()) {
452 report("MBB exits via conditional branch/branch but doesn't end with a "
453 "barrier instruction!", MBB);
454 } else if (!MBB->back().getDesc().isTerminator()) {
455 report("MBB exits via conditional branch/branch but the branch "
456 "isn't a terminator instruction!", MBB);
459 report("MBB exits via conditinal branch/branch but there's no "
463 report("AnalyzeBranch returned invalid data!", MBB);
468 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
469 E = MBB->livein_end(); I != E; ++I) {
470 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
471 report("MBB live-in list contains non-physical register", MBB);
475 for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
478 regsLiveInButUnused = regsLive;
480 const MachineFrameInfo *MFI = MF->getFrameInfo();
481 assert(MFI && "Function has no frame info");
482 BitVector PR = MFI->getPristineRegs(MBB);
483 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
485 for (const unsigned *R = TRI->getSubRegisters(I); *R; R++)
493 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
494 const TargetInstrDesc &TI = MI->getDesc();
495 if (MI->getNumOperands() < TI.getNumOperands()) {
496 report("Too few operands", MI);
497 *OS << TI.getNumOperands() << " operands expected, but "
498 << MI->getNumExplicitOperands() << " given.\n";
501 // Check the MachineMemOperands for basic consistency.
502 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
503 E = MI->memoperands_end(); I != E; ++I) {
504 if ((*I)->isLoad() && !TI.mayLoad())
505 report("Missing mayLoad flag", MI);
506 if ((*I)->isStore() && !TI.mayStore())
507 report("Missing mayStore flag", MI);
510 // Debug values must not have a slot index.
511 // Other instructions must have one.
513 bool mapped = !LiveInts->isNotInMIMap(MI);
514 if (MI->isDebugValue()) {
516 report("Debug instruction has a slot index", MI);
519 report("Missing slot index", MI);
526 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
527 const MachineInstr *MI = MO->getParent();
528 const TargetInstrDesc &TI = MI->getDesc();
530 // The first TI.NumDefs operands must be explicit register defines
531 if (MONum < TI.getNumDefs()) {
533 report("Explicit definition must be a register", MO, MONum);
534 else if (!MO->isDef())
535 report("Explicit definition marked as use", MO, MONum);
536 else if (MO->isImplicit())
537 report("Explicit definition marked as implicit", MO, MONum);
538 } else if (MONum < TI.getNumOperands()) {
541 report("Explicit operand marked as def", MO, MONum);
542 if (MO->isImplicit())
543 report("Explicit operand marked as implicit", MO, MONum);
546 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
547 if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg())
548 report("Extra explicit operand on non-variadic instruction", MO, MONum);
551 switch (MO->getType()) {
552 case MachineOperand::MO_Register: {
553 const unsigned Reg = MO->getReg();
557 // Check Live Variables.
559 // An <undef> doesn't refer to any register, so just skip it.
560 } else if (MO->isUse()) {
561 regsLiveInButUnused.erase(Reg);
565 if (MI->isRegTiedToDefOperand(MONum, &defIdx)) {
566 // A two-addr use counts as a kill if use and def are the same.
567 unsigned DefReg = MI->getOperand(defIdx).getReg();
570 // ANd in that case an explicit kill flag is not allowed.
572 report("Illegal kill flag on two-address instruction operand",
574 } else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
575 report("Two-address instruction operands must be identical",
579 isKill = MO->isKill();
582 addRegWithSubRegs(regsKilled, Reg);
584 // Check that LiveVars knows this kill.
585 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
587 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
588 if (std::find(VI.Kills.begin(),
589 VI.Kills.end(), MI) == VI.Kills.end())
590 report("Kill missing from LiveVariables", MO, MONum);
593 // Check LiveInts liveness and kill.
594 if (LiveInts && !LiveInts->isNotInMIMap(MI)) {
595 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI).getUseIndex();
596 if (LiveInts->hasInterval(Reg)) {
597 const LiveInterval &LI = LiveInts->getInterval(Reg);
598 if (!LI.liveAt(UseIdx)) {
599 report("No live range at use", MO, MONum);
600 *OS << UseIdx << " is not live in " << LI << '\n';
602 // TODO: Verify isKill == LI.killedAt.
603 } else if (TargetRegisterInfo::isVirtualRegister(Reg)) {
604 report("Virtual register has no Live interval", MO, MONum);
608 // Use of a dead register.
609 if (!regsLive.count(Reg)) {
610 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
611 // Reserved registers may be used even when 'dead'.
612 if (!isReserved(Reg))
613 report("Using an undefined physical register", MO, MONum);
615 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
616 // We don't know which virtual registers are live in, so only complain
617 // if vreg was killed in this MBB. Otherwise keep track of vregs that
618 // must be live in. PHI instructions are handled separately.
619 if (MInfo.regsKilled.count(Reg))
620 report("Using a killed virtual register", MO, MONum);
621 else if (!MI->isPHI())
622 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
628 // TODO: verify that earlyclobber ops are not used.
630 addRegWithSubRegs(regsDead, Reg);
632 addRegWithSubRegs(regsDefined, Reg);
634 // Check LiveInts for a live range, but only for virtual registers.
635 if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
636 !LiveInts->isNotInMIMap(MI)) {
637 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI).getDefIndex();
638 if (LiveInts->hasInterval(Reg)) {
639 const LiveInterval &LI = LiveInts->getInterval(Reg);
640 if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx)) {
641 assert(LR->valno && "NULL valno is not allowed");
642 if (LR->valno->def != DefIdx) {
643 report("Inconsistent valno->def", MO, MONum);
644 *OS << "Valno " << LR->valno->id << " is not defined at "
645 << DefIdx << " in " << LI << '\n';
648 report("No live range at def", MO, MONum);
649 *OS << DefIdx << " is not live in " << LI << '\n';
652 report("Virtual register has no Live interval", MO, MONum);
657 // Check register classes.
658 if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
659 const TargetOperandInfo &TOI = TI.OpInfo[MONum];
660 unsigned SubIdx = MO->getSubReg();
662 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
665 unsigned s = TRI->getSubReg(Reg, SubIdx);
667 report("Invalid subregister index for physical register",
673 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
674 if (!DRC->contains(sr)) {
675 report("Illegal physical register for instruction", MO, MONum);
676 *OS << TRI->getName(sr) << " is not a "
677 << DRC->getName() << " register.\n";
682 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
684 const TargetRegisterClass *SRC = RC->getSubRegisterRegClass(SubIdx);
686 report("Invalid subregister index for virtual register", MO, MONum);
687 *OS << "Register class " << RC->getName()
688 << " does not support subreg index " << SubIdx << "\n";
693 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
694 if (RC != DRC && !RC->hasSuperClass(DRC)) {
695 report("Illegal virtual register for instruction", MO, MONum);
696 *OS << "Expected a " << DRC->getName() << " register, but got a "
697 << RC->getName() << " register\n";
705 case MachineOperand::MO_MachineBasicBlock:
706 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
707 report("PHI operand is not in the CFG", MO, MONum);
715 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
716 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
717 set_union(MInfo.regsKilled, regsKilled);
718 set_subtract(regsLive, regsKilled); regsKilled.clear();
719 set_subtract(regsLive, regsDead); regsDead.clear();
720 set_union(regsLive, regsDefined); regsDefined.clear();
724 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
725 MBBInfoMap[MBB].regsLiveOut = regsLive;
729 // Calculate the largest possible vregsPassed sets. These are the registers that
730 // can pass through an MBB live, but may not be live every time. It is assumed
731 // that all vregsPassed sets are empty before the call.
732 void MachineVerifier::calcRegsPassed() {
733 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
734 // have any vregsPassed.
735 DenseSet<const MachineBasicBlock*> todo;
736 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
738 const MachineBasicBlock &MBB(*MFI);
739 BBInfo &MInfo = MBBInfoMap[&MBB];
740 if (!MInfo.reachable)
742 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
743 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
744 BBInfo &SInfo = MBBInfoMap[*SuI];
745 if (SInfo.addPassed(MInfo.regsLiveOut))
750 // Iteratively push vregsPassed to successors. This will converge to the same
751 // final state regardless of DenseSet iteration order.
752 while (!todo.empty()) {
753 const MachineBasicBlock *MBB = *todo.begin();
755 BBInfo &MInfo = MBBInfoMap[MBB];
756 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
757 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
760 BBInfo &SInfo = MBBInfoMap[*SuI];
761 if (SInfo.addPassed(MInfo.vregsPassed))
767 // Calculate the set of virtual registers that must be passed through each basic
768 // block in order to satisfy the requirements of successor blocks. This is very
769 // similar to calcRegsPassed, only backwards.
770 void MachineVerifier::calcRegsRequired() {
771 // First push live-in regs to predecessors' vregsRequired.
772 DenseSet<const MachineBasicBlock*> todo;
773 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
775 const MachineBasicBlock &MBB(*MFI);
776 BBInfo &MInfo = MBBInfoMap[&MBB];
777 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
778 PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
779 BBInfo &PInfo = MBBInfoMap[*PrI];
780 if (PInfo.addRequired(MInfo.vregsLiveIn))
785 // Iteratively push vregsRequired to predecessors. This will converge to the
786 // same final state regardless of DenseSet iteration order.
787 while (!todo.empty()) {
788 const MachineBasicBlock *MBB = *todo.begin();
790 BBInfo &MInfo = MBBInfoMap[MBB];
791 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
792 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
795 BBInfo &SInfo = MBBInfoMap[*PrI];
796 if (SInfo.addRequired(MInfo.vregsRequired))
802 // Check PHI instructions at the beginning of MBB. It is assumed that
803 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
804 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
805 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
806 BBI != BBE && BBI->isPHI(); ++BBI) {
807 DenseSet<const MachineBasicBlock*> seen;
809 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
810 unsigned Reg = BBI->getOperand(i).getReg();
811 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
812 if (!Pre->isSuccessor(MBB))
815 BBInfo &PrInfo = MBBInfoMap[Pre];
816 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
817 report("PHI operand is not live-out from predecessor",
818 &BBI->getOperand(i), i);
821 // Did we see all predecessors?
822 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
823 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
824 if (!seen.count(*PrI)) {
825 report("Missing PHI operand", BBI);
826 *OS << "BB#" << (*PrI)->getNumber()
827 << " is a predecessor according to the CFG.\n";
833 void MachineVerifier::visitMachineFunctionAfter() {
836 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
838 BBInfo &MInfo = MBBInfoMap[MFI];
840 // Skip unreachable MBBs.
841 if (!MInfo.reachable)
847 // Now check liveness info if available
848 if (LiveVars || LiveInts)
851 verifyLiveVariables();
853 verifyLiveIntervals();
856 void MachineVerifier::verifyLiveVariables() {
857 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
858 for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister,
859 RegE = MRI->getLastVirtReg()-1; Reg != RegE; ++Reg) {
860 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
861 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
863 BBInfo &MInfo = MBBInfoMap[MFI];
865 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
866 if (MInfo.vregsRequired.count(Reg)) {
867 if (!VI.AliveBlocks.test(MFI->getNumber())) {
868 report("LiveVariables: Block missing from AliveBlocks", MFI);
869 *OS << "Virtual register %reg" << Reg
870 << " must be live through the block.\n";
873 if (VI.AliveBlocks.test(MFI->getNumber())) {
874 report("LiveVariables: Block should not be in AliveBlocks", MFI);
875 *OS << "Virtual register %reg" << Reg
876 << " is not needed live through the block.\n";
883 void MachineVerifier::verifyLiveIntervals() {
884 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
885 for (LiveIntervals::const_iterator LVI = LiveInts->begin(),
886 LVE = LiveInts->end(); LVI != LVE; ++LVI) {
887 const LiveInterval &LI = *LVI->second;
888 assert(LVI->first == LI.reg && "Invalid reg to interval mapping");
890 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
893 const LiveRange *DefLR = LI.getLiveRangeContaining(VNI->def);
896 if (!VNI->isUnused()) {
897 report("Valno not live at def and not marked unused", MF);
898 *OS << "Valno #" << VNI->id << " in " << LI << '\n';
906 if (DefLR->valno != VNI) {
907 report("Live range at def has different valno", MF);
909 *OS << " should use valno #" << VNI->id << " in " << LI << '\n';
914 for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I) {
915 const LiveRange &LR = *I;
916 assert(LR.valno && "Live range has no valno");
918 if (LR.valno->id >= LI.getNumValNums() ||
919 LR.valno != LI.getValNumInfo(LR.valno->id)) {
920 report("Foreign valno in live range", MF);
922 *OS << " has a valno not in " << LI << '\n';
925 if (LR.valno->isUnused()) {
926 report("Live range valno is marked unused", MF);
928 *OS << " in " << LI << '\n';