1 //===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/Instructions.h"
27 #include "llvm/Function.h"
28 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/LiveStackAnalysis.h"
31 #include "llvm/CodeGen/MachineInstrBundle.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineMemOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/ADT/DenseSet.h"
42 #include "llvm/ADT/SetOperations.h"
43 #include "llvm/ADT/SmallVector.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/raw_ostream.h"
50 struct MachineVerifier {
52 MachineVerifier(Pass *pass, const char *b) :
55 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
58 bool runOnMachineFunction(MachineFunction &MF);
62 const char *const OutFileName;
64 const MachineFunction *MF;
65 const TargetMachine *TM;
66 const TargetInstrInfo *TII;
67 const TargetRegisterInfo *TRI;
68 const MachineRegisterInfo *MRI;
72 typedef SmallVector<unsigned, 16> RegVector;
73 typedef SmallVector<const uint32_t*, 4> RegMaskVector;
74 typedef DenseSet<unsigned> RegSet;
75 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
77 const MachineInstr *FirstTerminator;
79 BitVector regsReserved;
80 BitVector regsAllocatable;
82 RegVector regsDefined, regsDead, regsKilled;
83 RegMaskVector regMasks;
84 RegSet regsLiveInButUnused;
88 // Add Reg and any sub-registers to RV
89 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
91 if (TargetRegisterInfo::isPhysicalRegister(Reg))
92 for (const uint16_t *R = TRI->getSubRegisters(Reg); *R; R++)
97 // Is this MBB reachable from the MF entry point?
100 // Vregs that must be live in because they are used without being
101 // defined. Map value is the user.
104 // Regs killed in MBB. They may be defined again, and will then be in both
105 // regsKilled and regsLiveOut.
108 // Regs defined in MBB and live out. Note that vregs passing through may
109 // be live out without being mentioned here.
112 // Vregs that pass through MBB untouched. This set is disjoint from
113 // regsKilled and regsLiveOut.
116 // Vregs that must pass through MBB because they are needed by a successor
117 // block. This set is disjoint from regsLiveOut.
118 RegSet vregsRequired;
120 BBInfo() : reachable(false) {}
122 // Add register to vregsPassed if it belongs there. Return true if
124 bool addPassed(unsigned Reg) {
125 if (!TargetRegisterInfo::isVirtualRegister(Reg))
127 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
129 return vregsPassed.insert(Reg).second;
132 // Same for a full set.
133 bool addPassed(const RegSet &RS) {
134 bool changed = false;
135 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
141 // Add register to vregsRequired if it belongs there. Return true if
143 bool addRequired(unsigned Reg) {
144 if (!TargetRegisterInfo::isVirtualRegister(Reg))
146 if (regsLiveOut.count(Reg))
148 return vregsRequired.insert(Reg).second;
151 // Same for a full set.
152 bool addRequired(const RegSet &RS) {
153 bool changed = false;
154 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
160 // Same for a full map.
161 bool addRequired(const RegMap &RM) {
162 bool changed = false;
163 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
164 if (addRequired(I->first))
169 // Live-out registers are either in regsLiveOut or vregsPassed.
170 bool isLiveOut(unsigned Reg) const {
171 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
175 // Extra register info per MBB.
176 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
178 bool isReserved(unsigned Reg) {
179 return Reg < regsReserved.size() && regsReserved.test(Reg);
182 bool isAllocatable(unsigned Reg) {
183 return Reg < regsAllocatable.size() && regsAllocatable.test(Reg);
186 // Analysis information if available
187 LiveVariables *LiveVars;
188 LiveIntervals *LiveInts;
189 LiveStacks *LiveStks;
190 SlotIndexes *Indexes;
192 void visitMachineFunctionBefore();
193 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
194 void visitMachineInstrBefore(const MachineInstr *MI);
195 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
196 void visitMachineInstrAfter(const MachineInstr *MI);
197 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
198 void visitMachineFunctionAfter();
200 void report(const char *msg, const MachineFunction *MF);
201 void report(const char *msg, const MachineBasicBlock *MBB);
202 void report(const char *msg, const MachineInstr *MI);
203 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
205 void checkLiveness(const MachineOperand *MO, unsigned MONum);
206 void markReachable(const MachineBasicBlock *MBB);
207 void calcRegsPassed();
208 void checkPHIOps(const MachineBasicBlock *MBB);
210 void calcRegsRequired();
211 void verifyLiveVariables();
212 void verifyLiveIntervals();
215 struct MachineVerifierPass : public MachineFunctionPass {
216 static char ID; // Pass ID, replacement for typeid
217 const char *const Banner;
219 MachineVerifierPass(const char *b = 0)
220 : MachineFunctionPass(ID), Banner(b) {
221 initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
224 void getAnalysisUsage(AnalysisUsage &AU) const {
225 AU.setPreservesAll();
226 MachineFunctionPass::getAnalysisUsage(AU);
229 bool runOnMachineFunction(MachineFunction &MF) {
230 MF.verify(this, Banner);
237 char MachineVerifierPass::ID = 0;
238 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
239 "Verify generated machine code", false, false)
241 FunctionPass *llvm::createMachineVerifierPass(const char *Banner) {
242 return new MachineVerifierPass(Banner);
245 void MachineFunction::verify(Pass *p, const char *Banner) const {
246 MachineVerifier(p, Banner)
247 .runOnMachineFunction(const_cast<MachineFunction&>(*this));
250 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
251 raw_ostream *OutFile = 0;
253 std::string ErrorInfo;
254 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
255 raw_fd_ostream::F_Append);
256 if (!ErrorInfo.empty()) {
257 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
269 TM = &MF.getTarget();
270 TII = TM->getInstrInfo();
271 TRI = TM->getRegisterInfo();
272 MRI = &MF.getRegInfo();
279 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
280 // We don't want to verify LiveVariables if LiveIntervals is available.
282 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
283 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
284 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
287 visitMachineFunctionBefore();
288 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
290 visitMachineBasicBlockBefore(MFI);
291 for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
292 MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
293 if (MBBI->getParent() != MFI) {
294 report("Bad instruction parent pointer", MFI);
295 *OS << "Instruction: " << *MBBI;
298 // Skip BUNDLE instruction for now. FIXME: We should add code to verify
299 // the BUNDLE's specifically.
300 if (MBBI->isBundle())
302 visitMachineInstrBefore(MBBI);
303 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
304 visitMachineOperand(&MBBI->getOperand(I), I);
305 visitMachineInstrAfter(MBBI);
307 visitMachineBasicBlockAfter(MFI);
309 visitMachineFunctionAfter();
313 else if (foundErrors)
314 report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
322 regsLiveInButUnused.clear();
325 return false; // no changes
328 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
331 if (!foundErrors++) {
333 *OS << "# " << Banner << '\n';
334 MF->print(*OS, Indexes);
336 *OS << "*** Bad machine code: " << msg << " ***\n"
337 << "- function: " << MF->getFunction()->getName() << "\n";
340 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
342 report(msg, MBB->getParent());
343 *OS << "- basic block: " << MBB->getName()
345 << " (BB#" << MBB->getNumber() << ")";
347 *OS << " [" << Indexes->getMBBStartIdx(MBB)
348 << ';' << Indexes->getMBBEndIdx(MBB) << ')';
352 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
354 report(msg, MI->getParent());
355 *OS << "- instruction: ";
356 if (Indexes && Indexes->hasIndex(MI))
357 *OS << Indexes->getInstructionIndex(MI) << '\t';
361 void MachineVerifier::report(const char *msg,
362 const MachineOperand *MO, unsigned MONum) {
364 report(msg, MO->getParent());
365 *OS << "- operand " << MONum << ": ";
370 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
371 BBInfo &MInfo = MBBInfoMap[MBB];
372 if (!MInfo.reachable) {
373 MInfo.reachable = true;
374 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
375 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
380 void MachineVerifier::visitMachineFunctionBefore() {
381 lastIndex = SlotIndex();
382 regsReserved = TRI->getReservedRegs(*MF);
384 // A sub-register of a reserved register is also reserved
385 for (int Reg = regsReserved.find_first(); Reg>=0;
386 Reg = regsReserved.find_next(Reg)) {
387 for (const uint16_t *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
388 // FIXME: This should probably be:
389 // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
390 regsReserved.set(*Sub);
394 regsAllocatable = TRI->getAllocatableSet(*MF);
396 markReachable(&MF->front());
399 // Does iterator point to a and b as the first two elements?
400 static bool matchPair(MachineBasicBlock::const_succ_iterator i,
401 const MachineBasicBlock *a, const MachineBasicBlock *b) {
410 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
414 // If this block has allocatable physical registers live-in, check that
415 // it is an entry block or landing pad.
416 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
417 LE = MBB->livein_end();
420 if (isAllocatable(reg) && !MBB->isLandingPad() &&
421 MBB != MBB->getParent()->begin()) {
422 report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
427 // Count the number of landing pad successors.
428 SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
429 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
430 E = MBB->succ_end(); I != E; ++I) {
431 if ((*I)->isLandingPad())
432 LandingPadSuccs.insert(*I);
435 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
436 const BasicBlock *BB = MBB->getBasicBlock();
437 if (LandingPadSuccs.size() > 1 &&
439 AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
440 BB && isa<SwitchInst>(BB->getTerminator())))
441 report("MBB has more than one landing pad successor", MBB);
443 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
444 MachineBasicBlock *TBB = 0, *FBB = 0;
445 SmallVector<MachineOperand, 4> Cond;
446 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
448 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
449 // check whether its answers match up with reality.
451 // Block falls through to its successor.
452 MachineFunction::const_iterator MBBI = MBB;
454 if (MBBI == MF->end()) {
455 // It's possible that the block legitimately ends with a noreturn
456 // call or an unreachable, in which case it won't actually fall
457 // out the bottom of the function.
458 } else if (MBB->succ_size() == LandingPadSuccs.size()) {
459 // It's possible that the block legitimately ends with a noreturn
460 // call or an unreachable, in which case it won't actuall fall
462 } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
463 report("MBB exits via unconditional fall-through but doesn't have "
464 "exactly one CFG successor!", MBB);
465 } else if (!MBB->isSuccessor(MBBI)) {
466 report("MBB exits via unconditional fall-through but its successor "
467 "differs from its CFG successor!", MBB);
469 if (!MBB->empty() && MBB->back().isBarrier() &&
470 !TII->isPredicated(&MBB->back())) {
471 report("MBB exits via unconditional fall-through but ends with a "
472 "barrier instruction!", MBB);
475 report("MBB exits via unconditional fall-through but has a condition!",
478 } else if (TBB && !FBB && Cond.empty()) {
479 // Block unconditionally branches somewhere.
480 if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
481 report("MBB exits via unconditional branch but doesn't have "
482 "exactly one CFG successor!", MBB);
483 } else if (!MBB->isSuccessor(TBB)) {
484 report("MBB exits via unconditional branch but the CFG "
485 "successor doesn't match the actual successor!", MBB);
488 report("MBB exits via unconditional branch but doesn't contain "
489 "any instructions!", MBB);
490 } else if (!MBB->back().isBarrier()) {
491 report("MBB exits via unconditional branch but doesn't end with a "
492 "barrier instruction!", MBB);
493 } else if (!MBB->back().isTerminator()) {
494 report("MBB exits via unconditional branch but the branch isn't a "
495 "terminator instruction!", MBB);
497 } else if (TBB && !FBB && !Cond.empty()) {
498 // Block conditionally branches somewhere, otherwise falls through.
499 MachineFunction::const_iterator MBBI = MBB;
501 if (MBBI == MF->end()) {
502 report("MBB conditionally falls through out of function!", MBB);
503 } if (MBB->succ_size() != 2) {
504 report("MBB exits via conditional branch/fall-through but doesn't have "
505 "exactly two CFG successors!", MBB);
506 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
507 report("MBB exits via conditional branch/fall-through but the CFG "
508 "successors don't match the actual successors!", MBB);
511 report("MBB exits via conditional branch/fall-through but doesn't "
512 "contain any instructions!", MBB);
513 } else if (MBB->back().isBarrier()) {
514 report("MBB exits via conditional branch/fall-through but ends with a "
515 "barrier instruction!", MBB);
516 } else if (!MBB->back().isTerminator()) {
517 report("MBB exits via conditional branch/fall-through but the branch "
518 "isn't a terminator instruction!", MBB);
520 } else if (TBB && FBB) {
521 // Block conditionally branches somewhere, otherwise branches
523 if (MBB->succ_size() != 2) {
524 report("MBB exits via conditional branch/branch but doesn't have "
525 "exactly two CFG successors!", MBB);
526 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
527 report("MBB exits via conditional branch/branch but the CFG "
528 "successors don't match the actual successors!", MBB);
531 report("MBB exits via conditional branch/branch but doesn't "
532 "contain any instructions!", MBB);
533 } else if (!MBB->back().isBarrier()) {
534 report("MBB exits via conditional branch/branch but doesn't end with a "
535 "barrier instruction!", MBB);
536 } else if (!MBB->back().isTerminator()) {
537 report("MBB exits via conditional branch/branch but the branch "
538 "isn't a terminator instruction!", MBB);
541 report("MBB exits via conditinal branch/branch but there's no "
545 report("AnalyzeBranch returned invalid data!", MBB);
550 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
551 E = MBB->livein_end(); I != E; ++I) {
552 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
553 report("MBB live-in list contains non-physical register", MBB);
557 for (const uint16_t *R = TRI->getSubRegisters(*I); *R; R++)
560 regsLiveInButUnused = regsLive;
562 const MachineFrameInfo *MFI = MF->getFrameInfo();
563 assert(MFI && "Function has no frame info");
564 BitVector PR = MFI->getPristineRegs(MBB);
565 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
567 for (const uint16_t *R = TRI->getSubRegisters(I); *R; R++)
575 lastIndex = Indexes->getMBBStartIdx(MBB);
578 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
579 const MCInstrDesc &MCID = MI->getDesc();
580 if (MI->getNumOperands() < MCID.getNumOperands()) {
581 report("Too few operands", MI);
582 *OS << MCID.getNumOperands() << " operands expected, but "
583 << MI->getNumExplicitOperands() << " given.\n";
586 // Check the MachineMemOperands for basic consistency.
587 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
588 E = MI->memoperands_end(); I != E; ++I) {
589 if ((*I)->isLoad() && !MI->mayLoad())
590 report("Missing mayLoad flag", MI);
591 if ((*I)->isStore() && !MI->mayStore())
592 report("Missing mayStore flag", MI);
595 // Debug values must not have a slot index.
596 // Other instructions must have one, unless they are inside a bundle.
598 bool mapped = !LiveInts->isNotInMIMap(MI);
599 if (MI->isDebugValue()) {
601 report("Debug instruction has a slot index", MI);
602 } else if (MI->isInsideBundle()) {
604 report("Instruction inside bundle has a slot index", MI);
607 report("Missing slot index", MI);
611 // Ensure non-terminators don't follow terminators.
612 // Ignore predicated terminators formed by if conversion.
613 // FIXME: If conversion shouldn't need to violate this rule.
614 if (MI->isTerminator() && !TII->isPredicated(MI)) {
615 if (!FirstTerminator)
616 FirstTerminator = MI;
617 } else if (FirstTerminator) {
618 report("Non-terminator instruction after the first terminator", MI);
619 *OS << "First terminator was:\t" << *FirstTerminator;
623 if (!TII->verifyInstruction(MI, ErrorInfo))
624 report(ErrorInfo.data(), MI);
628 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
629 const MachineInstr *MI = MO->getParent();
630 const MCInstrDesc &MCID = MI->getDesc();
631 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
633 // The first MCID.NumDefs operands must be explicit register defines
634 if (MONum < MCID.getNumDefs()) {
636 report("Explicit definition must be a register", MO, MONum);
637 else if (!MO->isDef())
638 report("Explicit definition marked as use", MO, MONum);
639 else if (MO->isImplicit())
640 report("Explicit definition marked as implicit", MO, MONum);
641 } else if (MONum < MCID.getNumOperands()) {
642 // Don't check if it's the last operand in a variadic instruction. See,
643 // e.g., LDM_RET in the arm back end.
645 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
646 if (MO->isDef() && !MCOI.isOptionalDef())
647 report("Explicit operand marked as def", MO, MONum);
648 if (MO->isImplicit())
649 report("Explicit operand marked as implicit", MO, MONum);
652 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
653 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
654 report("Extra explicit operand on non-variadic instruction", MO, MONum);
657 switch (MO->getType()) {
658 case MachineOperand::MO_Register: {
659 const unsigned Reg = MO->getReg();
662 if (MRI->tracksLiveness() && !MI->isDebugValue())
663 checkLiveness(MO, MONum);
666 // Check register classes.
667 if (MONum < MCID.getNumOperands() && !MO->isImplicit()) {
668 unsigned SubIdx = MO->getSubReg();
670 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
672 report("Illegal subregister index for physical register", MO, MONum);
675 if (const TargetRegisterClass *DRC =
676 TII->getRegClass(MCID, MONum, TRI, *MF)) {
677 if (!DRC->contains(Reg)) {
678 report("Illegal physical register for instruction", MO, MONum);
679 *OS << TRI->getName(Reg) << " is not a "
680 << DRC->getName() << " register.\n";
685 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
687 const TargetRegisterClass *SRC =
688 TRI->getSubClassWithSubReg(RC, SubIdx);
690 report("Invalid subregister index for virtual register", MO, MONum);
691 *OS << "Register class " << RC->getName()
692 << " does not support subreg index " << SubIdx << "\n";
696 report("Invalid register class for subregister index", MO, MONum);
697 *OS << "Register class " << RC->getName()
698 << " does not fully support subreg index " << SubIdx << "\n";
702 if (const TargetRegisterClass *DRC =
703 TII->getRegClass(MCID, MONum, TRI, *MF)) {
705 const TargetRegisterClass *SuperRC =
706 TRI->getLargestLegalSuperClass(RC);
708 report("No largest legal super class exists.", MO, MONum);
711 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
713 report("No matching super-reg register class.", MO, MONum);
717 if (!RC->hasSuperClassEq(DRC)) {
718 report("Illegal virtual register for instruction", MO, MONum);
719 *OS << "Expected a " << DRC->getName() << " register, but got a "
720 << RC->getName() << " register\n";
728 case MachineOperand::MO_RegisterMask:
729 regMasks.push_back(MO->getRegMask());
732 case MachineOperand::MO_MachineBasicBlock:
733 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
734 report("PHI operand is not in the CFG", MO, MONum);
737 case MachineOperand::MO_FrameIndex:
738 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
739 LiveInts && !LiveInts->isNotInMIMap(MI)) {
740 LiveInterval &LI = LiveStks->getInterval(MO->getIndex());
741 SlotIndex Idx = LiveInts->getInstructionIndex(MI);
742 if (MI->mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) {
743 report("Instruction loads from dead spill slot", MO, MONum);
744 *OS << "Live stack: " << LI << '\n';
746 if (MI->mayStore() && !LI.liveAt(Idx.getRegSlot())) {
747 report("Instruction stores to dead spill slot", MO, MONum);
748 *OS << "Live stack: " << LI << '\n';
758 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
759 const MachineInstr *MI = MO->getParent();
760 const unsigned Reg = MO->getReg();
762 // Both use and def operands can read a register.
763 if (MO->readsReg()) {
764 regsLiveInButUnused.erase(Reg);
768 if (MI->isRegTiedToDefOperand(MONum, &defIdx)) {
769 // A two-addr use counts as a kill if use and def are the same.
770 unsigned DefReg = MI->getOperand(defIdx).getReg();
773 else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
774 report("Two-address instruction operands must be identical", MO, MONum);
777 isKill = MO->isKill();
780 addRegWithSubRegs(regsKilled, Reg);
782 // Check that LiveVars knows this kill.
783 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
785 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
786 if (std::find(VI.Kills.begin(), VI.Kills.end(), MI) == VI.Kills.end())
787 report("Kill missing from LiveVariables", MO, MONum);
790 // Check LiveInts liveness and kill.
791 if (TargetRegisterInfo::isVirtualRegister(Reg) &&
792 LiveInts && !LiveInts->isNotInMIMap(MI)) {
793 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI).getRegSlot(true);
794 if (LiveInts->hasInterval(Reg)) {
795 const LiveInterval &LI = LiveInts->getInterval(Reg);
796 if (!LI.liveAt(UseIdx)) {
797 report("No live range at use", MO, MONum);
798 *OS << UseIdx << " is not live in " << LI << '\n';
800 // Check for extra kill flags.
801 // Note that we allow missing kill flags for now.
802 if (MO->isKill() && !LI.killedAt(UseIdx.getRegSlot())) {
803 report("Live range continues after kill flag", MO, MONum);
804 *OS << "Live range: " << LI << '\n';
807 report("Virtual register has no Live interval", MO, MONum);
811 // Use of a dead register.
812 if (!regsLive.count(Reg)) {
813 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
814 // Reserved registers may be used even when 'dead'.
815 if (!isReserved(Reg))
816 report("Using an undefined physical register", MO, MONum);
818 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
819 // We don't know which virtual registers are live in, so only complain
820 // if vreg was killed in this MBB. Otherwise keep track of vregs that
821 // must be live in. PHI instructions are handled separately.
822 if (MInfo.regsKilled.count(Reg))
823 report("Using a killed virtual register", MO, MONum);
824 else if (!MI->isPHI())
825 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
832 // TODO: verify that earlyclobber ops are not used.
834 addRegWithSubRegs(regsDead, Reg);
836 addRegWithSubRegs(regsDefined, Reg);
839 if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
840 llvm::next(MRI->def_begin(Reg)) != MRI->def_end())
841 report("Multiple virtual register defs in SSA form", MO, MONum);
843 // Check LiveInts for a live range, but only for virtual registers.
844 if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
845 !LiveInts->isNotInMIMap(MI)) {
846 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI).getRegSlot();
847 if (LiveInts->hasInterval(Reg)) {
848 const LiveInterval &LI = LiveInts->getInterval(Reg);
849 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
850 assert(VNI && "NULL valno is not allowed");
851 if (VNI->def != DefIdx && !MO->isEarlyClobber()) {
852 report("Inconsistent valno->def", MO, MONum);
853 *OS << "Valno " << VNI->id << " is not defined at "
854 << DefIdx << " in " << LI << '\n';
857 report("No live range at def", MO, MONum);
858 *OS << DefIdx << " is not live in " << LI << '\n';
861 report("Virtual register has no Live interval", MO, MONum);
867 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
868 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
869 set_union(MInfo.regsKilled, regsKilled);
870 set_subtract(regsLive, regsKilled); regsKilled.clear();
871 // Kill any masked registers.
872 while (!regMasks.empty()) {
873 const uint32_t *Mask = regMasks.pop_back_val();
874 for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
875 if (TargetRegisterInfo::isPhysicalRegister(*I) &&
876 MachineOperand::clobbersPhysReg(Mask, *I))
877 regsDead.push_back(*I);
879 set_subtract(regsLive, regsDead); regsDead.clear();
880 set_union(regsLive, regsDefined); regsDefined.clear();
882 if (Indexes && Indexes->hasIndex(MI)) {
883 SlotIndex idx = Indexes->getInstructionIndex(MI);
884 if (!(idx > lastIndex)) {
885 report("Instruction index out of order", MI);
886 *OS << "Last instruction was at " << lastIndex << '\n';
893 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
894 MBBInfoMap[MBB].regsLiveOut = regsLive;
898 SlotIndex stop = Indexes->getMBBEndIdx(MBB);
899 if (!(stop > lastIndex)) {
900 report("Block ends before last instruction index", MBB);
901 *OS << "Block ends at " << stop
902 << " last instruction was at " << lastIndex << '\n';
908 // Calculate the largest possible vregsPassed sets. These are the registers that
909 // can pass through an MBB live, but may not be live every time. It is assumed
910 // that all vregsPassed sets are empty before the call.
911 void MachineVerifier::calcRegsPassed() {
912 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
913 // have any vregsPassed.
914 SmallPtrSet<const MachineBasicBlock*, 8> todo;
915 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
917 const MachineBasicBlock &MBB(*MFI);
918 BBInfo &MInfo = MBBInfoMap[&MBB];
919 if (!MInfo.reachable)
921 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
922 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
923 BBInfo &SInfo = MBBInfoMap[*SuI];
924 if (SInfo.addPassed(MInfo.regsLiveOut))
929 // Iteratively push vregsPassed to successors. This will converge to the same
930 // final state regardless of DenseSet iteration order.
931 while (!todo.empty()) {
932 const MachineBasicBlock *MBB = *todo.begin();
934 BBInfo &MInfo = MBBInfoMap[MBB];
935 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
936 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
939 BBInfo &SInfo = MBBInfoMap[*SuI];
940 if (SInfo.addPassed(MInfo.vregsPassed))
946 // Calculate the set of virtual registers that must be passed through each basic
947 // block in order to satisfy the requirements of successor blocks. This is very
948 // similar to calcRegsPassed, only backwards.
949 void MachineVerifier::calcRegsRequired() {
950 // First push live-in regs to predecessors' vregsRequired.
951 SmallPtrSet<const MachineBasicBlock*, 8> todo;
952 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
954 const MachineBasicBlock &MBB(*MFI);
955 BBInfo &MInfo = MBBInfoMap[&MBB];
956 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
957 PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
958 BBInfo &PInfo = MBBInfoMap[*PrI];
959 if (PInfo.addRequired(MInfo.vregsLiveIn))
964 // Iteratively push vregsRequired to predecessors. This will converge to the
965 // same final state regardless of DenseSet iteration order.
966 while (!todo.empty()) {
967 const MachineBasicBlock *MBB = *todo.begin();
969 BBInfo &MInfo = MBBInfoMap[MBB];
970 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
971 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
974 BBInfo &SInfo = MBBInfoMap[*PrI];
975 if (SInfo.addRequired(MInfo.vregsRequired))
981 // Check PHI instructions at the beginning of MBB. It is assumed that
982 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
983 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
984 SmallPtrSet<const MachineBasicBlock*, 8> seen;
985 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
986 BBI != BBE && BBI->isPHI(); ++BBI) {
989 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
990 unsigned Reg = BBI->getOperand(i).getReg();
991 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
992 if (!Pre->isSuccessor(MBB))
995 BBInfo &PrInfo = MBBInfoMap[Pre];
996 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
997 report("PHI operand is not live-out from predecessor",
998 &BBI->getOperand(i), i);
1001 // Did we see all predecessors?
1002 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1003 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1004 if (!seen.count(*PrI)) {
1005 report("Missing PHI operand", BBI);
1006 *OS << "BB#" << (*PrI)->getNumber()
1007 << " is a predecessor according to the CFG.\n";
1013 void MachineVerifier::visitMachineFunctionAfter() {
1016 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1017 MFI != MFE; ++MFI) {
1018 BBInfo &MInfo = MBBInfoMap[MFI];
1020 // Skip unreachable MBBs.
1021 if (!MInfo.reachable)
1027 // Now check liveness info if available
1030 if (MRI->isSSA() && !MF->empty()) {
1031 BBInfo &MInfo = MBBInfoMap[&MF->front()];
1032 for (RegSet::iterator
1033 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1035 report("Virtual register def doesn't dominate all uses.",
1036 MRI->getVRegDef(*I));
1040 verifyLiveVariables();
1042 verifyLiveIntervals();
1045 void MachineVerifier::verifyLiveVariables() {
1046 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
1047 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1048 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1049 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1050 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1051 MFI != MFE; ++MFI) {
1052 BBInfo &MInfo = MBBInfoMap[MFI];
1054 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
1055 if (MInfo.vregsRequired.count(Reg)) {
1056 if (!VI.AliveBlocks.test(MFI->getNumber())) {
1057 report("LiveVariables: Block missing from AliveBlocks", MFI);
1058 *OS << "Virtual register " << PrintReg(Reg)
1059 << " must be live through the block.\n";
1062 if (VI.AliveBlocks.test(MFI->getNumber())) {
1063 report("LiveVariables: Block should not be in AliveBlocks", MFI);
1064 *OS << "Virtual register " << PrintReg(Reg)
1065 << " is not needed live through the block.\n";
1072 void MachineVerifier::verifyLiveIntervals() {
1073 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
1074 for (LiveIntervals::const_iterator LVI = LiveInts->begin(),
1075 LVE = LiveInts->end(); LVI != LVE; ++LVI) {
1076 const LiveInterval &LI = *LVI->second;
1078 // Spilling and splitting may leave unused registers around. Skip them.
1079 if (MRI->reg_nodbg_empty(LI.reg))
1082 // Physical registers have much weirdness going on, mostly from coalescing.
1083 // We should probably fix it, but for now just ignore them.
1084 if (TargetRegisterInfo::isPhysicalRegister(LI.reg))
1087 assert(LVI->first == LI.reg && "Invalid reg to interval mapping");
1089 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
1092 const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def);
1095 if (!VNI->isUnused()) {
1096 report("Valno not live at def and not marked unused", MF);
1097 *OS << "Valno #" << VNI->id << " in " << LI << '\n';
1102 if (VNI->isUnused())
1105 if (DefVNI != VNI) {
1106 report("Live range at def has different valno", MF);
1107 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1108 << " where valno #" << DefVNI->id << " is live in " << LI << '\n';
1112 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
1114 report("Invalid definition index", MF);
1115 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1116 << " in " << LI << '\n';
1120 if (VNI->isPHIDef()) {
1121 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
1122 report("PHIDef value is not defined at MBB start", MF);
1123 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1124 << ", not at the beginning of BB#" << MBB->getNumber()
1125 << " in " << LI << '\n';
1129 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
1131 report("No instruction at def index", MF);
1132 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1133 << " in " << LI << '\n';
1137 bool hasDef = false;
1138 bool isEarlyClobber = false;
1139 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1140 if (!MOI->isReg() || !MOI->isDef())
1142 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1143 if (MOI->getReg() != LI.reg)
1146 if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
1147 !TRI->regsOverlap(LI.reg, MOI->getReg()))
1151 if (MOI->isEarlyClobber())
1152 isEarlyClobber = true;
1156 report("Defining instruction does not modify register", MI);
1157 *OS << "Valno #" << VNI->id << " in " << LI << '\n';
1160 // Early clobber defs begin at USE slots, but other defs must begin at
1162 if (isEarlyClobber) {
1163 if (!VNI->def.isEarlyClobber()) {
1164 report("Early clobber def must be at an early-clobber slot", MF);
1165 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1166 << " in " << LI << '\n';
1168 } else if (!VNI->def.isRegister()) {
1169 report("Non-PHI, non-early clobber def must be at a register slot",
1171 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1172 << " in " << LI << '\n';
1177 for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I) {
1178 const VNInfo *VNI = I->valno;
1179 assert(VNI && "Live range has no valno");
1181 if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) {
1182 report("Foreign valno in live range", MF);
1184 *OS << " has a valno not in " << LI << '\n';
1187 if (VNI->isUnused()) {
1188 report("Live range valno is marked unused", MF);
1190 *OS << " in " << LI << '\n';
1193 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(I->start);
1195 report("Bad start of live segment, no basic block", MF);
1197 *OS << " in " << LI << '\n';
1200 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
1201 if (I->start != MBBStartIdx && I->start != VNI->def) {
1202 report("Live segment must begin at MBB entry or valno def", MBB);
1204 *OS << " in " << LI << '\n' << "Basic block starts at "
1205 << MBBStartIdx << '\n';
1208 const MachineBasicBlock *EndMBB =
1209 LiveInts->getMBBFromIndex(I->end.getPrevSlot());
1211 report("Bad end of live segment, no basic block", MF);
1213 *OS << " in " << LI << '\n';
1217 // No more checks for live-out segments.
1218 if (I->end == LiveInts->getMBBEndIdx(EndMBB))
1221 // The live segment is ending inside EndMBB
1222 const MachineInstr *MI =
1223 LiveInts->getInstructionFromIndex(I->end.getPrevSlot());
1225 report("Live segment doesn't end at a valid instruction", EndMBB);
1227 *OS << " in " << LI << '\n' << "Basic block starts at "
1228 << MBBStartIdx << '\n';
1232 // The block slot must refer to a basic block boundary.
1233 if (I->end.isBlock()) {
1234 report("Live segment ends at B slot of an instruction", MI);
1236 *OS << " in " << LI << '\n';
1239 if (I->end.isDead()) {
1240 // Segment ends on the dead slot.
1241 // That means there must be a dead def.
1242 if (!SlotIndex::isSameInstr(I->start, I->end)) {
1243 report("Live segment ending at dead slot spans instructions", MI);
1245 *OS << " in " << LI << '\n';
1249 // A live segment can only end at an early-clobber slot if it is being
1250 // redefined by an early-clobber def.
1251 if (I->end.isEarlyClobber()) {
1252 if (I+1 == E || (I+1)->start != I->end) {
1253 report("Live segment ending at early clobber slot must be "
1254 "redefined by an EC def in the same instruction", MI);
1256 *OS << " in " << LI << '\n';
1260 // The following checks only apply to virtual registers. Physreg liveness
1261 // is too weird to check.
1262 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1263 // A live range can end with either a redefinition, a kill flag on a
1264 // use, or a dead flag on a def.
1265 bool hasRead = false;
1266 bool hasDeadDef = false;
1267 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1268 if (!MOI->isReg() || MOI->getReg() != LI.reg)
1270 if (MOI->readsReg())
1272 if (MOI->isDef() && MOI->isDead())
1276 if (I->end.isDead()) {
1278 report("Instruction doesn't have a dead def operand", MI);
1280 *OS << " in " << LI << '\n';
1284 report("Instruction ending live range doesn't read the register",
1287 *OS << " in " << LI << '\n';
1292 // Now check all the basic blocks in this live segment.
1293 MachineFunction::const_iterator MFI = MBB;
1294 // Is this live range the beginning of a non-PHIDef VN?
1295 if (I->start == VNI->def && !VNI->isPHIDef()) {
1296 // Not live-in to any blocks.
1303 assert(LiveInts->isLiveInToMBB(LI, MFI));
1304 // We don't know how to track physregs into a landing pad.
1305 if (TargetRegisterInfo::isPhysicalRegister(LI.reg) &&
1306 MFI->isLandingPad()) {
1307 if (&*MFI == EndMBB)
1312 // Check that VNI is live-out of all predecessors.
1313 for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
1314 PE = MFI->pred_end(); PI != PE; ++PI) {
1315 SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
1316 const VNInfo *PVNI = LI.getVNInfoBefore(PEnd);
1318 if (VNI->isPHIDef() && VNI->def == LiveInts->getMBBStartIdx(MFI))
1322 report("Register not marked live out of predecessor", *PI);
1323 *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
1324 << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before "
1325 << PEnd << " in " << LI << '\n';
1330 report("Different value live out of predecessor", *PI);
1331 *OS << "Valno #" << PVNI->id << " live out of BB#"
1332 << (*PI)->getNumber() << '@' << PEnd
1333 << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
1334 << '@' << LiveInts->getMBBStartIdx(MFI) << " in " << LI << '\n';
1337 if (&*MFI == EndMBB)
1343 // Check the LI only has one connected component.
1344 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1345 ConnectedVNInfoEqClasses ConEQ(*LiveInts);
1346 unsigned NumComp = ConEQ.Classify(&LI);
1348 report("Multiple connected components in live interval", MF);
1349 *OS << NumComp << " components in " << LI << '\n';
1350 for (unsigned comp = 0; comp != NumComp; ++comp) {
1351 *OS << comp << ": valnos";
1352 for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
1353 E = LI.vni_end(); I!=E; ++I)
1354 if (comp == ConEQ.getEqClass(*I))
1355 *OS << ' ' << (*I)->id;