1 //===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/Function.h"
27 #include "llvm/CodeGen/LiveVariables.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/ADT/DenseSet.h"
37 #include "llvm/ADT/SetOperations.h"
38 #include "llvm/ADT/SmallVector.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/raw_ostream.h"
45 struct MachineVerifier {
47 MachineVerifier(Pass *pass, bool allowDoubleDefs) :
49 allowVirtDoubleDefs(allowDoubleDefs),
50 allowPhysDoubleDefs(allowDoubleDefs),
51 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
54 bool runOnMachineFunction(MachineFunction &MF);
57 const bool allowVirtDoubleDefs;
58 const bool allowPhysDoubleDefs;
60 const char *const OutFileName;
62 const MachineFunction *MF;
63 const TargetMachine *TM;
64 const TargetRegisterInfo *TRI;
65 const MachineRegisterInfo *MRI;
69 typedef SmallVector<unsigned, 16> RegVector;
70 typedef DenseSet<unsigned> RegSet;
71 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
73 BitVector regsReserved;
75 RegVector regsDefined, regsDead, regsKilled;
76 RegSet regsLiveInButUnused;
78 // Add Reg and any sub-registers to RV
79 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
81 if (TargetRegisterInfo::isPhysicalRegister(Reg))
82 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
87 // Is this MBB reachable from the MF entry point?
90 // Vregs that must be live in because they are used without being
91 // defined. Map value is the user.
94 // Vregs that must be dead in because they are defined without being
95 // killed first. Map value is the defining instruction.
98 // Regs killed in MBB. They may be defined again, and will then be in both
99 // regsKilled and regsLiveOut.
102 // Regs defined in MBB and live out. Note that vregs passing through may
103 // be live out without being mentioned here.
106 // Vregs that pass through MBB untouched. This set is disjoint from
107 // regsKilled and regsLiveOut.
110 // Vregs that must pass through MBB because they are needed by a successor
111 // block. This set is disjoint from regsLiveOut.
112 RegSet vregsRequired;
114 BBInfo() : reachable(false) {}
116 // Add register to vregsPassed if it belongs there. Return true if
118 bool addPassed(unsigned Reg) {
119 if (!TargetRegisterInfo::isVirtualRegister(Reg))
121 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
123 return vregsPassed.insert(Reg).second;
126 // Same for a full set.
127 bool addPassed(const RegSet &RS) {
128 bool changed = false;
129 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
135 // Add register to vregsRequired if it belongs there. Return true if
137 bool addRequired(unsigned Reg) {
138 if (!TargetRegisterInfo::isVirtualRegister(Reg))
140 if (regsLiveOut.count(Reg))
142 return vregsRequired.insert(Reg).second;
145 // Same for a full set.
146 bool addRequired(const RegSet &RS) {
147 bool changed = false;
148 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
154 // Same for a full map.
155 bool addRequired(const RegMap &RM) {
156 bool changed = false;
157 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
158 if (addRequired(I->first))
163 // Live-out registers are either in regsLiveOut or vregsPassed.
164 bool isLiveOut(unsigned Reg) const {
165 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
169 // Extra register info per MBB.
170 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
172 bool isReserved(unsigned Reg) {
173 return Reg < regsReserved.size() && regsReserved.test(Reg);
176 // Analysis information if available
177 LiveVariables *LiveVars;
179 void visitMachineFunctionBefore();
180 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
181 void visitMachineInstrBefore(const MachineInstr *MI);
182 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
183 void visitMachineInstrAfter(const MachineInstr *MI);
184 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
185 void visitMachineFunctionAfter();
187 void report(const char *msg, const MachineFunction *MF);
188 void report(const char *msg, const MachineBasicBlock *MBB);
189 void report(const char *msg, const MachineInstr *MI);
190 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
192 void markReachable(const MachineBasicBlock *MBB);
193 void calcMaxRegsPassed();
194 void calcMinRegsPassed();
195 void checkPHIOps(const MachineBasicBlock *MBB);
197 void calcRegsRequired();
198 void verifyLiveVariables();
201 struct MachineVerifierPass : public MachineFunctionPass {
202 static char ID; // Pass ID, replacement for typeid
203 bool AllowDoubleDefs;
205 explicit MachineVerifierPass(bool allowDoubleDefs = false)
206 : MachineFunctionPass(&ID),
207 AllowDoubleDefs(allowDoubleDefs) {}
209 void getAnalysisUsage(AnalysisUsage &AU) const {
210 AU.setPreservesAll();
211 MachineFunctionPass::getAnalysisUsage(AU);
214 bool runOnMachineFunction(MachineFunction &MF) {
215 MF.verify(this, AllowDoubleDefs);
222 char MachineVerifierPass::ID = 0;
223 static RegisterPass<MachineVerifierPass>
224 MachineVer("machineverifier", "Verify generated machine code");
225 static const PassInfo *const MachineVerifyID = &MachineVer;
227 FunctionPass *llvm::createMachineVerifierPass(bool allowPhysDoubleDefs) {
228 return new MachineVerifierPass(allowPhysDoubleDefs);
231 void MachineFunction::verify(Pass *p, bool allowDoubleDefs) const {
232 MachineVerifier(p, allowDoubleDefs)
233 .runOnMachineFunction(const_cast<MachineFunction&>(*this));
236 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
237 raw_ostream *OutFile = 0;
239 std::string ErrorInfo;
240 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
241 raw_fd_ostream::F_Append);
242 if (!ErrorInfo.empty()) {
243 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
255 TM = &MF.getTarget();
256 TRI = TM->getRegisterInfo();
257 MRI = &MF.getRegInfo();
260 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
265 visitMachineFunctionBefore();
266 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
268 visitMachineBasicBlockBefore(MFI);
269 for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
270 MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
271 visitMachineInstrBefore(MBBI);
272 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
273 visitMachineOperand(&MBBI->getOperand(I), I);
274 visitMachineInstrAfter(MBBI);
276 visitMachineBasicBlockAfter(MFI);
278 visitMachineFunctionAfter();
282 else if (foundErrors)
283 llvm_report_error("Found "+Twine(foundErrors)+" machine code errors.");
290 regsLiveInButUnused.clear();
293 return false; // no changes
296 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
301 *OS << "*** Bad machine code: " << msg << " ***\n"
302 << "- function: " << MF->getFunction()->getNameStr() << "\n";
305 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
307 report(msg, MBB->getParent());
308 *OS << "- basic block: " << MBB->getName()
310 << " (BB#" << MBB->getNumber() << ")\n";
313 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
315 report(msg, MI->getParent());
316 *OS << "- instruction: ";
320 void MachineVerifier::report(const char *msg,
321 const MachineOperand *MO, unsigned MONum) {
323 report(msg, MO->getParent());
324 *OS << "- operand " << MONum << ": ";
329 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
330 BBInfo &MInfo = MBBInfoMap[MBB];
331 if (!MInfo.reachable) {
332 MInfo.reachable = true;
333 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
334 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
339 void MachineVerifier::visitMachineFunctionBefore() {
340 regsReserved = TRI->getReservedRegs(*MF);
342 // A sub-register of a reserved register is also reserved
343 for (int Reg = regsReserved.find_first(); Reg>=0;
344 Reg = regsReserved.find_next(Reg)) {
345 for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
346 // FIXME: This should probably be:
347 // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
348 regsReserved.set(*Sub);
351 markReachable(&MF->front());
354 // Does iterator point to a and b as the first two elements?
355 bool matchPair(MachineBasicBlock::const_succ_iterator i,
356 const MachineBasicBlock *a, const MachineBasicBlock *b) {
365 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
366 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
368 // Start with minimal CFG sanity checks.
369 MachineFunction::const_iterator MBBI = MBB;
371 if (MBBI != MF->end()) {
372 // Block is not last in function.
373 if (!MBB->isSuccessor(MBBI)) {
374 // Block does not fall through.
376 report("MBB doesn't fall through but is empty!", MBB);
379 if (TII->BlockHasNoFallThrough(*MBB)) {
381 report("TargetInstrInfo says the block has no fall through, but the "
382 "block is empty!", MBB);
383 } else if (!MBB->back().getDesc().isBarrier()) {
384 report("TargetInstrInfo says the block has no fall through, but the "
385 "block does not end in a barrier!", MBB);
389 // Block is last in function.
391 report("MBB is last in function but is empty!", MBB);
395 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
396 MachineBasicBlock *TBB = 0, *FBB = 0;
397 SmallVector<MachineOperand, 4> Cond;
398 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
400 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
401 // check whether its answers match up with reality.
403 // Block falls through to its successor.
404 MachineFunction::const_iterator MBBI = MBB;
406 if (MBBI == MF->end()) {
407 // It's possible that the block legitimately ends with a noreturn
408 // call or an unreachable, in which case it won't actually fall
409 // out the bottom of the function.
410 } else if (MBB->succ_empty()) {
411 // It's possible that the block legitimately ends with a noreturn
412 // call or an unreachable, in which case it won't actuall fall
414 } else if (MBB->succ_size() != 1) {
415 report("MBB exits via unconditional fall-through but doesn't have "
416 "exactly one CFG successor!", MBB);
417 } else if (MBB->succ_begin()[0] != MBBI) {
418 report("MBB exits via unconditional fall-through but its successor "
419 "differs from its CFG successor!", MBB);
421 if (!MBB->empty() && MBB->back().getDesc().isBarrier()) {
422 report("MBB exits via unconditional fall-through but ends with a "
423 "barrier instruction!", MBB);
426 report("MBB exits via unconditional fall-through but has a condition!",
429 } else if (TBB && !FBB && Cond.empty()) {
430 // Block unconditionally branches somewhere.
431 if (MBB->succ_size() != 1) {
432 report("MBB exits via unconditional branch but doesn't have "
433 "exactly one CFG successor!", MBB);
434 } else if (MBB->succ_begin()[0] != TBB) {
435 report("MBB exits via unconditional branch but the CFG "
436 "successor doesn't match the actual successor!", MBB);
439 report("MBB exits via unconditional branch but doesn't contain "
440 "any instructions!", MBB);
441 } else if (!MBB->back().getDesc().isBarrier()) {
442 report("MBB exits via unconditional branch but doesn't end with a "
443 "barrier instruction!", MBB);
444 } else if (!MBB->back().getDesc().isTerminator()) {
445 report("MBB exits via unconditional branch but the branch isn't a "
446 "terminator instruction!", MBB);
448 } else if (TBB && !FBB && !Cond.empty()) {
449 // Block conditionally branches somewhere, otherwise falls through.
450 MachineFunction::const_iterator MBBI = MBB;
452 if (MBBI == MF->end()) {
453 report("MBB conditionally falls through out of function!", MBB);
454 } if (MBB->succ_size() != 2) {
455 report("MBB exits via conditional branch/fall-through but doesn't have "
456 "exactly two CFG successors!", MBB);
457 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
458 report("MBB exits via conditional branch/fall-through but the CFG "
459 "successors don't match the actual successors!", MBB);
462 report("MBB exits via conditional branch/fall-through but doesn't "
463 "contain any instructions!", MBB);
464 } else if (MBB->back().getDesc().isBarrier()) {
465 report("MBB exits via conditional branch/fall-through but ends with a "
466 "barrier instruction!", MBB);
467 } else if (!MBB->back().getDesc().isTerminator()) {
468 report("MBB exits via conditional branch/fall-through but the branch "
469 "isn't a terminator instruction!", MBB);
471 } else if (TBB && FBB) {
472 // Block conditionally branches somewhere, otherwise branches
474 if (MBB->succ_size() != 2) {
475 report("MBB exits via conditional branch/branch but doesn't have "
476 "exactly two CFG successors!", MBB);
477 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
478 report("MBB exits via conditional branch/branch but the CFG "
479 "successors don't match the actual successors!", MBB);
482 report("MBB exits via conditional branch/branch but doesn't "
483 "contain any instructions!", MBB);
484 } else if (!MBB->back().getDesc().isBarrier()) {
485 report("MBB exits via conditional branch/branch but doesn't end with a "
486 "barrier instruction!", MBB);
487 } else if (!MBB->back().getDesc().isTerminator()) {
488 report("MBB exits via conditional branch/branch but the branch "
489 "isn't a terminator instruction!", MBB);
492 report("MBB exits via conditinal branch/branch but there's no "
496 report("AnalyzeBranch returned invalid data!", MBB);
501 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
502 E = MBB->livein_end(); I != E; ++I) {
503 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
504 report("MBB live-in list contains non-physical register", MBB);
508 for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
511 regsLiveInButUnused = regsLive;
513 const MachineFrameInfo *MFI = MF->getFrameInfo();
514 assert(MFI && "Function has no frame info");
515 BitVector PR = MFI->getPristineRegs(MBB);
516 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
518 for (const unsigned *R = TRI->getSubRegisters(I); *R; R++)
526 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
527 const TargetInstrDesc &TI = MI->getDesc();
528 if (MI->getNumOperands() < TI.getNumOperands()) {
529 report("Too few operands", MI);
530 *OS << TI.getNumOperands() << " operands expected, but "
531 << MI->getNumExplicitOperands() << " given.\n";
534 // Check the MachineMemOperands for basic consistency.
535 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
536 E = MI->memoperands_end(); I != E; ++I) {
537 if ((*I)->isLoad() && !TI.mayLoad())
538 report("Missing mayLoad flag", MI);
539 if ((*I)->isStore() && !TI.mayStore())
540 report("Missing mayStore flag", MI);
545 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
546 const MachineInstr *MI = MO->getParent();
547 const TargetInstrDesc &TI = MI->getDesc();
549 // The first TI.NumDefs operands must be explicit register defines
550 if (MONum < TI.getNumDefs()) {
552 report("Explicit definition must be a register", MO, MONum);
553 else if (!MO->isDef())
554 report("Explicit definition marked as use", MO, MONum);
555 else if (MO->isImplicit())
556 report("Explicit definition marked as implicit", MO, MONum);
557 } else if (MONum < TI.getNumOperands()) {
560 report("Explicit operand marked as def", MO, MONum);
561 if (MO->isImplicit())
562 report("Explicit operand marked as implicit", MO, MONum);
565 if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic())
566 report("Extra explicit operand on non-variadic instruction", MO, MONum);
569 switch (MO->getType()) {
570 case MachineOperand::MO_Register: {
571 const unsigned Reg = MO->getReg();
575 // Check Live Variables.
577 // An <undef> doesn't refer to any register, so just skip it.
578 } else if (MO->isUse()) {
579 regsLiveInButUnused.erase(Reg);
584 // Tied operands on two-address instuctions MUST NOT have a <kill> flag.
585 if (MI->isRegTiedToDefOperand(MONum))
586 report("Illegal kill flag on two-address instruction operand",
589 // TwoAddress instr modifying a reg is treated as kill+def.
591 if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
592 MI->getOperand(defIdx).getReg() == Reg)
596 addRegWithSubRegs(regsKilled, Reg);
598 // Check that LiveVars knows this kill
599 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg)) {
600 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
601 if (std::find(VI.Kills.begin(),
602 VI.Kills.end(), MI) == VI.Kills.end())
603 report("Kill missing from LiveVariables", MO, MONum);
607 // Use of a dead register.
608 if (!regsLive.count(Reg)) {
609 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
610 // Reserved registers may be used even when 'dead'.
611 if (!isReserved(Reg))
612 report("Using an undefined physical register", MO, MONum);
614 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
615 // We don't know which virtual registers are live in, so only complain
616 // if vreg was killed in this MBB. Otherwise keep track of vregs that
617 // must be live in. PHI instructions are handled separately.
618 if (MInfo.regsKilled.count(Reg))
619 report("Using a killed virtual register", MO, MONum);
620 else if (MI->getOpcode() != TargetInstrInfo::PHI)
621 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
627 // TODO: verify that earlyclobber ops are not used.
629 addRegWithSubRegs(regsDead, Reg);
631 addRegWithSubRegs(regsDefined, Reg);
634 // Check register classes.
635 if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
636 const TargetOperandInfo &TOI = TI.OpInfo[MONum];
637 unsigned SubIdx = MO->getSubReg();
639 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
642 unsigned s = TRI->getSubReg(Reg, SubIdx);
644 report("Invalid subregister index for physical register",
650 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
651 if (!DRC->contains(sr)) {
652 report("Illegal physical register for instruction", MO, MONum);
653 *OS << TRI->getName(sr) << " is not a "
654 << DRC->getName() << " register.\n";
659 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
661 if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) {
662 report("Invalid subregister index for virtual register", MO, MONum);
665 RC = *(RC->subregclasses_begin()+SubIdx);
667 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
668 if (RC != DRC && !RC->hasSuperClass(DRC)) {
669 report("Illegal virtual register for instruction", MO, MONum);
670 *OS << "Expected a " << DRC->getName() << " register, but got a "
671 << RC->getName() << " register\n";
679 case MachineOperand::MO_MachineBasicBlock:
680 if (MI->getOpcode() == TargetInstrInfo::PHI) {
681 if (!MO->getMBB()->isSuccessor(MI->getParent()))
682 report("PHI operand is not in the CFG", MO, MONum);
691 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
692 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
693 set_union(MInfo.regsKilled, regsKilled);
694 set_subtract(regsLive, regsKilled);
697 // Verify that both <def> and <def,dead> operands refer to dead registers.
698 RegVector defs(regsDefined);
699 defs.append(regsDead.begin(), regsDead.end());
701 for (RegVector::const_iterator I = defs.begin(), E = defs.end();
703 if (regsLive.count(*I)) {
704 if (TargetRegisterInfo::isPhysicalRegister(*I)) {
705 if (!allowPhysDoubleDefs && !isReserved(*I) &&
706 !regsLiveInButUnused.count(*I)) {
707 report("Redefining a live physical register", MI);
708 *OS << "Register " << TRI->getName(*I)
709 << " was defined but already live.\n";
712 if (!allowVirtDoubleDefs) {
713 report("Redefining a live virtual register", MI);
714 *OS << "Virtual register %reg" << *I
715 << " was defined but already live.\n";
718 } else if (TargetRegisterInfo::isVirtualRegister(*I) &&
719 !MInfo.regsKilled.count(*I)) {
720 // Virtual register defined without being killed first must be dead on
722 MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
726 set_subtract(regsLive, regsDead); regsDead.clear();
727 set_union(regsLive, regsDefined); regsDefined.clear();
731 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
732 MBBInfoMap[MBB].regsLiveOut = regsLive;
736 // Calculate the largest possible vregsPassed sets. These are the registers that
737 // can pass through an MBB live, but may not be live every time. It is assumed
738 // that all vregsPassed sets are empty before the call.
739 void MachineVerifier::calcMaxRegsPassed() {
740 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
741 // have any vregsPassed.
742 DenseSet<const MachineBasicBlock*> todo;
743 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
745 const MachineBasicBlock &MBB(*MFI);
746 BBInfo &MInfo = MBBInfoMap[&MBB];
747 if (!MInfo.reachable)
749 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
750 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
751 BBInfo &SInfo = MBBInfoMap[*SuI];
752 if (SInfo.addPassed(MInfo.regsLiveOut))
757 // Iteratively push vregsPassed to successors. This will converge to the same
758 // final state regardless of DenseSet iteration order.
759 while (!todo.empty()) {
760 const MachineBasicBlock *MBB = *todo.begin();
762 BBInfo &MInfo = MBBInfoMap[MBB];
763 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
764 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
767 BBInfo &SInfo = MBBInfoMap[*SuI];
768 if (SInfo.addPassed(MInfo.vregsPassed))
774 // Calculate the minimum vregsPassed set. These are the registers that always
775 // pass live through an MBB. The calculation assumes that calcMaxRegsPassed has
776 // been called earlier.
777 void MachineVerifier::calcMinRegsPassed() {
778 DenseSet<const MachineBasicBlock*> todo;
779 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
783 while (!todo.empty()) {
784 const MachineBasicBlock *MBB = *todo.begin();
786 BBInfo &MInfo = MBBInfoMap[MBB];
788 // Remove entries from vRegsPassed that are not live out from all
789 // reachable predecessors.
791 for (RegSet::iterator I = MInfo.vregsPassed.begin(),
792 E = MInfo.vregsPassed.end(); I != E; ++I) {
793 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
794 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
795 BBInfo &PrInfo = MBBInfoMap[*PrI];
796 if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) {
802 // If any regs removed, we need to recheck successors.
804 set_subtract(MInfo.vregsPassed, dead);
805 todo.insert(MBB->succ_begin(), MBB->succ_end());
810 // Calculate the set of virtual registers that must be passed through each basic
811 // block in order to satisfy the requirements of successor blocks. This is very
812 // similar to calcMaxRegsPassed, only backwards.
813 void MachineVerifier::calcRegsRequired() {
814 // First push live-in regs to predecessors' vregsRequired.
815 DenseSet<const MachineBasicBlock*> todo;
816 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
818 const MachineBasicBlock &MBB(*MFI);
819 BBInfo &MInfo = MBBInfoMap[&MBB];
820 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
821 PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
822 BBInfo &PInfo = MBBInfoMap[*PrI];
823 if (PInfo.addRequired(MInfo.vregsLiveIn))
828 // Iteratively push vregsRequired to predecessors. This will converge to the
829 // same final state regardless of DenseSet iteration order.
830 while (!todo.empty()) {
831 const MachineBasicBlock *MBB = *todo.begin();
833 BBInfo &MInfo = MBBInfoMap[MBB];
834 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
835 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
838 BBInfo &SInfo = MBBInfoMap[*PrI];
839 if (SInfo.addRequired(MInfo.vregsRequired))
845 // Check PHI instructions at the beginning of MBB. It is assumed that
846 // calcMinRegsPassed has been run so BBInfo::isLiveOut is valid.
847 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
848 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
849 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
850 DenseSet<const MachineBasicBlock*> seen;
852 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
853 unsigned Reg = BBI->getOperand(i).getReg();
854 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
855 if (!Pre->isSuccessor(MBB))
858 BBInfo &PrInfo = MBBInfoMap[Pre];
859 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
860 report("PHI operand is not live-out from predecessor",
861 &BBI->getOperand(i), i);
864 // Did we see all predecessors?
865 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
866 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
867 if (!seen.count(*PrI)) {
868 report("Missing PHI operand", BBI);
869 *OS << "BB#" << (*PrI)->getNumber()
870 << " is a predecessor according to the CFG.\n";
876 void MachineVerifier::visitMachineFunctionAfter() {
879 // With the maximal set of vregsPassed we can verify dead-in registers.
880 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
882 BBInfo &MInfo = MBBInfoMap[MFI];
884 // Skip unreachable MBBs.
885 if (!MInfo.reachable)
888 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
889 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
890 BBInfo &PrInfo = MBBInfoMap[*PrI];
891 if (!PrInfo.reachable)
894 // Verify physical live-ins. EH landing pads have magic live-ins so we
896 if (!MFI->isLandingPad()) {
897 for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(),
898 E = MFI->livein_end(); I != E; ++I) {
899 if (TargetRegisterInfo::isPhysicalRegister(*I) &&
900 !isReserved (*I) && !PrInfo.isLiveOut(*I)) {
901 report("Live-in physical register is not live-out from predecessor",
903 *OS << "Register " << TRI->getName(*I)
904 << " is not live-out from BB#" << (*PrI)->getNumber()
911 // Verify dead-in virtual registers.
912 if (!allowVirtDoubleDefs) {
913 for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
914 E = MInfo.vregsDeadIn.end(); I != E; ++I) {
915 // DeadIn register must be in neither regsLiveOut or vregsPassed of
917 if (PrInfo.isLiveOut(I->first)) {
918 report("Live-in virtual register redefined", I->second);
919 *OS << "Register %reg" << I->first
920 << " was live-out from predecessor MBB #"
921 << (*PrI)->getNumber() << ".\n";
930 // With the minimal set of vregsPassed we can verify live-in virtual
931 // registers, including PHI instructions.
932 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
934 BBInfo &MInfo = MBBInfoMap[MFI];
936 // Skip unreachable MBBs.
937 if (!MInfo.reachable)
942 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
943 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
944 BBInfo &PrInfo = MBBInfoMap[*PrI];
945 if (!PrInfo.reachable)
948 for (RegMap::iterator I = MInfo.vregsLiveIn.begin(),
949 E = MInfo.vregsLiveIn.end(); I != E; ++I) {
950 if (!PrInfo.isLiveOut(I->first)) {
951 report("Used virtual register is not live-in", I->second);
952 *OS << "Register %reg" << I->first
953 << " is not live-out from predecessor MBB #"
954 << (*PrI)->getNumber()
961 // Now check LiveVariables info if available
964 verifyLiveVariables();
968 void MachineVerifier::verifyLiveVariables() {
969 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
970 for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister,
971 RegE = MRI->getLastVirtReg()-1; Reg != RegE; ++Reg) {
972 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
973 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
975 BBInfo &MInfo = MBBInfoMap[MFI];
977 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
978 if (MInfo.vregsRequired.count(Reg)) {
979 if (!VI.AliveBlocks.test(MFI->getNumber())) {
980 report("LiveVariables: Block missing from AliveBlocks", MFI);
981 *OS << "Virtual register %reg" << Reg
982 << " must be live through the block.\n";
985 if (VI.AliveBlocks.test(MFI->getNumber())) {
986 report("LiveVariables: Block should not be in AliveBlocks", MFI);
987 *OS << "Virtual register %reg" << Reg
988 << " is not needed live through the block.\n";