1 //===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/ADT/DenseSet.h"
28 #include "llvm/ADT/DepthFirstIterator.h"
29 #include "llvm/ADT/SetOperations.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
32 #include "llvm/CodeGen/LiveStackAnalysis.h"
33 #include "llvm/CodeGen/LiveVariables.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineFunctionPass.h"
36 #include "llvm/CodeGen/MachineMemOperand.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/IR/BasicBlock.h"
39 #include "llvm/IR/InlineAsm.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/MC/MCAsmInfo.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/FileSystem.h"
45 #include "llvm/Support/Format.h"
46 #include "llvm/Support/raw_ostream.h"
47 #include "llvm/Target/TargetInstrInfo.h"
48 #include "llvm/Target/TargetMachine.h"
49 #include "llvm/Target/TargetRegisterInfo.h"
50 #include "llvm/Target/TargetSubtargetInfo.h"
54 struct MachineVerifier {
56 MachineVerifier(Pass *pass, const char *b) :
61 bool runOnMachineFunction(MachineFunction &MF);
65 const MachineFunction *MF;
66 const TargetMachine *TM;
67 const TargetInstrInfo *TII;
68 const TargetRegisterInfo *TRI;
69 const MachineRegisterInfo *MRI;
73 typedef SmallVector<unsigned, 16> RegVector;
74 typedef SmallVector<const uint32_t*, 4> RegMaskVector;
75 typedef DenseSet<unsigned> RegSet;
76 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
77 typedef SmallPtrSet<const MachineBasicBlock*, 8> BlockSet;
79 const MachineInstr *FirstTerminator;
80 BlockSet FunctionBlocks;
82 BitVector regsReserved;
84 RegVector regsDefined, regsDead, regsKilled;
85 RegMaskVector regMasks;
86 RegSet regsLiveInButUnused;
90 // Add Reg and any sub-registers to RV
91 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
93 if (TargetRegisterInfo::isPhysicalRegister(Reg))
94 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
95 RV.push_back(*SubRegs);
99 // Is this MBB reachable from the MF entry point?
102 // Vregs that must be live in because they are used without being
103 // defined. Map value is the user.
106 // Regs killed in MBB. They may be defined again, and will then be in both
107 // regsKilled and regsLiveOut.
110 // Regs defined in MBB and live out. Note that vregs passing through may
111 // be live out without being mentioned here.
114 // Vregs that pass through MBB untouched. This set is disjoint from
115 // regsKilled and regsLiveOut.
118 // Vregs that must pass through MBB because they are needed by a successor
119 // block. This set is disjoint from regsLiveOut.
120 RegSet vregsRequired;
122 // Set versions of block's predecessor and successor lists.
123 BlockSet Preds, Succs;
125 BBInfo() : reachable(false) {}
127 // Add register to vregsPassed if it belongs there. Return true if
129 bool addPassed(unsigned Reg) {
130 if (!TargetRegisterInfo::isVirtualRegister(Reg))
132 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
134 return vregsPassed.insert(Reg).second;
137 // Same for a full set.
138 bool addPassed(const RegSet &RS) {
139 bool changed = false;
140 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
146 // Add register to vregsRequired if it belongs there. Return true if
148 bool addRequired(unsigned Reg) {
149 if (!TargetRegisterInfo::isVirtualRegister(Reg))
151 if (regsLiveOut.count(Reg))
153 return vregsRequired.insert(Reg).second;
156 // Same for a full set.
157 bool addRequired(const RegSet &RS) {
158 bool changed = false;
159 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
165 // Same for a full map.
166 bool addRequired(const RegMap &RM) {
167 bool changed = false;
168 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
169 if (addRequired(I->first))
174 // Live-out registers are either in regsLiveOut or vregsPassed.
175 bool isLiveOut(unsigned Reg) const {
176 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
180 // Extra register info per MBB.
181 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
183 bool isReserved(unsigned Reg) {
184 return Reg < regsReserved.size() && regsReserved.test(Reg);
187 bool isAllocatable(unsigned Reg) {
188 return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg);
191 // Analysis information if available
192 LiveVariables *LiveVars;
193 LiveIntervals *LiveInts;
194 LiveStacks *LiveStks;
195 SlotIndexes *Indexes;
197 void visitMachineFunctionBefore();
198 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
199 void visitMachineBundleBefore(const MachineInstr *MI);
200 void visitMachineInstrBefore(const MachineInstr *MI);
201 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
202 void visitMachineInstrAfter(const MachineInstr *MI);
203 void visitMachineBundleAfter(const MachineInstr *MI);
204 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
205 void visitMachineFunctionAfter();
207 void report(const char *msg, const MachineFunction *MF);
208 void report(const char *msg, const MachineBasicBlock *MBB);
209 void report(const char *msg, const MachineInstr *MI);
210 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
211 void report(const char *msg, const MachineFunction *MF,
212 const LiveInterval &LI);
213 void report(const char *msg, const MachineBasicBlock *MBB,
214 const LiveInterval &LI);
215 void report(const char *msg, const MachineFunction *MF,
216 const LiveRange &LR, unsigned Reg, unsigned LaneMask);
217 void report(const char *msg, const MachineBasicBlock *MBB,
218 const LiveRange &LR, unsigned Reg, unsigned LaneMask);
220 void verifyInlineAsm(const MachineInstr *MI);
222 void checkLiveness(const MachineOperand *MO, unsigned MONum);
223 void markReachable(const MachineBasicBlock *MBB);
224 void calcRegsPassed();
225 void checkPHIOps(const MachineBasicBlock *MBB);
227 void calcRegsRequired();
228 void verifyLiveVariables();
229 void verifyLiveIntervals();
230 void verifyLiveInterval(const LiveInterval&);
231 void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned,
233 void verifyLiveRangeSegment(const LiveRange&,
234 const LiveRange::const_iterator I, unsigned,
236 void verifyLiveRange(const LiveRange&, unsigned, unsigned LaneMask = 0);
238 void verifyStackFrame();
241 struct MachineVerifierPass : public MachineFunctionPass {
242 static char ID; // Pass ID, replacement for typeid
243 const std::string Banner;
245 MachineVerifierPass(const std::string &banner = nullptr)
246 : MachineFunctionPass(ID), Banner(banner) {
247 initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
250 void getAnalysisUsage(AnalysisUsage &AU) const override {
251 AU.setPreservesAll();
252 MachineFunctionPass::getAnalysisUsage(AU);
255 bool runOnMachineFunction(MachineFunction &MF) override {
256 MF.verify(this, Banner.c_str());
263 char MachineVerifierPass::ID = 0;
264 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
265 "Verify generated machine code", false, false)
267 FunctionPass *llvm::createMachineVerifierPass(const std::string &Banner) {
268 return new MachineVerifierPass(Banner);
271 void MachineFunction::verify(Pass *p, const char *Banner) const {
272 MachineVerifier(p, Banner)
273 .runOnMachineFunction(const_cast<MachineFunction&>(*this));
276 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
280 TM = &MF.getTarget();
281 TII = MF.getSubtarget().getInstrInfo();
282 TRI = MF.getSubtarget().getRegisterInfo();
283 MRI = &MF.getRegInfo();
290 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
291 // We don't want to verify LiveVariables if LiveIntervals is available.
293 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
294 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
295 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
298 visitMachineFunctionBefore();
299 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
301 visitMachineBasicBlockBefore(MFI);
302 // Keep track of the current bundle header.
303 const MachineInstr *CurBundle = nullptr;
304 // Do we expect the next instruction to be part of the same bundle?
305 bool InBundle = false;
307 for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
308 MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
309 if (MBBI->getParent() != MFI) {
310 report("Bad instruction parent pointer", MFI);
311 errs() << "Instruction: " << *MBBI;
315 // Check for consistent bundle flags.
316 if (InBundle && !MBBI->isBundledWithPred())
317 report("Missing BundledPred flag, "
318 "BundledSucc was set on predecessor", MBBI);
319 if (!InBundle && MBBI->isBundledWithPred())
320 report("BundledPred flag is set, "
321 "but BundledSucc not set on predecessor", MBBI);
323 // Is this a bundle header?
324 if (!MBBI->isInsideBundle()) {
326 visitMachineBundleAfter(CurBundle);
328 visitMachineBundleBefore(CurBundle);
329 } else if (!CurBundle)
330 report("No bundle header", MBBI);
331 visitMachineInstrBefore(MBBI);
332 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
333 const MachineInstr &MI = *MBBI;
334 const MachineOperand &Op = MI.getOperand(I);
335 if (Op.getParent() != &MI) {
336 // Make sure to use correct addOperand / RemoveOperand / ChangeTo
337 // functions when replacing operands of a MachineInstr.
338 report("Instruction has operand with wrong parent set", &MI);
341 visitMachineOperand(&Op, I);
344 visitMachineInstrAfter(MBBI);
346 // Was this the last bundled instruction?
347 InBundle = MBBI->isBundledWithSucc();
350 visitMachineBundleAfter(CurBundle);
352 report("BundledSucc flag set on last instruction in block", &MFI->back());
353 visitMachineBasicBlockAfter(MFI);
355 visitMachineFunctionAfter();
358 report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
366 regsLiveInButUnused.clear();
369 return false; // no changes
372 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
375 if (!foundErrors++) {
377 errs() << "# " << Banner << '\n';
378 MF->print(errs(), Indexes);
380 errs() << "*** Bad machine code: " << msg << " ***\n"
381 << "- function: " << MF->getName() << "\n";
384 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
386 report(msg, MBB->getParent());
387 errs() << "- basic block: BB#" << MBB->getNumber()
388 << ' ' << MBB->getName()
389 << " (" << (const void*)MBB << ')';
391 errs() << " [" << Indexes->getMBBStartIdx(MBB)
392 << ';' << Indexes->getMBBEndIdx(MBB) << ')';
396 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
398 report(msg, MI->getParent());
399 errs() << "- instruction: ";
400 if (Indexes && Indexes->hasIndex(MI))
401 errs() << Indexes->getInstructionIndex(MI) << '\t';
402 MI->print(errs(), TM);
405 void MachineVerifier::report(const char *msg,
406 const MachineOperand *MO, unsigned MONum) {
408 report(msg, MO->getParent());
409 errs() << "- operand " << MONum << ": ";
410 MO->print(errs(), TRI);
414 void MachineVerifier::report(const char *msg, const MachineFunction *MF,
415 const LiveInterval &LI) {
417 errs() << "- interval: " << LI << '\n';
420 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
421 const LiveInterval &LI) {
423 errs() << "- interval: " << LI << '\n';
426 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
427 const LiveRange &LR, unsigned Reg,
430 errs() << "- liverange: " << LR << '\n';
431 errs() << "- register: " << PrintReg(Reg, TRI) << '\n';
433 errs() << "- lanemask: " << format("%04X\n", LaneMask);
436 void MachineVerifier::report(const char *msg, const MachineFunction *MF,
437 const LiveRange &LR, unsigned Reg,
440 errs() << "- liverange: " << LR << '\n';
441 errs() << "- register: " << PrintReg(Reg, TRI) << '\n';
443 errs() << "- lanemask: " << format("%04X\n", LaneMask);
446 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
447 BBInfo &MInfo = MBBInfoMap[MBB];
448 if (!MInfo.reachable) {
449 MInfo.reachable = true;
450 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
451 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
456 void MachineVerifier::visitMachineFunctionBefore() {
457 lastIndex = SlotIndex();
458 regsReserved = MRI->getReservedRegs();
460 // A sub-register of a reserved register is also reserved
461 for (int Reg = regsReserved.find_first(); Reg>=0;
462 Reg = regsReserved.find_next(Reg)) {
463 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
464 // FIXME: This should probably be:
465 // assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register");
466 regsReserved.set(*SubRegs);
470 markReachable(&MF->front());
472 // Build a set of the basic blocks in the function.
473 FunctionBlocks.clear();
474 for (const auto &MBB : *MF) {
475 FunctionBlocks.insert(&MBB);
476 BBInfo &MInfo = MBBInfoMap[&MBB];
478 MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
479 if (MInfo.Preds.size() != MBB.pred_size())
480 report("MBB has duplicate entries in its predecessor list.", &MBB);
482 MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
483 if (MInfo.Succs.size() != MBB.succ_size())
484 report("MBB has duplicate entries in its successor list.", &MBB);
487 // Check that the register use lists are sane.
488 MRI->verifyUseLists();
493 // Does iterator point to a and b as the first two elements?
494 static bool matchPair(MachineBasicBlock::const_succ_iterator i,
495 const MachineBasicBlock *a, const MachineBasicBlock *b) {
504 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
505 FirstTerminator = nullptr;
508 // If this block has allocatable physical registers live-in, check that
509 // it is an entry block or landing pad.
510 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
511 LE = MBB->livein_end();
514 if (isAllocatable(reg) && !MBB->isLandingPad() &&
515 MBB != MBB->getParent()->begin()) {
516 report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
521 // Count the number of landing pad successors.
522 SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
523 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
524 E = MBB->succ_end(); I != E; ++I) {
525 if ((*I)->isLandingPad())
526 LandingPadSuccs.insert(*I);
527 if (!FunctionBlocks.count(*I))
528 report("MBB has successor that isn't part of the function.", MBB);
529 if (!MBBInfoMap[*I].Preds.count(MBB)) {
530 report("Inconsistent CFG", MBB);
531 errs() << "MBB is not in the predecessor list of the successor BB#"
532 << (*I)->getNumber() << ".\n";
536 // Check the predecessor list.
537 for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
538 E = MBB->pred_end(); I != E; ++I) {
539 if (!FunctionBlocks.count(*I))
540 report("MBB has predecessor that isn't part of the function.", MBB);
541 if (!MBBInfoMap[*I].Succs.count(MBB)) {
542 report("Inconsistent CFG", MBB);
543 errs() << "MBB is not in the successor list of the predecessor BB#"
544 << (*I)->getNumber() << ".\n";
548 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
549 const BasicBlock *BB = MBB->getBasicBlock();
550 if (LandingPadSuccs.size() > 1 &&
552 AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
553 BB && isa<SwitchInst>(BB->getTerminator())))
554 report("MBB has more than one landing pad successor", MBB);
556 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
557 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
558 SmallVector<MachineOperand, 4> Cond;
559 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
561 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
562 // check whether its answers match up with reality.
564 // Block falls through to its successor.
565 MachineFunction::const_iterator MBBI = MBB;
567 if (MBBI == MF->end()) {
568 // It's possible that the block legitimately ends with a noreturn
569 // call or an unreachable, in which case it won't actually fall
570 // out the bottom of the function.
571 } else if (MBB->succ_size() == LandingPadSuccs.size()) {
572 // It's possible that the block legitimately ends with a noreturn
573 // call or an unreachable, in which case it won't actuall fall
575 } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
576 report("MBB exits via unconditional fall-through but doesn't have "
577 "exactly one CFG successor!", MBB);
578 } else if (!MBB->isSuccessor(MBBI)) {
579 report("MBB exits via unconditional fall-through but its successor "
580 "differs from its CFG successor!", MBB);
582 if (!MBB->empty() && MBB->back().isBarrier() &&
583 !TII->isPredicated(&MBB->back())) {
584 report("MBB exits via unconditional fall-through but ends with a "
585 "barrier instruction!", MBB);
588 report("MBB exits via unconditional fall-through but has a condition!",
591 } else if (TBB && !FBB && Cond.empty()) {
592 // Block unconditionally branches somewhere.
593 // If the block has exactly one successor, that happens to be a
594 // landingpad, accept it as valid control flow.
595 if (MBB->succ_size() != 1+LandingPadSuccs.size() &&
596 (MBB->succ_size() != 1 || LandingPadSuccs.size() != 1 ||
597 *MBB->succ_begin() != *LandingPadSuccs.begin())) {
598 report("MBB exits via unconditional branch but doesn't have "
599 "exactly one CFG successor!", MBB);
600 } else if (!MBB->isSuccessor(TBB)) {
601 report("MBB exits via unconditional branch but the CFG "
602 "successor doesn't match the actual successor!", MBB);
605 report("MBB exits via unconditional branch but doesn't contain "
606 "any instructions!", MBB);
607 } else if (!MBB->back().isBarrier()) {
608 report("MBB exits via unconditional branch but doesn't end with a "
609 "barrier instruction!", MBB);
610 } else if (!MBB->back().isTerminator()) {
611 report("MBB exits via unconditional branch but the branch isn't a "
612 "terminator instruction!", MBB);
614 } else if (TBB && !FBB && !Cond.empty()) {
615 // Block conditionally branches somewhere, otherwise falls through.
616 MachineFunction::const_iterator MBBI = MBB;
618 if (MBBI == MF->end()) {
619 report("MBB conditionally falls through out of function!", MBB);
620 } else if (MBB->succ_size() == 1) {
621 // A conditional branch with only one successor is weird, but allowed.
623 report("MBB exits via conditional branch/fall-through but only has "
624 "one CFG successor!", MBB);
625 else if (TBB != *MBB->succ_begin())
626 report("MBB exits via conditional branch/fall-through but the CFG "
627 "successor don't match the actual successor!", MBB);
628 } else if (MBB->succ_size() != 2) {
629 report("MBB exits via conditional branch/fall-through but doesn't have "
630 "exactly two CFG successors!", MBB);
631 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
632 report("MBB exits via conditional branch/fall-through but the CFG "
633 "successors don't match the actual successors!", MBB);
636 report("MBB exits via conditional branch/fall-through but doesn't "
637 "contain any instructions!", MBB);
638 } else if (MBB->back().isBarrier()) {
639 report("MBB exits via conditional branch/fall-through but ends with a "
640 "barrier instruction!", MBB);
641 } else if (!MBB->back().isTerminator()) {
642 report("MBB exits via conditional branch/fall-through but the branch "
643 "isn't a terminator instruction!", MBB);
645 } else if (TBB && FBB) {
646 // Block conditionally branches somewhere, otherwise branches
648 if (MBB->succ_size() == 1) {
649 // A conditional branch with only one successor is weird, but allowed.
651 report("MBB exits via conditional branch/branch through but only has "
652 "one CFG successor!", MBB);
653 else if (TBB != *MBB->succ_begin())
654 report("MBB exits via conditional branch/branch through but the CFG "
655 "successor don't match the actual successor!", MBB);
656 } else if (MBB->succ_size() != 2) {
657 report("MBB exits via conditional branch/branch but doesn't have "
658 "exactly two CFG successors!", MBB);
659 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
660 report("MBB exits via conditional branch/branch but the CFG "
661 "successors don't match the actual successors!", MBB);
664 report("MBB exits via conditional branch/branch but doesn't "
665 "contain any instructions!", MBB);
666 } else if (!MBB->back().isBarrier()) {
667 report("MBB exits via conditional branch/branch but doesn't end with a "
668 "barrier instruction!", MBB);
669 } else if (!MBB->back().isTerminator()) {
670 report("MBB exits via conditional branch/branch but the branch "
671 "isn't a terminator instruction!", MBB);
674 report("MBB exits via conditinal branch/branch but there's no "
678 report("AnalyzeBranch returned invalid data!", MBB);
683 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
684 E = MBB->livein_end(); I != E; ++I) {
685 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
686 report("MBB live-in list contains non-physical register", MBB);
689 for (MCSubRegIterator SubRegs(*I, TRI, /*IncludeSelf=*/true);
690 SubRegs.isValid(); ++SubRegs)
691 regsLive.insert(*SubRegs);
693 regsLiveInButUnused = regsLive;
695 const MachineFrameInfo *MFI = MF->getFrameInfo();
696 assert(MFI && "Function has no frame info");
697 BitVector PR = MFI->getPristineRegs(*MF);
698 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
699 for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);
700 SubRegs.isValid(); ++SubRegs)
701 regsLive.insert(*SubRegs);
708 lastIndex = Indexes->getMBBStartIdx(MBB);
711 // This function gets called for all bundle headers, including normal
712 // stand-alone unbundled instructions.
713 void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
714 if (Indexes && Indexes->hasIndex(MI)) {
715 SlotIndex idx = Indexes->getInstructionIndex(MI);
716 if (!(idx > lastIndex)) {
717 report("Instruction index out of order", MI);
718 errs() << "Last instruction was at " << lastIndex << '\n';
723 // Ensure non-terminators don't follow terminators.
724 // Ignore predicated terminators formed by if conversion.
725 // FIXME: If conversion shouldn't need to violate this rule.
726 if (MI->isTerminator() && !TII->isPredicated(MI)) {
727 if (!FirstTerminator)
728 FirstTerminator = MI;
729 } else if (FirstTerminator) {
730 report("Non-terminator instruction after the first terminator", MI);
731 errs() << "First terminator was:\t" << *FirstTerminator;
735 // The operands on an INLINEASM instruction must follow a template.
736 // Verify that the flag operands make sense.
737 void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
738 // The first two operands on INLINEASM are the asm string and global flags.
739 if (MI->getNumOperands() < 2) {
740 report("Too few operands on inline asm", MI);
743 if (!MI->getOperand(0).isSymbol())
744 report("Asm string must be an external symbol", MI);
745 if (!MI->getOperand(1).isImm())
746 report("Asm flags must be an immediate", MI);
747 // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
748 // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16.
749 if (!isUInt<5>(MI->getOperand(1).getImm()))
750 report("Unknown asm flags", &MI->getOperand(1), 1);
752 static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
754 unsigned OpNo = InlineAsm::MIOp_FirstOperand;
756 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
757 const MachineOperand &MO = MI->getOperand(OpNo);
758 // There may be implicit ops after the fixed operands.
761 NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
764 if (OpNo > MI->getNumOperands())
765 report("Missing operands in last group", MI);
767 // An optional MDNode follows the groups.
768 if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
771 // All trailing operands must be implicit registers.
772 for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
773 const MachineOperand &MO = MI->getOperand(OpNo);
774 if (!MO.isReg() || !MO.isImplicit())
775 report("Expected implicit register after groups", &MO, OpNo);
779 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
780 const MCInstrDesc &MCID = MI->getDesc();
781 if (MI->getNumOperands() < MCID.getNumOperands()) {
782 report("Too few operands", MI);
783 errs() << MCID.getNumOperands() << " operands expected, but "
784 << MI->getNumOperands() << " given.\n";
787 // Check the tied operands.
788 if (MI->isInlineAsm())
791 // Check the MachineMemOperands for basic consistency.
792 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
793 E = MI->memoperands_end(); I != E; ++I) {
794 if ((*I)->isLoad() && !MI->mayLoad())
795 report("Missing mayLoad flag", MI);
796 if ((*I)->isStore() && !MI->mayStore())
797 report("Missing mayStore flag", MI);
800 // Debug values must not have a slot index.
801 // Other instructions must have one, unless they are inside a bundle.
803 bool mapped = !LiveInts->isNotInMIMap(MI);
804 if (MI->isDebugValue()) {
806 report("Debug instruction has a slot index", MI);
807 } else if (MI->isInsideBundle()) {
809 report("Instruction inside bundle has a slot index", MI);
812 report("Missing slot index", MI);
817 if (!TII->verifyInstruction(MI, ErrorInfo))
818 report(ErrorInfo.data(), MI);
822 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
823 const MachineInstr *MI = MO->getParent();
824 const MCInstrDesc &MCID = MI->getDesc();
825 unsigned NumDefs = MCID.getNumDefs();
826 if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
827 NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
829 // The first MCID.NumDefs operands must be explicit register defines
830 if (MONum < NumDefs) {
831 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
833 report("Explicit definition must be a register", MO, MONum);
834 else if (!MO->isDef() && !MCOI.isOptionalDef())
835 report("Explicit definition marked as use", MO, MONum);
836 else if (MO->isImplicit())
837 report("Explicit definition marked as implicit", MO, MONum);
838 } else if (MONum < MCID.getNumOperands()) {
839 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
840 // Don't check if it's the last operand in a variadic instruction. See,
841 // e.g., LDM_RET in the arm back end.
843 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
844 if (MO->isDef() && !MCOI.isOptionalDef())
845 report("Explicit operand marked as def", MO, MONum);
846 if (MO->isImplicit())
847 report("Explicit operand marked as implicit", MO, MONum);
850 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
853 report("Tied use must be a register", MO, MONum);
854 else if (!MO->isTied())
855 report("Operand should be tied", MO, MONum);
856 else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
857 report("Tied def doesn't match MCInstrDesc", MO, MONum);
858 } else if (MO->isReg() && MO->isTied())
859 report("Explicit operand should not be tied", MO, MONum);
861 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
862 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
863 report("Extra explicit operand on non-variadic instruction", MO, MONum);
866 switch (MO->getType()) {
867 case MachineOperand::MO_Register: {
868 const unsigned Reg = MO->getReg();
871 if (MRI->tracksLiveness() && !MI->isDebugValue())
872 checkLiveness(MO, MONum);
874 // Verify the consistency of tied operands.
876 unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
877 const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
878 if (!OtherMO.isReg())
879 report("Must be tied to a register", MO, MONum);
880 if (!OtherMO.isTied())
881 report("Missing tie flags on tied operand", MO, MONum);
882 if (MI->findTiedOperandIdx(OtherIdx) != MONum)
883 report("Inconsistent tie links", MO, MONum);
884 if (MONum < MCID.getNumDefs()) {
885 if (OtherIdx < MCID.getNumOperands()) {
886 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
887 report("Explicit def tied to explicit use without tie constraint",
890 if (!OtherMO.isImplicit())
891 report("Explicit def should be tied to implicit use", MO, MONum);
896 // Verify two-address constraints after leaving SSA form.
898 if (!MRI->isSSA() && MO->isUse() &&
899 MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
900 Reg != MI->getOperand(DefIdx).getReg())
901 report("Two-address instruction operands must be identical", MO, MONum);
903 // Check register classes.
904 if (MONum < MCID.getNumOperands() && !MO->isImplicit()) {
905 unsigned SubIdx = MO->getSubReg();
907 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
909 report("Illegal subregister index for physical register", MO, MONum);
912 if (const TargetRegisterClass *DRC =
913 TII->getRegClass(MCID, MONum, TRI, *MF)) {
914 if (!DRC->contains(Reg)) {
915 report("Illegal physical register for instruction", MO, MONum);
916 errs() << TRI->getName(Reg) << " is not a "
917 << TRI->getRegClassName(DRC) << " register.\n";
922 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
924 const TargetRegisterClass *SRC =
925 TRI->getSubClassWithSubReg(RC, SubIdx);
927 report("Invalid subregister index for virtual register", MO, MONum);
928 errs() << "Register class " << TRI->getRegClassName(RC)
929 << " does not support subreg index " << SubIdx << "\n";
933 report("Invalid register class for subregister index", MO, MONum);
934 errs() << "Register class " << TRI->getRegClassName(RC)
935 << " does not fully support subreg index " << SubIdx << "\n";
939 if (const TargetRegisterClass *DRC =
940 TII->getRegClass(MCID, MONum, TRI, *MF)) {
942 const TargetRegisterClass *SuperRC =
943 TRI->getLargestLegalSuperClass(RC, *MF);
945 report("No largest legal super class exists.", MO, MONum);
948 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
950 report("No matching super-reg register class.", MO, MONum);
954 if (!RC->hasSuperClassEq(DRC)) {
955 report("Illegal virtual register for instruction", MO, MONum);
956 errs() << "Expected a " << TRI->getRegClassName(DRC)
957 << " register, but got a " << TRI->getRegClassName(RC)
966 case MachineOperand::MO_RegisterMask:
967 regMasks.push_back(MO->getRegMask());
970 case MachineOperand::MO_MachineBasicBlock:
971 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
972 report("PHI operand is not in the CFG", MO, MONum);
975 case MachineOperand::MO_FrameIndex:
976 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
977 LiveInts && !LiveInts->isNotInMIMap(MI)) {
978 LiveInterval &LI = LiveStks->getInterval(MO->getIndex());
979 SlotIndex Idx = LiveInts->getInstructionIndex(MI);
980 if (MI->mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) {
981 report("Instruction loads from dead spill slot", MO, MONum);
982 errs() << "Live stack: " << LI << '\n';
984 if (MI->mayStore() && !LI.liveAt(Idx.getRegSlot())) {
985 report("Instruction stores to dead spill slot", MO, MONum);
986 errs() << "Live stack: " << LI << '\n';
996 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
997 const MachineInstr *MI = MO->getParent();
998 const unsigned Reg = MO->getReg();
1000 // Both use and def operands can read a register.
1001 if (MO->readsReg()) {
1002 regsLiveInButUnused.erase(Reg);
1005 addRegWithSubRegs(regsKilled, Reg);
1007 // Check that LiveVars knows this kill.
1008 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
1010 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1011 if (std::find(VI.Kills.begin(), VI.Kills.end(), MI) == VI.Kills.end())
1012 report("Kill missing from LiveVariables", MO, MONum);
1015 // Check LiveInts liveness and kill.
1016 if (LiveInts && !LiveInts->isNotInMIMap(MI)) {
1017 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI);
1018 // Check the cached regunit intervals.
1019 if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) {
1020 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
1021 if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units)) {
1022 LiveQueryResult LRQ = LR->Query(UseIdx);
1023 if (!LRQ.valueIn()) {
1024 report("No live segment at use", MO, MONum);
1025 errs() << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
1026 << ' ' << *LR << '\n';
1028 if (MO->isKill() && !LRQ.isKill()) {
1029 report("Live range continues after kill flag", MO, MONum);
1030 errs() << PrintRegUnit(*Units, TRI) << ' ' << *LR << '\n';
1036 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1037 if (LiveInts->hasInterval(Reg)) {
1038 // This is a virtual register interval.
1039 const LiveInterval &LI = LiveInts->getInterval(Reg);
1040 LiveQueryResult LRQ = LI.Query(UseIdx);
1041 if (!LRQ.valueIn()) {
1042 report("No live segment at use", MO, MONum);
1043 errs() << UseIdx << " is not live in " << LI << '\n';
1045 // Check for extra kill flags.
1046 // Note that we allow missing kill flags for now.
1047 if (MO->isKill() && !LRQ.isKill()) {
1048 report("Live range continues after kill flag", MO, MONum);
1049 errs() << "Live range: " << LI << '\n';
1052 report("Virtual register has no live interval", MO, MONum);
1057 // Use of a dead register.
1058 if (!regsLive.count(Reg)) {
1059 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1060 // Reserved registers may be used even when 'dead'.
1061 bool Bad = !isReserved(Reg);
1062 // We are fine if just any subregister has a defined value.
1064 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid();
1066 if (regsLive.count(*SubRegs)) {
1072 // If there is an additional implicit-use of a super register we stop
1073 // here. By definition we are fine if the super register is not
1074 // (completely) dead, if the complete super register is dead we will
1075 // get a report for its operand.
1077 for (const MachineOperand &MOP : MI->uses()) {
1080 if (!MOP.isImplicit())
1082 for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); SubRegs.isValid();
1084 if (*SubRegs == Reg) {
1092 report("Using an undefined physical register", MO, MONum);
1093 } else if (MRI->def_empty(Reg)) {
1094 report("Reading virtual register without a def", MO, MONum);
1096 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1097 // We don't know which virtual registers are live in, so only complain
1098 // if vreg was killed in this MBB. Otherwise keep track of vregs that
1099 // must be live in. PHI instructions are handled separately.
1100 if (MInfo.regsKilled.count(Reg))
1101 report("Using a killed virtual register", MO, MONum);
1102 else if (!MI->isPHI())
1103 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
1109 // Register defined.
1110 // TODO: verify that earlyclobber ops are not used.
1112 addRegWithSubRegs(regsDead, Reg);
1114 addRegWithSubRegs(regsDefined, Reg);
1117 if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
1118 std::next(MRI->def_begin(Reg)) != MRI->def_end())
1119 report("Multiple virtual register defs in SSA form", MO, MONum);
1121 // Check LiveInts for a live segment, but only for virtual registers.
1122 if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
1123 !LiveInts->isNotInMIMap(MI)) {
1124 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI);
1125 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
1126 if (LiveInts->hasInterval(Reg)) {
1127 const LiveInterval &LI = LiveInts->getInterval(Reg);
1128 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
1129 assert(VNI && "NULL valno is not allowed");
1130 if (VNI->def != DefIdx) {
1131 report("Inconsistent valno->def", MO, MONum);
1132 errs() << "Valno " << VNI->id << " is not defined at "
1133 << DefIdx << " in " << LI << '\n';
1136 report("No live segment at def", MO, MONum);
1137 errs() << DefIdx << " is not live in " << LI << '\n';
1139 // Check that, if the dead def flag is present, LiveInts agree.
1141 LiveQueryResult LRQ = LI.Query(DefIdx);
1142 if (!LRQ.isDeadDef()) {
1143 report("Live range continues after dead def flag", MO, MONum);
1144 errs() << "Live range: " << LI << '\n';
1148 report("Virtual register has no Live interval", MO, MONum);
1154 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
1157 // This function gets called after visiting all instructions in a bundle. The
1158 // argument points to the bundle header.
1159 // Normal stand-alone instructions are also considered 'bundles', and this
1160 // function is called for all of them.
1161 void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
1162 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1163 set_union(MInfo.regsKilled, regsKilled);
1164 set_subtract(regsLive, regsKilled); regsKilled.clear();
1165 // Kill any masked registers.
1166 while (!regMasks.empty()) {
1167 const uint32_t *Mask = regMasks.pop_back_val();
1168 for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
1169 if (TargetRegisterInfo::isPhysicalRegister(*I) &&
1170 MachineOperand::clobbersPhysReg(Mask, *I))
1171 regsDead.push_back(*I);
1173 set_subtract(regsLive, regsDead); regsDead.clear();
1174 set_union(regsLive, regsDefined); regsDefined.clear();
1178 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
1179 MBBInfoMap[MBB].regsLiveOut = regsLive;
1183 SlotIndex stop = Indexes->getMBBEndIdx(MBB);
1184 if (!(stop > lastIndex)) {
1185 report("Block ends before last instruction index", MBB);
1186 errs() << "Block ends at " << stop
1187 << " last instruction was at " << lastIndex << '\n';
1193 // Calculate the largest possible vregsPassed sets. These are the registers that
1194 // can pass through an MBB live, but may not be live every time. It is assumed
1195 // that all vregsPassed sets are empty before the call.
1196 void MachineVerifier::calcRegsPassed() {
1197 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
1198 // have any vregsPassed.
1199 SmallPtrSet<const MachineBasicBlock*, 8> todo;
1200 for (const auto &MBB : *MF) {
1201 BBInfo &MInfo = MBBInfoMap[&MBB];
1202 if (!MInfo.reachable)
1204 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
1205 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
1206 BBInfo &SInfo = MBBInfoMap[*SuI];
1207 if (SInfo.addPassed(MInfo.regsLiveOut))
1212 // Iteratively push vregsPassed to successors. This will converge to the same
1213 // final state regardless of DenseSet iteration order.
1214 while (!todo.empty()) {
1215 const MachineBasicBlock *MBB = *todo.begin();
1217 BBInfo &MInfo = MBBInfoMap[MBB];
1218 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
1219 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
1222 BBInfo &SInfo = MBBInfoMap[*SuI];
1223 if (SInfo.addPassed(MInfo.vregsPassed))
1229 // Calculate the set of virtual registers that must be passed through each basic
1230 // block in order to satisfy the requirements of successor blocks. This is very
1231 // similar to calcRegsPassed, only backwards.
1232 void MachineVerifier::calcRegsRequired() {
1233 // First push live-in regs to predecessors' vregsRequired.
1234 SmallPtrSet<const MachineBasicBlock*, 8> todo;
1235 for (const auto &MBB : *MF) {
1236 BBInfo &MInfo = MBBInfoMap[&MBB];
1237 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
1238 PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
1239 BBInfo &PInfo = MBBInfoMap[*PrI];
1240 if (PInfo.addRequired(MInfo.vregsLiveIn))
1245 // Iteratively push vregsRequired to predecessors. This will converge to the
1246 // same final state regardless of DenseSet iteration order.
1247 while (!todo.empty()) {
1248 const MachineBasicBlock *MBB = *todo.begin();
1250 BBInfo &MInfo = MBBInfoMap[MBB];
1251 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1252 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1255 BBInfo &SInfo = MBBInfoMap[*PrI];
1256 if (SInfo.addRequired(MInfo.vregsRequired))
1262 // Check PHI instructions at the beginning of MBB. It is assumed that
1263 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
1264 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
1265 SmallPtrSet<const MachineBasicBlock*, 8> seen;
1266 for (const auto &BBI : *MBB) {
1271 for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2) {
1272 unsigned Reg = BBI.getOperand(i).getReg();
1273 const MachineBasicBlock *Pre = BBI.getOperand(i + 1).getMBB();
1274 if (!Pre->isSuccessor(MBB))
1277 BBInfo &PrInfo = MBBInfoMap[Pre];
1278 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
1279 report("PHI operand is not live-out from predecessor",
1280 &BBI.getOperand(i), i);
1283 // Did we see all predecessors?
1284 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1285 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1286 if (!seen.count(*PrI)) {
1287 report("Missing PHI operand", &BBI);
1288 errs() << "BB#" << (*PrI)->getNumber()
1289 << " is a predecessor according to the CFG.\n";
1295 void MachineVerifier::visitMachineFunctionAfter() {
1298 for (const auto &MBB : *MF) {
1299 BBInfo &MInfo = MBBInfoMap[&MBB];
1301 // Skip unreachable MBBs.
1302 if (!MInfo.reachable)
1308 // Now check liveness info if available
1311 // Check for killed virtual registers that should be live out.
1312 for (const auto &MBB : *MF) {
1313 BBInfo &MInfo = MBBInfoMap[&MBB];
1314 for (RegSet::iterator
1315 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1317 if (MInfo.regsKilled.count(*I)) {
1318 report("Virtual register killed in block, but needed live out.", &MBB);
1319 errs() << "Virtual register " << PrintReg(*I)
1320 << " is used after the block.\n";
1325 BBInfo &MInfo = MBBInfoMap[&MF->front()];
1326 for (RegSet::iterator
1327 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1329 report("Virtual register def doesn't dominate all uses.",
1330 MRI->getVRegDef(*I));
1334 verifyLiveVariables();
1336 verifyLiveIntervals();
1339 void MachineVerifier::verifyLiveVariables() {
1340 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
1341 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1342 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1343 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1344 for (const auto &MBB : *MF) {
1345 BBInfo &MInfo = MBBInfoMap[&MBB];
1347 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
1348 if (MInfo.vregsRequired.count(Reg)) {
1349 if (!VI.AliveBlocks.test(MBB.getNumber())) {
1350 report("LiveVariables: Block missing from AliveBlocks", &MBB);
1351 errs() << "Virtual register " << PrintReg(Reg)
1352 << " must be live through the block.\n";
1355 if (VI.AliveBlocks.test(MBB.getNumber())) {
1356 report("LiveVariables: Block should not be in AliveBlocks", &MBB);
1357 errs() << "Virtual register " << PrintReg(Reg)
1358 << " is not needed live through the block.\n";
1365 void MachineVerifier::verifyLiveIntervals() {
1366 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
1367 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1368 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1370 // Spilling and splitting may leave unused registers around. Skip them.
1371 if (MRI->reg_nodbg_empty(Reg))
1374 if (!LiveInts->hasInterval(Reg)) {
1375 report("Missing live interval for virtual register", MF);
1376 errs() << PrintReg(Reg, TRI) << " still has defs or uses\n";
1380 const LiveInterval &LI = LiveInts->getInterval(Reg);
1381 assert(Reg == LI.reg && "Invalid reg to interval mapping");
1382 verifyLiveInterval(LI);
1385 // Verify all the cached regunit intervals.
1386 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
1387 if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
1388 verifyLiveRange(*LR, i);
1391 void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
1392 const VNInfo *VNI, unsigned Reg,
1393 unsigned LaneMask) {
1394 if (VNI->isUnused())
1397 const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
1400 report("Valno not live at def and not marked unused", MF, LR, Reg,
1402 errs() << "Valno #" << VNI->id << '\n';
1406 if (DefVNI != VNI) {
1407 report("Live segment at def has different valno", MF, LR, Reg, LaneMask);
1408 errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
1409 << " where valno #" << DefVNI->id << " is live\n";
1413 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
1415 report("Invalid definition index", MF, LR, Reg, LaneMask);
1416 errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
1417 << " in " << LR << '\n';
1421 if (VNI->isPHIDef()) {
1422 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
1423 report("PHIDef value is not defined at MBB start", MBB, LR, Reg,
1425 errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
1426 << ", not at the beginning of BB#" << MBB->getNumber() << '\n';
1432 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
1434 report("No instruction at def index", MBB, LR, Reg, LaneMask);
1435 errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1440 bool hasDef = false;
1441 bool isEarlyClobber = false;
1442 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1443 if (!MOI->isReg() || !MOI->isDef())
1445 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1446 if (MOI->getReg() != Reg)
1449 if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
1450 !TRI->hasRegUnit(MOI->getReg(), Reg))
1453 if (LaneMask != 0 &&
1454 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask) == 0)
1457 if (MOI->isEarlyClobber())
1458 isEarlyClobber = true;
1462 report("Defining instruction does not modify register", MI);
1463 errs() << "Valno #" << VNI->id << " in " << LR << '\n';
1466 // Early clobber defs begin at USE slots, but other defs must begin at
1468 if (isEarlyClobber) {
1469 if (!VNI->def.isEarlyClobber()) {
1470 report("Early clobber def must be at an early-clobber slot", MBB, LR,
1472 errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1474 } else if (!VNI->def.isRegister()) {
1475 report("Non-PHI, non-early clobber def must be at a register slot",
1476 MBB, LR, Reg, LaneMask);
1477 errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1482 void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
1483 const LiveRange::const_iterator I,
1484 unsigned Reg, unsigned LaneMask) {
1485 const LiveRange::Segment &S = *I;
1486 const VNInfo *VNI = S.valno;
1487 assert(VNI && "Live segment has no valno");
1489 if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
1490 report("Foreign valno in live segment", MF, LR, Reg, LaneMask);
1491 errs() << S << " has a bad valno\n";
1494 if (VNI->isUnused()) {
1495 report("Live segment valno is marked unused", MF, LR, Reg, LaneMask);
1496 errs() << S << '\n';
1499 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
1501 report("Bad start of live segment, no basic block", MF, LR, Reg, LaneMask);
1502 errs() << S << '\n';
1505 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
1506 if (S.start != MBBStartIdx && S.start != VNI->def) {
1507 report("Live segment must begin at MBB entry or valno def", MBB, LR, Reg,
1509 errs() << S << '\n';
1512 const MachineBasicBlock *EndMBB =
1513 LiveInts->getMBBFromIndex(S.end.getPrevSlot());
1515 report("Bad end of live segment, no basic block", MF, LR, Reg, LaneMask);
1516 errs() << S << '\n';
1520 // No more checks for live-out segments.
1521 if (S.end == LiveInts->getMBBEndIdx(EndMBB))
1524 // RegUnit intervals are allowed dead phis.
1525 if (!TargetRegisterInfo::isVirtualRegister(Reg) && VNI->isPHIDef() &&
1526 S.start == VNI->def && S.end == VNI->def.getDeadSlot())
1529 // The live segment is ending inside EndMBB
1530 const MachineInstr *MI =
1531 LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
1533 report("Live segment doesn't end at a valid instruction", EndMBB, LR, Reg,
1535 errs() << S << '\n';
1539 // The block slot must refer to a basic block boundary.
1540 if (S.end.isBlock()) {
1541 report("Live segment ends at B slot of an instruction", EndMBB, LR, Reg,
1543 errs() << S << '\n';
1546 if (S.end.isDead()) {
1547 // Segment ends on the dead slot.
1548 // That means there must be a dead def.
1549 if (!SlotIndex::isSameInstr(S.start, S.end)) {
1550 report("Live segment ending at dead slot spans instructions", EndMBB, LR,
1552 errs() << S << '\n';
1556 // A live segment can only end at an early-clobber slot if it is being
1557 // redefined by an early-clobber def.
1558 if (S.end.isEarlyClobber()) {
1559 if (I+1 == LR.end() || (I+1)->start != S.end) {
1560 report("Live segment ending at early clobber slot must be "
1561 "redefined by an EC def in the same instruction", EndMBB, LR, Reg,
1563 errs() << S << '\n';
1567 // The following checks only apply to virtual registers. Physreg liveness
1568 // is too weird to check.
1569 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1570 // A live segment can end with either a redefinition, a kill flag on a
1571 // use, or a dead flag on a def.
1572 bool hasRead = false;
1573 bool hasSubRegDef = false;
1574 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1575 if (!MOI->isReg() || MOI->getReg() != Reg)
1577 if (LaneMask != 0 &&
1578 (LaneMask & TRI->getSubRegIndexLaneMask(MOI->getSubReg())) == 0)
1580 if (MOI->isDef() && MOI->getSubReg() != 0)
1581 hasSubRegDef = true;
1582 if (MOI->readsReg())
1585 if (!S.end.isDead()) {
1587 // When tracking subregister liveness, the main range must start new
1588 // values on partial register writes, even if there is no read.
1589 if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask != 0 ||
1591 report("Instruction ending live segment doesn't read the register",
1593 errs() << S << " in " << LR << '\n';
1599 // Now check all the basic blocks in this live segment.
1600 MachineFunction::const_iterator MFI = MBB;
1601 // Is this live segment the beginning of a non-PHIDef VN?
1602 if (S.start == VNI->def && !VNI->isPHIDef()) {
1603 // Not live-in to any blocks.
1610 assert(LiveInts->isLiveInToMBB(LR, MFI));
1611 // We don't know how to track physregs into a landing pad.
1612 if (!TargetRegisterInfo::isVirtualRegister(Reg) &&
1613 MFI->isLandingPad()) {
1614 if (&*MFI == EndMBB)
1620 // Is VNI a PHI-def in the current block?
1621 bool IsPHI = VNI->isPHIDef() &&
1622 VNI->def == LiveInts->getMBBStartIdx(MFI);
1624 // Check that VNI is live-out of all predecessors.
1625 for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
1626 PE = MFI->pred_end(); PI != PE; ++PI) {
1627 SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
1628 const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
1630 // All predecessors must have a live-out value.
1632 report("Register not marked live out of predecessor", *PI, LR, Reg,
1634 errs() << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
1635 << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before "
1640 // Only PHI-defs can take different predecessor values.
1641 if (!IsPHI && PVNI != VNI) {
1642 report("Different value live out of predecessor", *PI, LR, Reg,
1644 errs() << "Valno #" << PVNI->id << " live out of BB#"
1645 << (*PI)->getNumber() << '@' << PEnd
1646 << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
1647 << '@' << LiveInts->getMBBStartIdx(MFI) << '\n';
1650 if (&*MFI == EndMBB)
1656 void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
1657 unsigned LaneMask) {
1658 for (const VNInfo *VNI : LR.valnos)
1659 verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
1661 for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
1662 verifyLiveRangeSegment(LR, I, Reg, LaneMask);
1665 void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
1666 unsigned Reg = LI.reg;
1667 assert(TargetRegisterInfo::isVirtualRegister(Reg));
1668 verifyLiveRange(LI, Reg);
1671 unsigned MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
1672 for (const LiveInterval::SubRange &SR : LI.subranges()) {
1673 if ((Mask & SR.LaneMask) != 0)
1674 report("Lane masks of sub ranges overlap in live interval", MF, LI);
1675 if ((SR.LaneMask & ~MaxMask) != 0)
1676 report("Subrange lanemask is invalid", MF, LI);
1678 report("Subrange must not be empty", MF, SR, LI.reg, SR.LaneMask);
1679 Mask |= SR.LaneMask;
1680 verifyLiveRange(SR, LI.reg, SR.LaneMask);
1682 report("A Subrange is not covered by the main range", MF, LI);
1685 // Check the LI only has one connected component.
1686 ConnectedVNInfoEqClasses ConEQ(*LiveInts);
1687 unsigned NumComp = ConEQ.Classify(&LI);
1689 report("Multiple connected components in live interval", MF, LI);
1690 for (unsigned comp = 0; comp != NumComp; ++comp) {
1691 errs() << comp << ": valnos";
1692 for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
1693 E = LI.vni_end(); I!=E; ++I)
1694 if (comp == ConEQ.getEqClass(*I))
1695 errs() << ' ' << (*I)->id;
1702 // FrameSetup and FrameDestroy can have zero adjustment, so using a single
1703 // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
1705 // We use a bool plus an integer to capture the stack state.
1706 struct StackStateOfBB {
1707 StackStateOfBB() : EntryValue(0), ExitValue(0), EntryIsSetup(false),
1708 ExitIsSetup(false) { }
1709 StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
1710 EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
1711 ExitIsSetup(ExitSetup) { }
1712 // Can be negative, which means we are setting up a frame.
1720 /// Make sure on every path through the CFG, a FrameSetup <n> is always followed
1721 /// by a FrameDestroy <n>, stack adjustments are identical on all
1722 /// CFG edges to a merge point, and frame is destroyed at end of a return block.
1723 void MachineVerifier::verifyStackFrame() {
1724 unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
1725 unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
1727 SmallVector<StackStateOfBB, 8> SPState;
1728 SPState.resize(MF->getNumBlockIDs());
1729 SmallPtrSet<const MachineBasicBlock*, 8> Reachable;
1731 // Visit the MBBs in DFS order.
1732 for (df_ext_iterator<const MachineFunction*,
1733 SmallPtrSet<const MachineBasicBlock*, 8> >
1734 DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
1735 DFI != DFE; ++DFI) {
1736 const MachineBasicBlock *MBB = *DFI;
1738 StackStateOfBB BBState;
1739 // Check the exit state of the DFS stack predecessor.
1740 if (DFI.getPathLength() >= 2) {
1741 const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
1742 assert(Reachable.count(StackPred) &&
1743 "DFS stack predecessor is already visited.\n");
1744 BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
1745 BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
1746 BBState.ExitValue = BBState.EntryValue;
1747 BBState.ExitIsSetup = BBState.EntryIsSetup;
1750 // Update stack state by checking contents of MBB.
1751 for (const auto &I : *MBB) {
1752 if (I.getOpcode() == FrameSetupOpcode) {
1753 // The first operand of a FrameOpcode should be i32.
1754 int Size = I.getOperand(0).getImm();
1756 "Value should be non-negative in FrameSetup and FrameDestroy.\n");
1758 if (BBState.ExitIsSetup)
1759 report("FrameSetup is after another FrameSetup", &I);
1760 BBState.ExitValue -= Size;
1761 BBState.ExitIsSetup = true;
1764 if (I.getOpcode() == FrameDestroyOpcode) {
1765 // The first operand of a FrameOpcode should be i32.
1766 int Size = I.getOperand(0).getImm();
1768 "Value should be non-negative in FrameSetup and FrameDestroy.\n");
1770 if (!BBState.ExitIsSetup)
1771 report("FrameDestroy is not after a FrameSetup", &I);
1772 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
1774 if (BBState.ExitIsSetup && AbsSPAdj != Size) {
1775 report("FrameDestroy <n> is after FrameSetup <m>", &I);
1776 errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
1777 << AbsSPAdj << ">.\n";
1779 BBState.ExitValue += Size;
1780 BBState.ExitIsSetup = false;
1783 SPState[MBB->getNumber()] = BBState;
1785 // Make sure the exit state of any predecessor is consistent with the entry
1787 for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
1788 E = MBB->pred_end(); I != E; ++I) {
1789 if (Reachable.count(*I) &&
1790 (SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
1791 SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
1792 report("The exit stack state of a predecessor is inconsistent.", MBB);
1793 errs() << "Predecessor BB#" << (*I)->getNumber() << " has exit state ("
1794 << SPState[(*I)->getNumber()].ExitValue << ", "
1795 << SPState[(*I)->getNumber()].ExitIsSetup
1796 << "), while BB#" << MBB->getNumber() << " has entry state ("
1797 << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
1801 // Make sure the entry state of any successor is consistent with the exit
1803 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
1804 E = MBB->succ_end(); I != E; ++I) {
1805 if (Reachable.count(*I) &&
1806 (SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
1807 SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
1808 report("The entry stack state of a successor is inconsistent.", MBB);
1809 errs() << "Successor BB#" << (*I)->getNumber() << " has entry state ("
1810 << SPState[(*I)->getNumber()].EntryValue << ", "
1811 << SPState[(*I)->getNumber()].EntryIsSetup
1812 << "), while BB#" << MBB->getNumber() << " has exit state ("
1813 << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
1817 // Make sure a basic block with return ends with zero stack adjustment.
1818 if (!MBB->empty() && MBB->back().isReturn()) {
1819 if (BBState.ExitIsSetup)
1820 report("A return block ends with a FrameSetup.", MBB);
1821 if (BBState.ExitValue)
1822 report("A return block ends with a nonzero stack adjustment.", MBB);